PC-BASED MEASUREMENT AND

CONTROL

CHAPTER 7: EMBEDDED INTERFACE

CONTENTS
PhD. NGUYỄN HOÀNG GIÁP
Outline
➢ UART
➢ l2C
➢ SPI
UART
➢ Universal Asynchronous Receiver/Transmitter
➢ Was discussed in detail in RS232 lectures
Outline
➢ UART and USART
➢ l2C
➢ SPI
I2C bus
➢ I2C: Inter-Integrated Circuit
✓ It was developed by Philips Semiconductor in 1980 for
intercommunication between partial blocks inside one device.
✓ Atmel Corporation titles I2C as TWI (Two-Wire serial Interface)
✓ I2C is a half-duplex synchronous serial interface chỉ có 1 chân gửi và nhận

➢ The communication protocol of I2C allows connection of up to 128

devices via pair of bidirectional wires:
✓ SDA: Serial Data
✓ SCL: Serial Clock
➢ Every wire contains a pull-up resistor, thus in idle state the lines arc high.
I2C communication protocol
➢ Master Device
✓ This device generates the clock signal and starts and controls
all communication.
➢ Slave devices
✓ These devices are controlled by master's clock signal and is
being addressed by the master device.
➢ Communication is started by Start Condition, and is ended by
stop Condition.
➢ There are two types of communication frames:
✓ Address
✓ Data
Start and stop Conditions
➢ Every bit transmission is controlled by one period of clock (SCL)
➢ The level of SDA must be stable while clock signal is high.
➢ Only exceptions are start and stop conditions:
I2C address packet
➢ All address packets are 9-bit wide and contain
✓ 7-bit slave address
✓ one R/W control bit (1: read, O:write)
✓ One acknowledge bit (ACK)
➢ Acknowledge bit is sent by the slave device if the address was recognized
and it is ready for further communication.
➢ Address bits are organized in order form MSB to LSB.
A Combination of address and data packets:

s Typical communication via I2C bus starts by start condition, followed by slave device
addressing, one or more data packets, and ends by stop condition.
Master write transaction
➢ If the master writes to the slave device, the data transfer direction is not
changed.

➢ If the master needs to communicate with other slaves it can generate a

repeated start with another slave address without generating stop
condition.
Master read transaction
➢ If the master needs to read from the slave device, it sends the I2C
address with the R/W bit set to read. After this the master device
starts reading the data.
Master combined write and read transaction
➢ A master may need to write some data and then read from the slave
device.
➢ In such cases it must first write to the slave device, change the data
transfer direction, and then read the device.
➢ The master may uses a repeated start to avoid losing the bus after the
first packet.
I2C physical layer

➢ Both SCL and SDA lines are of open-drain

✓ Thus, pull-up resistors are needed.

➢ Pulling the line to ground is considered a logical zero while letting the line
float is a logical one.
➢ Multiple nodes may be driving the lines simultaneously. If ơnỵ node is
driving the line low, it will be low.
✓ Nodes that are trying to transmit a logical one (i.e. letting the line float
high) can see this, and thereby know that another node is active at the
same time.
✓ When used on SCL, this is called clock stretching and gives slaves a
flow control mechanism.
✓ When used on SDA, this is called arbitration and ensures there is only
one transmitter at a time.
Clock stretching
➢ An addressed slave device may hold the clock line (SCL) low after
receiving (or sending) a byte, indicating that it is not yet ready to
process more data.
✓ The master that is communicating with the slave may not finish the
transmission of the current bit, but must wait until the clock line
actually goes high.
➢ Clock stretching is the only time in l2C where the slave drives SCL.
I2C clock speed
➢ Standard mode: 100 kbps
➢ Low-speed mode: 10 kbps, but arbitrarily low clock frequencies are
also allowed.
➢ Fast mode: 400 kbps
➢ Fast mode plus (FM+) : 1Mbps
➢ High Speed: 3.4 Mbps
Bus arbitration
➢ The l2C bus is a multi-master bus
✓ It means more than one IC/device capable of initiating a data transfer
can be connected to it.
➢ Only two devices exchange data during one conversation.
➢ Every master monitors the bus for start and stop bits, and does not start a
message while another master is keeping the bus busy.
➢ Two masters may start transmission at about the same time
✓ If master1 sets SDA to 1 (not driving) and master2 sets it to 0 (pull to
ground), the line will be low.
✓ Master1 observes that the line is different from expected another node
is transmitting → stops driving SDA and SCL.
✓ It waits for a STOP; then it may try to reissue its entire message.
✓ Master2 can continue without any problem.
7-bit I2C addressing
➢ The allocation of I2C addresses is administered by the I2C bus
committee.
➢ Some addresses are reserved for specific purposes or future uses

➢ → only 112 addresses can actually be used.

10-bit I2C addressing
➢ Added to the new versions of I2C to support more slave devices.
➢ 10-bit addressing can be used together with 7-bit addressing
✓ A special 7-bit address (1111OXX) is used to signal 10-bit I2C address.
✓ If the master wants to write data to the slave device, it must send the
remaining 8 bits of slave address as the second byte.

✓ If the master wants to read data from slave, it must send the complete 10-bit
address (two bytes) as for writing, then a repeated start is sent followed by the
first address byte with read/write bit set to high to signal reading. After this
procedure the data can be read from the slave device.
Example: l2C serial EEPROM
➢ Microchip 24LC515 Serial EEPROM
✓ 64K x 8 (512Kbit)
✓ Clock up to 400 KHZ
✓ Data Retention >200 years
✓ 64-Byte page write buffer
➢ The 24LC515 is a 64KB memory which would require 16 address lines,
and 8 data lines if a parallel interface was used!
✓ → many pins if parallel interface is used!
➢ Putting a serial interface on a memory device lowers the required pin
count.
24LC515 addressing
➢ Upper 4 bits of the device address are assigned by manufacturer and are
hardcoded in the device (1010b). Lower 3 bits are used in different ways:
✓ A2 should be hardwired to VCC. A1 and A0 are software configurable.
24LC515 byte write operation

➢ Used to write one byte

✓ Send Control Byte, high address byte, low address byte, data.
✓ After data is sent, takes 5 ms for write to complete (slow!)
24LC515 page write operation
➢ Send a block of 64 bytes, then perform write
✓ Send starting address, followed by 64 bytes
✓ After 64 bytes are sent, wait 5 ms for write to complete s Much faster
than individual writes
➢ Address should be on a page boundary.
✓ For page size = 64 = 0x40, starting address should be a multiple of 64.
24LC515 write speed comparison
➢ Assume a 400 Khz I2C bus → 2.5 s clock period
➢ Byte write:
✓ 9 bit transmission = 2.5 s * 9 = 22.5 s
✓ 5 ms + 22.5 s* 4 (control+add_high+add_low+data) =5.09 ms
✓ :or 64 bytes = 325 ms approximately, not counting software overhead.
➢ Page Write
✓ 67 bytes total (control+add_high+add_low+data)
✓ 5 ms + 67 * 22 5 s = 6.5 ms !!!
24LC515 read operation: current address
➢ An internal counter is used to keep track of the last used address
➢ A current address read uses this address, thus only sends the
command byte
✓ Internal counter incremented after read operation
24LC515 random read operation
➢ Must first set the internal address counter by starting a write operation,
but aborting by not sending data byte
address packet
24LC515 sequential read
➢ Like a current address read, but after Slave sends data byte, Master
sends ACK instead of STOP
✓ Slave then sends next byte
✓ Can do this from 0x0000h to 0x7FFF (lower 32K block), when
0x7FFF is reached, address rolls over to 0x0000.
✓ Upper block goes from 0x8000 to 0xFFFF; at 0xFFFF address rolls
over to 0x8000.
✓ Internal address counter is only 15 bits wide.
Bit-banging the I2C master protocol
➢ Implementation of I2C interface in software.
➢ Assume the following hardware-specific functions are available:
✓ [From Wikipedia]
Start condition
Stop condition
I2C bit write
I2C bit read
I2C byte write
I2C byte read
Outline
➢ UART
➢ I2C
➢ SPI
SPI interface
➢ SPI: Serial Peripheral Interface
✓ Originally developed by Motorola
✓ Sometimes SPI is also called a "four wire" serial bus
✓ SPI is a 4-wire full duplex synchronous serial interface
➢ SPI is developed primarily for the communication between host processor
and peripherals
✓ E.g., MCU to external memory, sensors, ADC and DAC, control
devices, real-time clocks, etc. J Connection of two processors via SPI is
possible as well.
➢ de facto standard: since there isn't a formal standard, there are some
variations among devices, such as
✓ word size
✓ polarity of clock and select signals
✓ LSB first or MSB first
→ the SPI system has options to select among these variations
SPI facts
➢ High speed serial communications (12 Mbits/sec) interface
✓ Higher speed than I2C, but requires more pins!
➢ The SPI Bus is usually used only on the PCB.
✓ Due to this high-speed aspect, the bus lines cannot be too long.
➢ Both single-master and multi-master protocols are possible in SPI
✓ The multi-master bus is rarely used and look awkward
SPI principles of operation

➢ One device is the "master" (typically the MCU), and generates the clock

signal

➢ There are one or more "slaves" (typically peripheral chips)

➢ Data is shifted serially from a shift register in the master to a shift register

in the slave

➢ The shift registers are connected in a "ring" configuration

➢ when the master shifts its data to the slave, it automatically gets back the
data that was in the slave's shift register
SPI signals
➢ MOSI (Master Out, Slave In)
✓ MOSI connects to MOSI
✓ Is an output on master, input on slaves
➢ MISO (Master In, Slave Out)
✓ MISO connects to MISO
✓ Is an input on master, output on slaves
✓ If a slave is not selected, the slave makes its output high impedance (so
other slaves can use that line)
➢ SCK (Serial Clock)
✓ Generated by master, input to slaves
✓ Only runs when master wants to transmit data
➢ SS (Slave Select)
✓ Generated by master, used to select (enable) a slave
✓ When SS is asserted, the slave will transfer contents of its shift register
Bi-directional synchronous communications
➢ To send (or receive) an 8-bit word, the master generates 8 pulses of
the clock (SCK)
Multiple slaves - method 1

➢ In this method, the master uses multiple signals to individually select

each slave
➢ Only the selected slave may transmit on the MISO line
Multiple slaves - method 2
➢ In this method, the master and all the slaves are on a giant ring
✓ data is shuttled through all of them
➢ There is no way to individually access a particular slave
✓ If the master wants to send data to slave 1, say, it has to go
through slave 0
SPI clock signal
➢ There are four possible combinations of clock
polarity and phase
➢ CPOL-Clock polarity
➢ CPHA-Clock phase
SPI advantages and disadvantages
➢ Advantages of SPI
✓ Full duplex communication
✓ Higher throughput than l2C protocol
✓ Not limited to 8-bit words in the case of bit-transferring s Simple hardware
interfacing
✓ Typically lower power requirements than l2C due to less circuitry.
✓ No arbitration or associated failure modes.
✓ Slaves use the master's clock, and don't need precision oscillators.
➢ Disadvantages of SPI
✓ Requires more pins on IC packages than l2C
✓ No slave acknowledgment
✓ Without a formal standard, validating conformance is not possible
✓ Only handles short distances compared to RS-232, RS-485, or CAN.
Example SPI-compatible chips
➢ TC72 digital thermometer
✓ 10 bit resolution
✓ Least significant bit (LSB) corresponds to 0.25 degrees C
➢ MCP4922 D/A converter
✓ 12-bit serial data in
✓ analog voltage out
➢ ADE7753 multifunction metering IC
✓ Active, reactive, and apparent energy measurements, line-voltage period
measurement, and RMS calculation on the voltage and current.
✓ Temperature sensor
➢ MAX6952 LED display driver
✓ for 5x7 matrix displays
✓ Other matrix sizes are possible; also multiple colors
➢ 25AA256 EEPROM
✓ 256 Kbit
Example - TC72 digital thermometer
➢ Ten-bit resolution and SPI interface
➢ Capable of reading temperature from -55 to 125 degrees C
➢ Can be used in continuous temperature conversion or one-shot
conversion mode
Example: SPI interface in ATMEL AVRs
➢ The AVR contains the following three registers that deal with SPI:

➢ SPCR - SPI Control Register

✓ contains the bits to initialize SPI and control it.

➢ SPSR - SPI Status Register

✓ is used to read the status of the bus lines.

➢ SPDR-SPI Data Register

✓ is the read/write register where the actual data transfer takes place.
AVR SPI control register
➢ Bit 7: SPIE - SPI Interrupt Enable
✓ To enable interrupts in the SPI
➢ Bit 6: SPE-SPI Enable
✓ To enable SPI as a whole. When SPI is enabled, the normal I/o functions of the
pins are overridden
➢ Bit 5: DORD - Data Order
✓ 1: LSB first, 0: MSB first
➢ Bit 4: MSTR - Master/Slave Select
✓ To configure the device as Master or as Slave. 1: Master mode, 0: Slave mode.
➢ Bit 3: CPOL-Clock Polarity
✓ 1: SCK is HIGH when the bus is idle, 0: SCK is LOW in case of idle bus.
➢ Bit 2: CPHA-Clock Phase
✓ 1: to sample data at the leading (first) edge of SCK, 0: to sample data at the
trailing (second) edge of SCK.
➢ Bit 1,0: SPR1, SPRO - SPI Clock Rate Select
✓ These bits, along with a SPI2X bit in the SPSR register, are used to choose the
oscillator frequency divider.
AVR SPI status register
➢ Bit 7: SPIF-SPI Interrupt Flag
✓ is set whenever a serial transfer is complete. An interrupt is also
generated if SPIE bit (bit 7 in SPCR) is enabled and global interrupts are
enabled.
➢ Bit 6: WCOL-Write Collision Flag
✓ is set when data is written on the SPI Data Register (SPDR) when there is
an impending transfer or the data lines are busy.
➢ Bit 5:1 - Reserved bits
➢ Bit 0: SPI2x - SPI Double Speed Mode
✓ reduces the frequency divider from 4x to 2x, hence doubling the speed.
Set this bit to 1 to enable SPI Double Speed Mode. This bit is used in
conjunction with the SPR1:0 bits of SPCR Register.
Sample ATMEL AVR SPI code
SPI and ISP
➢ ISP: In-System Programming
✓ Allows programming and reprogramming of any AVR microcontroller
positioned inside the end system.
✓ ISP eliminates the physical removal of chips from the system for
reprogramming.
➢ ISP uses the SPI signals for programming the chip.
ISP
➢ To avoid problems, the In-System Programmer should be able to keep the
entire Target System Reset for the duration of the programming cycle.