A

course
for
[Link]. CSIT
Year/Part: I/II
Subject: Microprocessor
Unit 7:Advanced Microprocessor

Presented
BY
Er. Ganesh Kumal
 Contents
• 80286: Architecture (Block Diagram) ,
Registers, (Real/Protected mode), Privilege
Levels, Descriptor Cache, Memory Access in
GDT and LDT, Multitasking, Addressing Modes,
Flag Register
• 80386: Architecture (Block Diagram), Register
organization, Memory Access in Protected
Mode, Paging (Up to LA to PA)

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 80286
• Introduced in 1982
• 80286 is the first member of the family of
advanced microprocessor.
• Various versions of 80286 are available that run
on 12.5 MHz, 10 MHz and 8 MHz clock frequency.
• It is 16-bit microprocessor and 24-bit address
lines and able to address 16MB of memory.
• Multi tasking ability
• Advanced memory management, virtual memory
management and protection abilities.

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 CONT…
• It has four level memory protection and support
for virtual memory.
• There are two operating modes in 80286
– Real address mode
– Protected virtual memory address mode
• In real address mode the processor can address
1MB of physical memory.
• Virtual address mode is for
multiuser/multitasking system. In this mode
memory management unit can manage upto 1GB
virtual memory.
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 Comparison of 80286 among some
other Microprocessor
Microprocessor Data Bus Address Bus Memory
Width Width Size

8086 16 20 1M

80186 16 20 1M

80286 16 24 16M

80386 DX 32 32 4G

80486 32 32 4G

Pentium 4 and 64 40 1T
Core 2
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 Internal Architecture of 80286

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 Functional Parts
The CPU contains four functional blocks:
1. Address Unit
2. Bus Unit
3. Instruction Unit
4. Execution Unit

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 Functional Parts of 80286
Address Unit
 Responsible for calculating physical address of instructions and data
that the CPU want to access.
 Address lines derived by this unit is also used to address different
peripherals.
 The physical address computed by the address unit is handed over
to the bus unit (BU) of the CPU.
Bus Unit
 Major function of the bus unit is to fetch instruction bytes from the
memory.
 The bus control module controls the pre-fetcher module.
 The pre-fetched instructions are arranged in a 6-byte instruction
queue.
 The 6-byte pre-fetch queue forwards the instructions arranged in it
to the instruction unit (IU).

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 Contd…
Instruction Unit
 It accepts instructions from the pre-fetch queue and
decodes them one by one.
 The decoded instructions are latched onto a decoded
instruction queue.
 The output of decoded instruction queue drives a control
circuit in the execution unit.
Execution Unit
 It is responsible for executing the instruction received from
decoded instruction queue.
 The EU contains the register bank used for storing the data.
 The ALU carries out all the arithmetic and logical operations
and sends the result over the data bus or back to the
register bank.

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 Operating Modes
Real Addressing Mode
 Addresses only 1MB of physical memory using A0-A19. The lines A20-A23
are not used in this mode.
 While addressing the physical memory, the 80286 uses BHE along with A0-
A19.
 Instruction set is upwardly compatible.
 Because of extra pipelining and other circuit level improvements, in real
address mode also, the 80286 operates at a much faster rate than 8086,
although functionally they work in an identical fashion.
 As in 8086, the physical memory is organized in terms of segments of
64Kbyte maximum size.
 In the real mode the first 1Kbyte of memory starting from address 00000H
to 003FFH is reserved for interrupt vector table. Also the addresses from
FFFF0H to FFFFFH are reserved for system initialization.
 When the 80286 is reset, it always starts the execution in real address
mode.

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 Protected Virtual Address Mode
 80286 is the first processor to support the
concept of virtual memory.
 The virtual memory does not exist physically, it
still appears to be available with in the system.
 The VM is implemented using physical memory
that the CPU can directly access and secondary
memory that is used as a storage for data and
program.
 The Segment of the program or data required for
actual execution at that instant is fetched from
the secondary memory into physical memory.
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 CONT…
• The 80286 is able to address 1 G byte of virtual
memory per task.
• The complete virtual memory is mapped on to the
16Mbyte physical memory.
• If a program larger than 16Mbyte is stored on the hard
disk and is to be executed, if it is fetched in terms of
data or program segments of less than 16Mbyte in size
into the program memory by swapping sequentially as
per sequence of execution.
• Hardware reset is only the way to come out from
protected mode.

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 Register Organization of 80286
• The 80286 CPU contains almost the same set
of registers, as in 8086, namely
1. Eight 16-bit general purpose registers.
2. Four 16-bit segment registers.
3. Status and control registers
4. Instruction pointers

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 Registers of 80286

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 CONT…
• The flag bits (D0, D2, D4, D6, D7 and D11) are modified
according to execution of logical and arithmetic
operations. These are called status bits.
– IOPL- I/O privilege field (D12 and D13)
o IOPL is used in protected mode operation to select the privilege
level for I/O devices. If the current privilege level is higher or more
trusted than the IOPL, I/O executes without hindrance. If the IOPL
is lower than the current privilege level, an interrupt occurs,
causing execution to suspend.
• The additional field available in 80286 flag registers
are:
– NT- Nested task flag (D14):
o The nested task flag indicates that the current task is nested
within another task in protected mode operation. This line is
set when the task is nested by software.

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 Multitasking
 Multi-user operating
system serves multiple
user at the same time.
 The OS of 80286 is
capable of running
multiple user programs.
 Each user is called a
task. Hence multi-user
operating system also
called multi-tasking Figure: Multi-tasking OS
operating system. Prepared By: Er. Ganesh Kumal
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 Privilege levels
 To provide a higher
degree of control for
protection, protected
mode defines privilege
levels:
i) Descriptor privilege
level
ii) Current privilege level
iii) Input/output privilege Figure: Privilege levels
level

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 Contd…
 There are four types of privilege levels
00 kernel level (highest privilege level)
01 OS Services
10 OS Extensions
11 Applications (lowest privilege level)
 Each task assigned a privilege level, which indicates the priority or
privilege of that task.
 It can only changed by transferring the control, using gate
descriptors, to a new segment.
 A task executing at level 0, the most privileged level, can access all
the data segment defined in GDT or LDT of the task.
 A task executing at level 3, the least privileged level, will have the
most limited access to data and other descriptors.
 In most environments, the operating system and some device
drivers run in ring 0 and applications run in ring 3.

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 Descriptor
• Descriptor is a identifier of a program segment or
page.
• A segment cannot be accessed, if its descriptor
does not exist in either LDT or GDT.
• Set of descriptor (descriptor table) arranged in a
proper sequence describes the complete
program.
• The descriptor describes the complete program.
• The descriptor describes the location, length and
access rights of the segment of memory.

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 Cont…
• The descriptor is a block of contiguous memory
location containing information of a segment, like:
 Segment base address
 Segment limit
 Privilege level
 Segment type
 Segment availability in physical memory
 Descriptor type
 Segment use by another task

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 Local Descriptor Table (LDT)
Local Descriptor Table
LDT is set up in the system for each task or
closely related group of task.
Each task can have its own descriptor table
and memory area defined by the descriptor in
it.
The operating system will switch the current
LDT when scheduling a new process, using the
LDT machine instruction.

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 Global Descriptor Table(GDT)
• 80286 has a single Global Descriptor
Table(GDT) which is shared between all tasks.
• The GDT is a data structure used by Intel X86-
family processors in order to define the
characteristics of the various memory areas
used during program execution, including the
base address, the size and access privilege.

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 Cont…

Figure: 80286 Descriptor Figure: Access right bytes for 80286 descriptor

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 80386
• 80386 is an enhanced version of the 80286 microprocessor.
• 80386 includes 32-bit extended registers, 32-bit address and data
bus.
• It has a physical memory size of 4GBytes and addressed as a virtual
memory with up to 64TBytes.
• Memory management unit is enhanced to provide memory paging.
• 80386 supports virtual memory, paging and protection.
• 80386 includes special hardware for task switching.
• 80386 supports three operating modes:
1. Real mode (default)
2. Protected Virtual Address Mode (PVAM)
3. Virtual Mode

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 Architecture of 80386

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 CONT…
The 80386 includes six functional units:
1. Bus Interface Unit
2. Code Pre-fetch Unit
3. Instruction Decoder Unit
4. Execution Unit
5. Segmentation Unit
6. Paging Unit

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 CONT…
• Bus Interface Unit
– It connects the 80386 with memory and I/O. Based on
internal requests for fetching instructions and
transferring data from the code pre-fetch unit, the
80386 generates address, data and control signals for
the current bus cycles.
• Code Pre-fetch Unit
– Pre-fetches instructions when the bus interface unit is
not executing the bus cycles. It then stores them in a
16-byte instruction queue for decoding by the
instruction decode unit.

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 CONT…
• Instruction Decode Unit
– Translates instructions from the pre-fetch queue into micro-
codes. The decoded instructions are then stored in an
instruction queue (FIFO) for processing by the execution unit.
• Execution Unit
– Processes the instructions from the instruction queue. It
contains a control unit, a data unit and a protection test unit.
• Control Unit:
– Contains micro-code and parallel hardware for fast multiply,
divide and effective address calculation, The unit includes a 32-
bit ALU, 8 general purpose registers and a 64-bit barrel shifter
for performing multiple bit shifts in one clock. The data unit
carries out data operations requested by the control unit.

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 CONT…
• Protection Test Unit
– Checks for segmentation violations under the control
of microcode.
• Segmentation Unit
– Calculates and translates the logical address into
linear address at the request of the execution unit.
– The translated linear address is sent to the paging
unit. Upon enabling the paging mechanism, the 80386
translates these linear addresses into physical
addresses. If paging is not enabled, the physical
address is identical to the linear address and no
translation is necessary.

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 Register Organization of 80386

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 Register Organization of 80386
• It has 32-bit general purpose registers which may be used
as either 8-bit or 16-bit registers.
• A 32-bit register known as an extended register, is
represented by the register name with prefix E.
– AX is EAX, BX is EBX and so on.
• The 16-bit registers BP, SP, SI and DI in 8086 are now
available with their extended size of 32-bit and are names
as EBP, ESP, ESI and EDI.
• AX represents the lower 16-bit of the 32-bit register EAX.
• BP, SP, SI, DI represents the lower 16-bit of their 32-bit
counterparts, and can be used as independent 16-bit
registers.
• The CS and SS are the code and stack segment registers ,
while DS, ES, FS, GS are 4 data segment registers.

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 Register Organization

VM: If this flag is set, 80386 enters the

virtual mode in protected mode.
RF: it is used with debugging to
control the resumption of execution
after the next instruction
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Memory Access in Protected Mode
• The processor can switch from the real address mode to PVAM by
setting the PE(protect enable ) bit in the control register CR0.
• In this PVAM the processor can run all 8086 and 80286 programs
with sophisticated memory management and hardware assisted
protection mechanism.
• In PVAM the processor has very large address space.
• It has 4GB of physical memory address space and 64TB of virtual
memory address space.
• The 80386 supports two methods of converting a virtual address to
physical address.
• One method, paging is disabled and the physical address is
computed using the selector, descriptor and offset like 80286
• Another method, the paging is enabled and linear address is
computed using the selector, descriptor and offset like 80286 and
linear address is converted to P.A by paging unit.

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 Paging(Up to LA to PA)
• Paging is one of the memory management
technique used for virtual memory multitasking
operating system.
• The segmentation scheme may divide the
physical memory into a variable size segments
but the paging divides the memory into fixed size
pages.
• Physical memory is divided into equal size block
called as page and the process is called paging.
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 Contd…
• The advantage of paging scheme is that the
complete segment of a task need not be in the
physical memory at any time.
• Only a few pages of the segments, which are
required currently for the execution need to be
available in the P.A memory. Thus the memory
requirement of the task is substantially reduced.
• The previous page which are executed, need not
be available in the memory, and hence the space
occupied by them may be relinquished for other
task.

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 Contd…
• In paging , address generated by segment
address translation is not valid. Linear address
generated by segment address translation is
converted to physical address. The process is
called as page translation.
• Components of page mechanism
Page directory
Page table
Page frame or page

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 End Unit 7
Thank You!

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