PHYSICAL

DESIGN

-CVN REDDY SEELAM

 Introduction to Physical Design Flow in VLSI
Physical design in VLSI translates the logical structure of a netlist into a manufacturable layout
by converting it into a GDSII file, the standard format for IC mask generation. This stage
transforms RTL logic into a physical representation, arranging cells, gates, and transistors with
designated coordinates and connections on multiple fabrication layers. Every step in the physical
design flow—partitioning, placement, power planning, and routing—ensures the chip design
meets critical performance, area, and power requirements. As IC designs grow in complexity,
physical design plays an increasingly vital role in delivering high-performance, reliable, and cost-
effective chips to market.
Key Steps in Physical Design Flow

1. Partitioning
• Partitioning breaks down a large circuit into manageable sub-circuits or modules,
streamlining the design and analysis process.
• Each partition can be designed independently, allowing parallel workflows and reducing
design complexity.
• This step optimizes timing and power across the design since each smaller partition can be
optimized individually, ultimately enhancing chip performance.
• Partitioning is also crucial for minimizing interconnect delay between modules and reducing
congestion in dense designs.
2. Floorplanning
• Floorplanning determines the layout’s structure by assigning shapes and positions to the sub-
circuits, external ports, IP blocks, and macro blocks.
• It helps to minimize wiring congestion, balance power consumption, and reduce interconnect
delays.
• Floorplanning takes into account factors such as connectivity and signal flow, aiming to
create a layout that minimizes path delays and maximizes space efficiency.
• Poor floorplanning can lead to excessive area usage, long interconnects, and difficulties in
achieving timing closure.
3. Power Planning (Power and Ground Routing)
• Power planning ensures a stable power supply and efficient distribution across the design.
• Power and ground (VDD and GND) networks are laid out to deliver consistent voltage and
prevent hotspots, which can degrade performance and reliability.
• Power distribution strategies vary; for instance, power rings and grids are often used around
cells and blocks.
• Decoupling capacitors are placed near power-sensitive components to absorb fluctuations.
• Proper power planning supports high-current requirements and minimizes IR drop (voltage
drop), which can cause timing delays.
4. Placement
• Placement assigns exact coordinates for each cell within the layout. Automated tools
optimize this by considering cell connectivity to minimize wire length, area, and delay.
• Placement includes legalizing cell locations within predefined boundaries, resolving overlap,
and ensuring that cells don’t exceed power or timing budgets.
• Precise placement significantly impacts the chip’s area, speed, and manufacturability, as the
cell arrangement dictates how easily the design can meet timing and connectivity
requirements.
5. Clock Tree Synthesis (CTS)
• Clock Tree Synthesis ensures that the clock signal reaches all sequential elements within a
specific skew budget to maintain synchronous operation.
• Buffering is added where necessary to minimize clock skew and timing delays across the
design.
• Clock gating techniques, applied during CTS, control clock signal distribution to inactive
parts of the circuit to save power.
• CTS is crucial in maintaining timing accuracy, as any skew or delay in the clock signal can
impact the overall functionality of the chip.
6. Global Routing
• Global routing outlines the main routing paths and allocates resources for each signal, such
as routing tracks and channels.
• In this stage, high-level paths are set to reduce congestion and maintain design integrity,
ensuring that each net has sufficient routing resources to meet timing and connectivity
requirements.
• Global routing prepares the design for more detailed routing while minimizing signal
interference and maximizing resource efficiency.
7. Detailed Routing
• Detailed routing assigns each net to specific metal layers and routing tracks within the global
routing framework.
• It ensures precise connectivity, checking for any Design Rule Violations (DRVs) such as
short circuits or open circuits.
• This step is particularly challenging in high-density designs, where routing resources are
limited, and signal integrity must be maintained.
• Advanced EDA tools automate detailed routing to achieve efficient paths, minimal delay,
and reduced power dissipation, ensuring each signal meets timing requirements.
8. Timing Closure
• Timing closure fine-tunes the design to meet performance and timing requirements by
adjusting placement, routing, and buffering.
• Optimizations in this stage include resizing cells, adjusting interconnect lengths, and
inserting repeaters to reduce signal delay.
• Achieving timing closure is crucial in high-frequency designs, as any delay or skew can
impact the circuit’s performance.
• Techniques like buffer insertion, wire re-timing, and path balancing are applied to meet
timing constraints effectively.
9. Layout Verification and GDSII Generation
• Layout verification ensures the design is free of errors like Design Rule Violations (DRCs),
Layout vs. Schematic (LVS) mismatches, and antenna violations.
• DRC checks that each layer meets fabrication rules, while LVS verifies that the physical
layout matches the logical design.
• Once verified, the layout is converted into a GDSII file, the industry-standard format for
mask generation, enabling the design to proceed to the fabrication phase.
Impacts of Physical Design on Key Metrics
1. Performance: Signal delays, caused by longer interconnects or poorly placed cells, affect the
chip’s operating speed. Physical design minimizes these delays by optimizing interconnect
lengths.
2. Area: Compact floorplanning and placement strategies reduce overall chip area, improving
manufacturability and reducing production costs.
3. Reliability: Excessive use of vias or close placement of wires can reduce the circuit’s reliability
by increasing the likelihood of faults. Proper spacing and routing improve reliability over the
chip's lifespan.
4. Power: Careful placement, power planning, and the use of low-power cells reduce power
consumption by minimizing switching activity and dynamic power dissipation.
5. Yield: Designs that follow optimal spacing and interconnect guidelines minimize the chance
of defects during fabrication, enhancing yield and reducing manufacturing costs.
Conclusion
Physical design flow is a critical phase in VLSI, directly impacting a chip’s performance, power,
area, and reliability. Each stage, from partitioning to layout verification, is meticulously
optimized to ensure that the final layout is manufacturable, efficient, and meets stringent industry
standards. As chip designs grow increasingly complex, mastering the physical design process is
essential to delivering high-quality, market-ready ICs that meet the demands of modern
technology.
 What is Partitioning?
Partitioning in VLSI refers to dividing a complex design into smaller, manageable blocks or
modules. These functional blocks are either structurally instantiated or linked into the main
module, also known as the Top-Level Module. Partitioning can occur at various levels, helping
to simplify design, enhance efficiency, and support hierarchical design methodologies.
Partitioning in VLSI Design: Simplifying Complexity
In the VLSI design cycle, the process is broadly divided into Front-End (FE) and Back-End (BE)
stages.
• Front-End Design: Focuses on defining the logical behavior of a circuit according to
functional specifications, starting from system specification to producing a technology-mapped
gate-level netlist.
• Back-End Design: Begins with the gate-level netlist, focusing on translating the logical circuit
into a physical layout on a silicon wafer, including placement, routing of power and signals,
and preparing the design for tape-out.
Types of Partitioning:
[Link] Partitioning:
• During the RTL design phase, the larger design is divided into smaller functional blocks or
modules.
• This allows designers to focus on individual modules, ensuring functionality and ease of
testing.
• Logical partitioning structures the design for better understanding and implementation.
[Link] Partitioning:
• Focuses on the physical placement of the functional blocks on the chip.
• Ensures that blocks are positioned for optimized routing and efficient use of area.
Levels of Partitioning:
[Link]-Level Partitioning:
• The system is divided into groups of PCBs (Printed Circuit Boards), with each subsystem
designed as an individual PCB.
• Example: A computer motherboard can be split into power supply, processor, and I/O
boards.
[Link]-Level Partitioning:
• A PCB is further divided into smaller sub-circuits, each implemented as separate VLSI chips.
• Example: Memory, processor, and GPU chips on a motherboard.
[Link]-Level Partitioning:
• The circuit assigned to a chip is split into manageable sub-circuits.
• Example: Dividing a processor into ALU, control unit, and cache blocks.
 Why is Partitioning Important?

1. Physical Packaging:
• Partitioning adheres to physical constraints, conforming to the hierarchy of cabinets, boards,
chips, and modules.
• This decomposition ensures that the design can fit within physical space and packaging
requirements.
2. Divide and Conquer Strategy:
Breaking down complex designs into smaller, more manageable parts facilitates:
• Parallel development by teams working on different sections.
• Logical conversion of the netlist into a physical layout.
• Efficient cell placement and extraction of RLC parameters for simulation.
• Better coordination between logic and layout teams.
3. System Emulation & Rapid Prototyping:
• Prototypes using FPGAs require partitioning, as FPGAs often have less capacity than
modern VLSI designs.
• Partitioning tools help map the netlist onto multiple FPGAs for rapid testing and validation.
4. Hardware-Software Codesign:
• Partitioning is essential in hardware/software codesign, where tasks are divided between
hardware (custom circuits) and software (programmable processors).
• Example: Splitting tasks for a system-on-chip (SoC) into hardware accelerators and software
routines.
5. Design Reuse Management:
• For large designs like SoCs, partitioning facilitates design reuse by clustering netlists into
reusable functional modules.
• This approach reduces design effort and time for future projects.
Advantages of Partitioning:
• Enhanced Design Efficiency: Smaller blocks are easier to manage, debug, and verify.
• Scalability: Supports hierarchical design and parallel workflows.
• Improved Routing: Simplifies routing by localizing interconnects within functional blocks.
• Power Optimization: Allows better control of power domains.
• Ease of Testing: Smaller blocks can be tested independently, improving overall verification
coverage.
 Challenges in Partitioning:
[Link] Optimization:
Incorrect partitioning can lead to excessive interconnects between blocks, increasing complexity
and delays.
[Link] Closure:
Ensuring timing closure across partition boundaries can be difficult, especially for high-
performance designs.
[Link] Allocation:
Balancing resource usage (power, area, and routing congestion) across partitions is a challenge.
[Link] Limitations:
Partitioning tools may not always handle complex interdependencies efficiently, requiring
manual intervention.
Conclusion:
Partitioning is an indispensable step in the VLSI design cycle, enabling efficient handling of
complex designs by dividing them into manageable blocks. It supports modularity, scalability,
and reuse while streamlining the physical design process. Although it introduces certain
challenges, its advantages in enhancing design efficiency and reducing complexity make it an
integral part of modern VLSI design.
 Partitioning : Principles and Techniques
Partitioning is a cornerstone of VLSI design, breaking down complex circuits into manageable
sub-circuits. In this second part, we dive deeper into the rules, outcomes, and advanced
methodologies that make partitioning effective and indispensable.
Rules of Partitioning
Partitioning is guided by several key principles to ensure optimal design, minimal delays, and
efficient fabrication. Below are the critical rules:
[Link] Between Partitions:
• Reducing the number of interconnections between partitions minimizes delays and simplifies
independent design and fabrication.
• Fewer interconnections result in less complexity during routing and timing closure.
[Link] Due to Partitioning:
• Partitioning may introduce delays as the critical path can cross partition boundaries multiple
times.
• Designers must account for these delays to ensure timing closure across partitions.
[Link] of Terminals:
• The number of nets required to connect a sub-circuit to other sub-circuits must not exceed
the available terminal count of the sub-circuit.
• This prevents congestion and ensures efficient routing.
[Link] of Partitions:
• Increasing the number of partitions can simplify individual design sections but may lead to
higher fabrication costs and additional interconnections between partitions.
• A balance must be struck between simplicity and cost efficiency.
[Link] of Each Partition:
• The area of each partition must be optimized to ensure balanced resource allocation, prevent
wastage of space, and meet physical constraints such as chip size and power dissipation.
What Happens After Circuit Partitioning?
After partitioning, designers analyze and plan based on the partitioned layout. The following
outcomes are derived:
[Link] Estimation:
• The area occupied by each partition is calculated to ensure balance and optimal resource
utilization.
[Link] Shapes:
• Possible shapes and dimensions of blocks are ascertained for physical layout planning.
[Link] Requirements:
• The number of terminals needed for each block is determined to ensure seamless
interconnections.
[Link] Availability:
• A netlist specifying connections between blocks becomes available, serving as a blueprint
for routing and placement.
 Graph Theory in Partitioning
Partitioning in VLSI leverages graph theory to represent layout topologies and solve partitioning
problems efficiently.

Graph Representation:
A graph Graph Representation:A graph 𝐺(𝑉,𝐸)
G(V,E) consists of:
• Vertices (V): Representing components, cells, or modules in the circuit.
• Edges (E): Representing connections or interdependencies between the components

• Graphs are used to model circuit layouts, interconnections, and constraints.

• They help identify optimal partitioning solutions while minimizing cross-boundary
interactions.
Partitioning Algorithms

Partitioning involves dividing a circuit into manageable k partitions. The primary objective is to
minimize the number or weight of cut edges while maintaining balanced partition sizes.
Partitioning algorithms can be categorized as follows:
Constructive vs. Iterative Methods:
Constructive Methods:
• Create partitioning solutions from scratch, often using graphs to represent circuit layouts.
• Useful in the initial design stages.
Iterative Methods:
• Work to refine or improve existing partitioning solutions by iteratively adjusting boundaries
and interconnections.
• Common iterative methods include Kernighan-Lin (KL) and Fiduccia-Mattheyses (FM)
algorithms.
 Deterministic vs. Probabilistic Methods:
Deterministic Methods:
• Produce consistent solutions for the same inputs, ensuring reliability and predictability.
• Example: Recursive bisection methods.
Probabilistic Methods:
• Generate different solutions for the same inputs using randomization techniques.
• Useful in exploring diverse design possibilities and avoiding local optima.
Challenges in Partitioning
[Link] Partition Size:
Uneven partition sizes can lead to inefficient resource utilization and increased delays.
[Link] Path Delays:
Managing delays caused by critical paths crossing partitions is a key challenge.
[Link]:
As circuits grow larger, finding optimal partitioning solutions becomes computationally
expensive.
[Link] Conditions:
Physical constraints such as chip size and floorplan restrictions must be respected during
partitioning.
Conclusion
Partitioning in VLSI design is both an art and a science, blending logical and physical design
principles to manage complexity and enhance efficiency. By following established rules and
leveraging advanced algorithms, designers can achieve balanced and optimized partitions that
streamline the entire design and fabrication process. As VLSI systems grow in complexity,
innovative partitioning techniques will continue to play a pivotal role in pushing the boundaries
of technology.
 Floorplanning in ASIC Design (Part 1): A Detailed Guide
Floorplanning serves as the cornerstone of any physical design process in ASIC (Application-
Specific Integrated Circuit) development. It involves the systematic arrangement of circuit
components to achieve high performance, efficient area utilization, and robust power and signal
integrity. Let’s explore the intricacies of floorplanning, from its inputs to key parameters and
implementation steps.

What is Floorplanning?
Floorplanning is a critical step in the physical design flow, where the physical layout of the chip
is determined. This process requires balancing multiple constraints, including performance, area,
power, and manufacturability, to create a robust and efficient chip.
Key aspects of floorplanning
Placement of I/O Pads and Macros: Proper alignment ensures efficient signal flow and minimizes
parasitic effects.
1. Design of Power and Ground Networks: Robust power distribution is crucial for reliable chip
operation.
2. Preparation for Routing: Ensuring adequate space for routing minimizes congestion and
improves timing.
The primary objective is to create a layout that satisfies the design's performance goals while
adhering to area and power constraints.
Inputs Required for Floorplanning
Before initiating floorplanning, several critical files and constraints must be prepared. These
inputs guide the placement and organization of components in the chip.
[Link] (.v):
• A netlist is a textual description of the chip's logical connectivity, including gates, flip-flops,
and macros.
• It defines the functional relationship between components.
[Link] File (techlef):
• Contains details about the technology node, such as routing layers, design rules, and process-
specific parameters.
[Link] Library Files (.lib):
• Defines the timing characteristics of standard cells, including propagation delays, setup/hold
times, and power consumption.
[Link] Library (.lef):
• Provides physical dimensions of cells and macros, including height, width, and pin locations.
[Link] Design Constraints (SDC):
• Specifies design constraints such as clock definitions, input/output timing, and multi-cycle
paths.
[Link]+ Files:
• Contains data for parasitic extraction, enabling accurate delay and signal integrity analysis.
 Steps in Floorplanning
Once the physical design database is created using the imported netlist and associated library
files, the following steps are undertaken:
1. Die Size Estimation
➢ Core Width and Height:
• The core dimensions are calculated based on the total logic area and the required routing
space.
➢ Aspect Ratio:
• The aspect ratio determines the shape of the die and influences routing efficiency.
2. I/O Pad Placement
➢ Pad Sites Creation:
• Sites are allocated around the die boundary for placing I/O pads.
➢ Types of Pads:
• Power Pads: Deliver power to the chip.
• Ground Pads: Ensure stable grounding.
• Signal Pads: Facilitate data communication between the chip and external circuits.
Proper placement minimizes electro-migration and current-switching noise.
3. Macro Placement
➢ Manual Macro Placement:
• Suitable for designs with a few macros, where placement is guided by connectivity and timing
requirements.
➢ Automatic Macro Placement:
• Used for complex designs with numerous macros, leveraging automation tools for efficient
arrangement.
4. Standard Cell Row Creation
• Rows are created for the placement of standard cells, ensuring alignment and consistency
across the layout.
5. Power Planning (Pre-Routing)
• The initial power and ground grid is designed to ensure uniform power distribution and
minimize IR drops.
6. Adding Physical-Only Cells
• Auxiliary cells such as filler cells, decap cells, and tap cells are added to enhance chip
performance and mitigate signal noise.
7. Core and I/O Factors
• Aspect Ratio: Balances horizontal and vertical routing resources.
• Core Utilization: Maintains sufficient space for routing and timing closure.
• Cell Orientation: Ensures proper alignment for manufacturing.
• Core-to-I/O Clearance: Adequate spacing avoids routing congestion near the die boundary.
Key Floorplanning Parameters
1. Aspect Ratio
• Defines the relationship between the width and height of the die.
Aspect Ratio=Width/Height
• A well-chosen aspect ratio ensures efficient routing and minimizes delay.
2. Core Utilization
• Represents the fraction of the core area occupied by standard cells, macros, and I/O pads.
Core Utilization=(Macros Area + Standard Cell Area + Pads Area)/Total Core Area
• A typical utilization range is 70%-80%, leaving space for routing and optimizations.
3. Pad Placement
Proper pad placement ensures functional integrity and minimizes issues like electro-migration
and switching noise.
The number of power and ground pads is calculated as:
Ngnd=Itotal/Imax
where:
• Ngnd = Number of ground pads.
• Itotal = Total current (static + dynamic).
• Imax = Maximum allowable current per pad.
Challenges in Floorplanning
[Link] Optimization:
Balancing standard cell placement and routing space is critical for achieving design goals.
[Link] Integrity:
Ensuring a robust power grid minimizes voltage drops and maintains circuit reliability.
[Link] Integrity:
Preventing crosstalk and managing switching noise is essential for timing closure.
[Link] Congestion:
A poorly planned floorplan can lead to severe routing issues, increasing delays and design
iterations.
Conclusion
Floorplanning is more than just placing components on a die; it is the foundational step that
shapes the success of an ASIC design. A carefully executed floorplan ensures high performance,
efficient area usage, and reliable power distribution. By understanding the inputs, processes, and
challenges, designers can create optimized layouts that meet design specifications and
manufacturing constraints.
 Floorplanning in ASIC Design (Part 1): A Detailed Guide
Floorplanning serves as the cornerstone of any physical design process in ASIC (Application-
Specific Integrated Circuit) development. It involves the systematic arrangement of circuit
components to achieve high performance, efficient area utilization, and robust power and signal
integrity. Let’s explore the intricacies of floorplanning, from its inputs to key parameters and
implementation steps.

What is Floorplanning?
Floorplanning is a critical step in the physical design flow, where the physical layout of the chip
is determined. This process requires balancing multiple constraints, including performance, area,
power, and manufacturability, to create a robust and efficient chip.
Key aspects of floorplanning
Placement of I/O Pads and Macros: Proper alignment ensures efficient signal flow and minimizes
parasitic effects.
1. Design of Power and Ground Networks: Robust power distribution is crucial for reliable chip
operation.
2. Preparation for Routing: Ensuring adequate space for routing minimizes congestion and
improves timing.
The primary objective is to create a layout that satisfies the design's performance goals while
adhering to area and power constraints.
Inputs Required for Floorplanning
Before initiating floorplanning, several critical files and constraints must be prepared. These
inputs guide the placement and organization of components in the chip.
[Link] (.v):
• A netlist is a textual description of the chip's logical connectivity, including gates, flip-flops,
and macros.
• It defines the functional relationship between components.
[Link] File (techlef):
• Contains details about the technology node, such as routing layers, design rules, and process-
specific parameters.
[Link] Library Files (.lib):
• Defines the timing characteristics of standard cells, including propagation delays, setup/hold
times, and power consumption.
[Link] Library (.lef):
• Provides physical dimensions of cells and macros, including height, width, and pin locations.
[Link] Design Constraints (SDC):
• Specifies design constraints such as clock definitions, input/output timing, and multi-cycle
paths.
[Link]+ Files:
• Contains data for parasitic extraction, enabling accurate delay and signal integrity analysis.
 Steps in Floorplanning
Once the physical design database is created using the imported netlist and associated library
files, the following steps are undertaken:
1. Die Size Estimation
➢ Core Width and Height:
• The core dimensions are calculated based on the total logic area and the required routing
space.
➢ Aspect Ratio:
• The aspect ratio determines the shape of the die and influences routing efficiency.
2. I/O Pad Placement
➢ Pad Sites Creation:
• Sites are allocated around the die boundary for placing I/O pads.
➢ Types of Pads:
• Power Pads: Deliver power to the chip.
• Ground Pads: Ensure stable grounding.
• Signal Pads: Facilitate data communication between the chip and external circuits.
Proper placement minimizes electro-migration and current-switching noise.
3. Macro Placement
➢ Manual Macro Placement:
• Suitable for designs with a few macros, where placement is guided by connectivity and timing
requirements.
➢ Automatic Macro Placement:
• Used for complex designs with numerous macros, leveraging automation tools for efficient
arrangement.
4. Standard Cell Row Creation
• Rows are created for the placement of standard cells, ensuring alignment and consistency
across the layout.
5. Power Planning (Pre-Routing)
• The initial power and ground grid is designed to ensure uniform power distribution and
minimize IR drops.
6. Adding Physical-Only Cells
• Auxiliary cells such as filler cells, decap cells, and tap cells are added to enhance chip
performance and mitigate signal noise.
7. Core and I/O Factors
• Aspect Ratio: Balances horizontal and vertical routing resources.
• Core Utilization: Maintains sufficient space for routing and timing closure.
• Cell Orientation: Ensures proper alignment for manufacturing.
• Core-to-I/O Clearance: Adequate spacing avoids routing congestion near the die boundary.
Key Floorplanning Parameters
1. Aspect Ratio
• Defines the relationship between the width and height of the die.
Aspect Ratio=Width/Height
• A well-chosen aspect ratio ensures efficient routing and minimizes delay.
2. Core Utilization
• Represents the fraction of the core area occupied by standard cells, macros, and I/O pads.
Core Utilization=(Macros Area + Standard Cell Area + Pads Area)/Total Core Area
• A typical utilization range is 70%-80%, leaving space for routing and optimizations.
3. Pad Placement
Proper pad placement ensures functional integrity and minimizes issues like electro-migration
and switching noise.
The number of power and ground pads is calculated as:
Ngnd=Itotal/Imax
where:
• Ngnd = Number of ground pads.
• Itotal = Total current (static + dynamic).
• Imax = Maximum allowable current per pad.
Challenges in Floorplanning
[Link] Optimization:
Balancing standard cell placement and routing space is critical for achieving design goals.
[Link] Integrity:
Ensuring a robust power grid minimizes voltage drops and maintains circuit reliability.
[Link] Integrity:
Preventing crosstalk and managing switching noise is essential for timing closure.
[Link] Congestion:
A poorly planned floorplan can lead to severe routing issues, increasing delays and design
iterations.
Conclusion
Floorplanning is more than just placing components on a die; it is the foundational step that
shapes the success of an ASIC design. A carefully executed floorplan ensures high performance,
efficient area usage, and reliable power distribution. By understanding the inputs, processes, and
challenges, designers can create optimized layouts that meet design specifications and
manufacturing constraints.
Floorplanning plays a pivotal role in determining the quality of an ASIC design, directly
influencing performance, power efficiency, and area optimization. This segment explores
advanced techniques, critical concepts, best practices, and outcomes in floor planning.
Types of Floorplan Techniques
1)Abutted Design
• In abutted floorplanning, blocks are tightly packed together without any gaps.
• This technique simplifies interconnection as blocks are adjacent, reducing routing complexity.
• It is typically used for designs where minimal area and high integration are priorities.
• Advantages:
a. Reduces routing overhead.
b. Facilitates compact chip design.
• Challenges: May lead to routing congestion in complex designs.
2)Non-Abutted Design
• Introduces gaps between blocks, offering greater flexibility for routing.
• Connections between blocks are established through routing nets, accommodating designs with
intricate routing requirements.
• Advantages:
a. Avoids congestion by allocating space for routing.
b. Easier to manage thermal dissipation in larger designs.
• Challenges:Consumes more area compared to abutted designs.
3)Mixed Design
• Combines features of both abutted and non-abutted designs.
• Certain blocks are tightly packed while others have gaps, balancing area efficiency with routing
flexibility.
• Commonly employed in designs with diverse functional blocks requiring different placement
strategies.
Key Terms Related to Floorplanning
1)Standard Cell Row
• The core area is divided into uniform rows where standard cells are systematically placed.
• Rows ensure alignment, facilitating efficient routing and signal integrity.
2)Fly Lines
• Represent virtual connections between macros or between macros and IO pads.
• Act as visual guides for manual placement, highlighting interconnections.
3)Macros to IO Pin
• Describes the connection strategy between macros and IO pins for efficient signal routing.
• Ensures minimal delay and reduces routing congestion by aligning macros with their
corresponding IO pins.
4)Halo (Keep-Out Margin)
• A reserved area around macros to prevent other cells from being placed too close.
• Essential for reducing congestion and allowing space for routing.
• Improves overall signal quality and prevents layout violations near macros.
 Blockages in Floorplanning
Blockages are regions within the chip where cell placement is restricted to manage congestion,
power, and routing complexities.
[Link] Blockages
• Restricts placement of standard cells and macros but allows buffers or inverters.
• Useful during optimization, legalization, and clock tree synthesis.
[Link] Blockages
• Prohibits any cell placement, including buffers and macros, in specified areas.
• Primarily used to avoid congestion near macro corners or sensitive areas.
• Controls power rail generation around macros to ensure proper power delivery.
[Link] Blockages
• Limits cell density in specific regions without completely blocking placement.
• Allows designers to adjust blockage factors (e.g., reduce density to 50% instead of 100%) for
better utilization.
Guidelines for Effective Floorplanning
To achieve an optimal floorplan, adhere to these practical guidelines:
[Link] Placement:
• Position macros near the core's periphery, aligning pins towards the center.
• Avoid placing macros in the core's center to minimize routing bottlenecks and ensure smooth
signal flow.
[Link] Path Optimization:
• Avoid notches or irregularities in the core area that disrupt routing.
• If macros must be placed centrally, create roundabout paths to maintain connectivity.
[Link] Considerations:
• Place macros with frequent communication (talking macros) near each other to reduce signal
delays and routing complexity.
• Avoid criss-crossing signal paths to prevent timing issues.
[Link] Maintenance:
• Maintain appropriate halos around macros to provide space for routing and reduce congestion.
• Ensure halos are neither too small (causing routing issues) nor too large (wasting valuable
area).
Outputs of Floorplanning
The outcomes of a well-executed floorplanning process include:
[Link] and Boundary Area:
• Finalized dimensions of the core and its boundary, ensuring compliance with design
specifications.
[Link] Ports/Pins Placement:
• Precise positioning of input/output ports and pins, aligning with functional and routing
requirements.
[Link] Placement:
• Accurate alignment and positioning of macros, ensuring optimal performance and minimal
routing congestion.
[Link] DEF File:
• A comprehensive Design Exchange Format (DEF) file containing detailed floorplan
information for subsequent design stages.
Conclusion
Floorplanning is not merely a step in the physical design process; it is the foundation for the entire
ASIC design. By carefully choosing the appropriate floorplan technique, understanding key
concepts like halos and blockages, and adhering to best practices, designers can create a layout
that ensures high performance, efficient routing, and reduced congestion. A well-executed
floorplan is critical for achieving design objectives and laying the groundwork for downstream
processes like placement, routing, and timing analysis.
 Power Planning in VLSI Design
In the past, designing VLSI circuits mainly focused on reducing chip area and maximizing speed.
However, with advancements in technology, power consumption has become the most critical
aspect, especially for devices that rely on batteries. Factors like the increased number of
transistors, faster operation, and higher leakage currents in smaller technologies make power
management an essential part of the design.
Why is Power Planning Important?
• More Transistors: Today’s chips are packed with billions of transistors, which increases
power usage.
• Faster Operations: Higher speeds mean the design needs stable power delivery to function
without errors.
• Leakage Currents: Smaller transistors lead to power leakage, wasting energy even when
the device is idle.
What is Power Planning?
Power planning ensures that all parts of a chip, such as macros, standard cells, and other
components, receive stable power. It involves designing a structure for delivering power and
ground across the entire chip.
• Power for IO Pads: IO pads already have built-in power and ground connections. These are
connected through their design.
• Power for the Core: A core ring surrounds the logic area, carrying power (VDD) and ground
(VSS).
Inside the core, power and ground stripes spread power across the logic. When these stripes form
a grid, it’s called a power mesh.

Steps in Power Planning

[Link] Requirements:
• Determine how many power pins, rings, and stripes are needed based on the chip’s power
usage.
• Decide the width of these components to handle the required current.
[Link] Drop Analysis:
• Ensure voltage doesn’t drop too much while traveling through the metal layers, as this can
affect circuit performance.
[Link] Files for Power Planning:
• Netlist (.v): Contains the chip's logical design.
• SDC File: Specifies timing rules the chip must meet.
• Library Files (.lef & .lib): Provide information about the physical and functional properties
of design components.
• TLU+: Data for analyzing resistance and capacitance.
• UPF File: Describes the chip's power setup.
Levels of Power Distribution
[Link]:
Carry power (VDD) and ground (VSS) around the chip's perimeter.
[Link]:
Extend from the rings to spread power throughout the core area.
[Link]:
Connect power and ground to individual standard cells.
How is Power Planning Managed?
[Link] Power Management:
• Power rings are placed around the core.
• Special power rings are created for macros or IP blocks that need extra power.
• Power straps are added based on how much power the core needs.
[Link] Power Management:
• Power rings are also created for IO cells.
• Trunks connect the IO power rings to the core power rings and pads.
What Makes an Ideal Power Distribution Network?
A good power network has these qualities:
• Stable Power: Provides a consistent voltage with minimal noise.
• Durable: Prevents issues like overheating and metal layer wear.
• Efficient Use of Space: Uses minimal chip area and wiring.
• Easy to Design: Allows for straightforward layout and implementation.
Conclusion
Power planning is vital in modern chip design because it ensures efficient power delivery to all
parts of the chip. With the right methods, designers can address issues like IR drops, leakage
currents, and power stability. As VLSI technology continues to advance, effective power planning
will remain a cornerstone of designing energy-efficient and reliable chips for modern devices.
 Placement in Physical Design
Placement is a fundamental step in the physical design flow of a VLSI chip. It involves assigning
physical locations to all the standard cells and macros in a chip while optimizing critical
parameters like timing, power, and area. Placement heavily impacts the chip's performance,
power consumption, and manufacturability.
Key Objectives of Placement
[Link] Optimization:
• Placement ensures that cell positions meet timing constraints by minimizing delays in critical
paths and keeping the interconnect lengths minimal.
[Link] Optimization:
• By strategically placing cells to reduce interconnect lengths and avoid hotspots, placement
contributes to reduced power consumption.
[Link] Optimization:
• Placement ensures efficient utilization of the available area, avoiding unnecessary
congestion or wasted space.
[Link] Routability:
• Placement must ensure the design can be routed effectively, with minimal congestion in
critical areas.
[Link] Violations:
• It avoids timing Design Rule Check (DRC) violations by adhering to the design constraints
during placement.

Phases of Placement
1. Pre-Placement Optimization:
• Wire Load Models (WLMs) are removed as they become inaccurate in modern designs.
• Virtual routing is used to calculate RC (Resistance-Capacitance) values, which are more
accurate and reflect the physical interconnects better than WLMs.
2. Coarse Placement:
The tool assigns approximate locations to cells based on timing, congestion, and multi-voltage
domain constraints.
During this phase:
• Cells might overlap or not align to the placement grid.
• Large blocks such as RAMs and IPs act as placement blockages, restricting standard cell
placement.
• Coarse placement provides a quick estimate for initial analysis, including congestion and
timing.
3. Legalization:
The tool adjusts cell positions to ensure:
• Cells align to the placement grid.
• Overlapping cells are repositioned to avoid overlaps.
• Timing violations introduced during coarse placement are minimized through incremental
optimizations.
4. Incremental Optimization:
• Tools resize cells, adjust driving strengths, or reposition certain cells to resolve timing or
congestion issues introduced during legalization.
Placement Constraints

To ensure the quality of placement, constraints are applied during the process:
• Placement Blockages: Areas where cells are not allowed to be placed, typically near macros
or sensitive regions.
• Placement Bounds: Define specific regions within which cells can be placed.
• Density Constraints: Ensure cell placement does not exceed a specified density, improving
routability.
• Cell Spacing Constraints: Maintain a minimum distance between cells to prevent
manufacturing defects and ensure proper routing.
Inputs and Outputs of Placement
Inputs:
• Netlist: Defines the connectivity of cells.
• Floorplan DEF: Provides the physical structure of the design, including macros, pins, and
blockages.
• Physical and Logical Libraries: Contain detailed descriptions of standard cells and their
attributes.
• Design Constraints: Specify timing, power, and area requirements.
• Technology File: Includes details about metal layers, vias, and other process-specific
parameters.
Outputs:
• Placement DEF: Updated design file containing the physical locations of all cells after
placement.
Placement Tools
Industry-Standard Tools:
[Link] Innovus:Widely used for high-performance and low-power designs, offering
advanced algorithms for placement and optimization.
[Link] ICC2 (IC Compiler 2):Known for its efficient timing, power, and area optimization
during placement.
[Link] (Siemens) Calibre: Offers advanced placement features, especially for mixed-signal
and custom designs.
Open-Source Tools:
[Link]:
An open-source toolchain designed for automated RTL-to-GDSII flow. Provides placement
capabilities as part of its flow.
[Link] with NextPnR:
Useful for FPGA placement and routing.
[Link]:
A stand-alone open-source tool for global placement, known for its scalability and efficiency.

Conclusion
Placement is a critical step in the VLSI design flow that directly impacts the chip's performance,
power consumption, and manufacturability. With advancements in technology and shrinking
geometries, placement has become more challenging but equally crucial. Leveraging industry-
standard tools like Cadence Innovus and Synopsys ICC2 or open-source tools like OpenROAD
ensures efficient and optimized placement, laying the foundation for successful routing and high-
quality designs. Through careful constraint management and iterative optimization, placement
ensures a robust and manufacturable chip design.
 Placement(Part-2)
Building on the fundamental principles of placement, this section delves into more detailed
aspects of optimization techniques, congestion management, and post-placement checks, which
are essential for achieving a manufacturable and high-performance design.

Optimization Techniques in Placement

Optimization techniques refine the initial placement to meet design objectives like timing, area,
and power. These techniques also aim to minimize congestion and improve routability.
1. Cloning
• Definition: Cloning duplicates a cell or gate to distribute its fan-out load more evenly across
the design.
• Purpose: Reduces timing delays caused by high fan-out nets, especially on critical paths.
• Example: A clock buffer driving multiple clock sinks can be cloned, where each clone drives
a subset of the sinks, reducing the load on a single buffer.
2. Gate Duplication
• Definition: Similar to cloning, gate duplication involves replicating gates to serve specific
areas of the design.
• Purpose: Gate duplication minimizes critical path delays by ensuring that signals travel shorter
distances.
• Use Case: Commonly applied in high-performance designs to meet stringent timing
requirements.
3. Gate Sizing
• Definition: Modifying the size of gates (up-sizing or down-sizing) to balance timing and
power.
• Purpose:
o Larger gates reduce delay but increase power consumption and area.
o Smaller gates save power but may not meet timing constraints on critical paths.
• Implementation: This is often performed iteratively based on timing analysis results during
placement.
4. Pin Swapping
• Definition: Exchanging input pins on a standard cell to optimize its internal delays.
• Purpose:
o Helps in fine-tuning delay characteristics of critical nets.
o Affects delay without changing functionality.
• Example: Swapping inputs on a multiplexer (MUX) based on signal arrival times can balance
delays.
5. Fan-Out Splitting
• Definition: Breaking down a high fan-out net by introducing buffers or cloning gates.
• Purpose:
o Prevents timing degradation caused by excessive load on a single net.
o Ensures that signal strength is preserved across long distances.
• Example: A high fan-out clock or reset signal can be split using buffers to drive various blocks
efficiently.
Congestion in Placement
Congestion is one of the most critical challenges in the placement stage. Poor congestion
management can lead to routing failures, increased delays, and ultimately, an unmanufacturable
design.

Understanding Congestion
[Link] is Congestion?
• Congestion occurs when the number of available routing tracks is insufficient to meet the
routing demands of a region.
[Link]:
• Congestion maps are used to highlight areas of high congestion.
• Colors such as red, orange, and yellow indicate varying levels of congestion severity, with red
being the most severe.
• Example: If a routing cell border shows 10/9 in light blue, it means 10 tracks are required, but
only 9 tracks are available.
[Link] for Congestion
• High Standard Cell Density:
✓ Overpacking cells in a small area leads to insufficient routing resources.
✓ This is common in timing-critical regions where many cells are clustered together.
• Proximity to Macros:
✓ Standard cells placed too close to macros limit the routing space available around the
macros.
• High Pin Density:
✓ High fan-in gates like AOI and OAI contribute to pin congestion, especially near macros or
block edges.
• Bad Floorplan:
✓ Poor floorplanning, such as inadequate blockages or halos, can lead to severe congestion.
• Macro Placement at the Center:
✓ Placing macros centrally limits the routing channels available for standard cells and IOs.
• Excessive IO Buffers:
✓ Buffer insertion during IO optimization often increases congestion in the core region.
[Link] to Mitigate Congestion in Placement
1. Macro Placement Optimization
✓ Place macros near the boundaries of the chip instead of the center.
✓ Use sufficient halos and blockages around macros to prevent congestion in their vicinity.
2. Uniform Cell Distribution
✓ Maintain a consistent standard cell density across the design.
✓ Avoid regions with extremely high or low cell density.
3. Pin Density Management
✓ Spread high fan-in cells throughout the design.
✓ Ensure that macros and blockages are strategically placed to minimize pin congestion.
4. Improved Floorplanning
✓ Allocate sufficient routing resources during floorplanning.
✓ Introduce soft blockages to guide the placement of non-critical cells away from congested
regions.
5. Buffer Optimization
✓ Limit the number of buffers inserted in the design.
✓ Spread buffer placement evenly to avoid clustering in a single region.
6. Routing Track Allocation
✓ Reserve sufficient routing resources for critical nets early in the placement process.
✓ Use metal layers effectively to distribute congestion.
Checks After Placement

After placement, a series of checks are performed to ensure the design is ready for routing and
meets all constraints.
1. Legalization Check
• Ensures that all cells are properly aligned to the placement grid.
2. Power-Ground (PG) Connections
• Ensure uniform power delivery to avoid IR drop issues.
3. Congestion and Density Analysis
• Ensure pin density maps are within acceptable limits to avoid routing bottlenecks.
4. Timing Quality of Results (QoR)
Check for:
• Worst Negative Slack (WNS): The most significant delay violation in the design.
• Total Negative Slack (TNS): The sum of all timing violations in the design.
• Ensure there are no severe timing violations that could impact functionality.
5. Design Rule Check (DRC)
Verify that there are no violations for:
• Maximum transition limits.
• Maximum capacitance limits.
• Maximum fan-out limits.
6. Utilization Analysis
• It Ensures total utilization of the design is below the target threshold,typically around 70-80%
Conclusion
Optimization and congestion management are pivotal to achieving a robust VLSI design. By
employing advanced techniques like cloning, gate sizing, and fan-out splitting, and addressing
congestion early in the placement process, designers can create efficient and manufacturable
chips. With the support of industry-standard and open-source tools, the placement process
continues to evolve, enabling designers to meet the demands of complex and high-performance
designs.
 Clock Tree Synthesis (CTS)
Clock Tree Synthesis (CTS) is a crucial phase in the physical design flow that ensures the
distribution of the clock signal to all sequential elements (flip-flops and latches) in a balanced
and efficient manner. Before CTS, the design assumes an ideal clock, meaning the clock signal
reaches all registers simultaneously without delay or skew. However, in reality, different elements
receive the clock signal at different times due to interconnect delays and variations in path
lengths. CTS addresses these issues by inserting buffers and inverters into the clock network to
achieve balanced skew and controlled insertion delay.
Importance of CTS
• Clock Distribution: Ensures all clock pins receive the clock signal.
• Clock Skew Minimization: Reduces the timing variations among sequential elements.
• Insertion Delay Control: Limits the overall delay from the clock source to the sinks.
• DRC Compliance: Ensures the design adheres to transition, capacitance, and fan-out
constraints.
• Optimized Performance: Helps in meeting hold timing requirements by proper buffer
insertion.
• Pre-CTS Stage: Clock Assumptions and Placement Considerations

Before CTS, placement optimization only considers the data paths, not the clock paths. The clock
signal is treated as an ideal input, and no modifications are made to its path during placement.
The following factors are key at this stage:
• Standard Cell and Macro Placement: Placement provides the exact positions of all sequential
elements that need the clock signal.
• Ideal Clock: A single ideal clock source drives all clock sinks (sequential elements) without
considering skew or insertion delay.
• Data Path Optimization: Buffer insertion, gate sizing, and other optimizations are applied to
data paths but not the clock path.
• Post-Placement Timing Analysis: Hold timing violations are usually ignored before CTS
because the clock signal is still ideal.
Clock Tree Synthesis (CTS) Process
CTS builds a structured clock network using buffers and inverters, ensuring balanced skew and
optimal insertion delay. The CTS process includes the following steps:
1. Inputs Required for CTS
To construct an efficient clock tree, several input files and constraints are needed:
1. Placement DEF (Design Exchange Format): Contains the physical placement information of
standard cells and macros.
2. Timing Constraints (SDC - Synopsys Design Constraints): Specifies the target clock
latency, skew, and other constraints.
3. Buffer/Inverter Libraries: Defines the permissible buffers and inverters used for building the
clock tree.
4. Clock Source and Sink Information: Identifies the clock origin and all clock-receiving
elements (flip-flops, latches, etc.).
5. Clock Tree Design Rule Constraints (DRC): Includes:
• Maximum transition limit
• Maximum capacitance limit
• Maximum fan-out limit
• Maximum buffer levels
[Link]-Default Routing (NDR) Rules: Ensures clock nets are routed with wider metal layers
and spacing to mitigate crosstalk.
[Link] Metal Layers for Clock Signals: Specifies which metal layers should be used for
routing clock signals.
2. CTS Execution Steps
The clock tree synthesis process consists of the following steps:
Step 1: Clock Tree Construction
• The tool inserts buffers and inverters in a hierarchical manner to build a balanced clock tree.
• The clock tree follows a buffer-tree structure, where multiple levels of buffers distribute the
clock signal.
Step 2: Skew and Latency Optimization
• Skew refers to the difference in clock arrival times between two registers. The goal is to
minimize skew to ensure synchronous operation.
• Latency is the total delay from the clock source to a register’s clock pin.
• The CTS algorithm balances the skew while keeping the insertion delay within limits.
Step 3: Clock Tree Optimization
Buffers and inverters are adjusted to improve the clock tree performance.
The process ensures:
• Clock paths remain balanced.
• Timing violations are minimized.
• Design rule constraints are met.
Step 4: Post-CTS Timing Analysis
After CTS, a new timing analysis is performed to assess:
• Hold violations (since data arrival times change after CTS adjustments).
• Clock path optimization to meet timing constraints.
• Congestion analysis due to added clock buffers.
3. Outputs of CTS
After the clock tree is built, the following reports are generated:
• CTS DEF File: Updated placement file with clock tree buffers and inverters.
• Latency and Skew Report: Summary of insertion delays and skew across all clock sinks.
• Clock Structure Report: Details of the hierarchical clock tree structure.
• Timing QoR Report: Evaluates the quality of results post-CTS.
 Primary Targets of CTS:
1. Skew Minimization: Ensures minimal timing variations between clock arrival times at
different sequential [Link] avoid setup and hold violations.
2. Insertion Delay Control: Manages clock signal delays to ensure synchronous operation.
Affects overall timing performance.
Effects of CTS on the Design
While CTS significantly improves clock distribution, it also introduces certain challenges:
Increased Congestion:
• The addition of clock buffers may lead to routing congestion.
• Buffer placement can affect nearby signal nets.
Cell Movements:
• Non-clock cells may be displaced to accommodate the clock tree buffers.
• May cause changes in timing and congestion in previously optimized areas.
New Timing Violations:
• Hold violations may appear due to modified clock delays.
• New transition/capacitance violations can arise due to added buffers.
Conclusion
Clock Tree Synthesis is a vital step in physical design that ensures robust and efficient clock
distribution. It transforms an ideal clock network into a practical, optimized structure while
balancing skew and minimizing insertion delay. Post-CTS optimization steps are necessary to
address congestion, timing violations, and routing challenges. Proper CTS implementation
significantly impacts the overall chip performance, power consumption, and manufacturability,
making it one of the most crucial stages in the VLSI design flow.
Clock Tree Synthesis (CTS) is a critical phase in VLSI Physical Design, where the goal is to
distribute the clock signal efficiently to all sequential elements while maintaining minimal skew
and balanced insertion delay. However, completing CTS is not the end—it requires several post-
CTS checks and optimizations to ensure that the design meets timing, congestion, and power
constraints.
Post-CTS Checks: Ensuring a Robust Clock Network
Once CTS is completed, several reports and design checks must be reviewed:
1. Latency Report Analysis
Is the skew minimized?
• Clock skew (the difference in clock arrival times between sequential elements) should be as
small as possible.
Is the insertion delay balanced?
• The insertion delay (time taken for the clock signal to reach the sink pins from the clock
source) should be uniform across different paths to prevent setup and hold violations.
2. Quality of Results (QoR) Report Analysis
Has the timing (especially HOLD) been met?
• After CTS, hold violations become more significant as buffers and inverters are added to the
clock tree.
If timing is not met, what are the causes?
• Possible reasons include high skew, improper constraints, poor clock tree balancing, or
excessive buffering.
3. Utilization & Congestion Report Analysis
Are standard cell utilizations acceptable?
• CTS adds buffers and inverters, which can increase utilization. Overuse of buffers may cause
congestion issues.
Check for global route congestion
• Overloaded clock nets can cause routing congestion that affects signal nets.
4. Placement Legality Check
• Ensure that buffers and inverters added during CTS do not cause placement violations.
• Are any cells overlapping? If yes, re-optimization may be needed.
5. Constraint Verification
• Are the false paths, asynchronous paths, half-cycle paths, and multi-cycle paths properly
constrained?
• If these constraints are missing, timing violations may appear artificially, leading to incorrect
optimization.
 Clock Endpoints in CTS
When CTS is performed, the EDA tool identifies and categorizes clock endpoints into different
types. These endpoints define how the clock network is optimized.
1. Sink Pins (Balancing Pins)
• Sink pins are primary clock endpoints that are considered in delay balancing.
• The tool assigns an insertion delay of zero to all sink pins.
• Used in calculations for skew reduction and delay balancing.
Examples:
• Clock pin on a sequential cell (e.g., Flip-flops, Registers).
• Clock pin on a macro cell (e.g., Memory macros, PLLs).
2. Ignore Pins
• Ignore pins are also clock endpoints, but they are excluded from clock tree timing
calculations.
• These pins do not contribute to skew or insertion delay calculations.
Examples:
• Source pins of a clock tree in the fanout of another clock.
• Non-clock input pins of sequential elements.
• Output ports.
3. Floating Pins
• Floating pins are like stop pins, but they consider internal macro delays within the clock path.
4. Exclude Pins
• These pins are ignored only for clock balancing, but the CTS tool still fixes the design rule
constraints (DRC).
5. Nonstop Pins
• These pins allow the clock tree to continue tracing against default behavior.
• Used in cases where divider clocks or sequential elements require clock propagation beyond
standard rules.
Why Clock Routes Are Given Higher Priority Than Signal Nets?
The clock tree is not routed like normal signals—it is given a higher priority because:
• Clock propagation happens after placement to get accurate delay and skew estimation.
• The clock network is the most frequently switching signal, leading to dynamic power
dissipation.
• Clock tree needs to be routed before signal nets to ensure minimal skew and delay
mismatches.
• By optimizing clock routing first, signal nets can then be routed efficiently around the clock
tree.
CTS Optimization Techniques
Once CTS is completed, several optimization techniques are applied to improve its performance
and robustness:
1. Buffer & Gate Sizing
• Adjusting buffer and inverter sizes to balance delay and minimize skew.
2. Buffer Relocation
• Moving buffers to better locations to reduce capacitance and resistance effects.
3. High Fanout Net (HFN) Synthesis
• Handling high-fanout clock nets by inserting buffers to prevent large delays.
4. Delay Insertion
• Adding buffers to equalize insertion delays and balance the clock arrival time.
5. Fixing Max Transition & Capacitance Violations
• Ensuring that the clock signal transition time and capacitance loading are within acceptable
limits.
6. Fixing Max Fanout Violations
• Managing fanout load balancing by adding repeaters or extra buffers to optimize distribution.
7. Minimizing Disturbances to Other Cells
• Ensuring that CTS optimizations do not negatively impact data paths and signal nets.
Challenges in CTS & Their Solutions
Challenge: High Skew
• Solution: Use buffer balancing, delay insertion, and optimized tree structures to reduce skew.
Challenge: Excessive Clock Buffer Insertion
• Solution: Use HFN synthesis to minimize unnecessary buffers.
Challenge: Congestion Due to Clock Routing
• Solution: Perform early congestion analysis and optimize buffer placement to spread the
load.
Challenge: Hold Violations After CTS
• Solution: Apply hold fixing techniques like delay padding and gate sizing.
Conclusion & Key Takeaways
• CTS is not just about building a clock tree—it is about ensuring timing closure, minimizing
skew, and optimizing power and congestion.
• Post-CTS checks such as latency analysis, utilization, congestion, and placement legality are
crucial.
• Different types of clock endpoints (sink pins, ignore pins, floating pins, exclude pins) help
define clock optimization rules.
• Clock routing is prioritized over signal nets due to its impact on power and timing.
• Optimization techniques like buffer sizing, fanout balancing, delay insertion, and congestion
reduction help refine CTS.
 Routing in Physical Design
Routing is a crucial phase in VLSI Physical Design, where the physical connections between
various components, such as standard cells, macros, and input/output (I/O) ports, are established
according to design constraints and manufacturing rules. It plays a key role in determining the
overall performance, power consumption, and manufacturability of an integrated circuit (IC).
After Placement and Clock Tree Synthesis (CTS), routing ensures that all nets are correctly
connected while maintaining timing, congestion, and design rule constraints. This process
requires careful optimization to achieve the best Quality of Results (QoR) in terms of timing
closure, signal integrity, and power distribution.
Inputs to Routing
Before initiating the routing phase, several essential files and constraints must be provided to
ensure that the process adheres to the design specifications and meets timing requirements. The
primary inputs for routing are as follows:
1. Netlist:- The netlist contains the logical connectivity between standard cells, macros, and I/O
ports. It serves as a blueprint for routing the signals across the IC.
2. LEF/Technology File:- The Library Exchange Format (LEF) or technology file defines the
physical and electrical characteristics of the standard cells and metal layers. This includes:
• Metal layers and their resistivity
• Via definitions and routing rules
• Spacing constraints and width limitations
3. DEF/UTF+ Files:-The Design Exchange Format (DEF) or UTF+ files contain the design
layout, standard cell placements, and macro locations before routing. These files serve as the
starting point for the routing tool.
4. SDC File (Synopsys Design Constraints):-The SDC file contains critical timing
constraints such as:
• Clock definitions
• Input and output delays
• Timing budgets for various paths
Ensuring that the routing adheres to the constraints specified in the SDC file is essential for
achieving timing closure.
5. Timing Budget for Critical Nets
High-speed and latency-sensitive signals require dedicated routing paths to meet setup and hold
time constraints. The timing budget ensures that these critical nets receive appropriate attention
during routing.
 Outputs of Routing
Upon completion of the routing phase, several key files are generated that are essential for the
sign-off process, verification, and tape-out preparation. These include:
1. Geometric Layout of All Nets (.GDS)
• The Graphic Data System (GDS) file contains the final routed metal layers and
interconnections.
• It is used for fabrication and is one of the primary deliverables sent to the foundry.
2. Standard Parasitic Exchange Format (SPEF) File
• The SPEF file captures the resistance (R), capacitance (C), and inductance (L) of the routed
nets.
• It is essential for post-route Static Timing Analysis (STA) to ensure that routing parasitics do
not cause timing violations.
3. Updated SDC File
• After routing, the SDC file is updated to reflect changes in clock latencies, delays, and
additional constraints that emerged during the process.
• These outputs are used in subsequent sign-off analysis, Design Rule Check (DRC), and
timing verification to ensure the design is ready for manufacturing.
Checklist Before Routing
Before initiating routing, several critical checks must be performed to ensure a smooth and
efficient process. The pre-routing checklist includes:
1. Placement Completed:- All standard cells and macros must be placed in their final
positions. Any placement congestion must be resolved to avoid routing issues.
2. Clock Tree Synthesis (CTS) Completed:- The clock network must be built and
optimized to minimize skew and insertion delay. Improper CTS may lead to significant timing
violations post-routing.
3. Power and Ground (P/G) Nets Routed:- The power delivery network (PDN) must be
implemented before signal routing to ensure stable voltage levels across the design.
4. Estimated Congestion – Acceptable :- Routing congestion must be analyzed to prevent
overlapping routes and design rule violations.
5. Estimated Timing – Acceptable (~0 ns Slack):- Before routing, the estimated slack
should be within acceptable limits to prevent excessive timing violations.
6. Estimated Maximum Capacitance/Transition – No Violations:- Routing must not
exceed the maximum capacitance and transition limits set by the technology constraints.
Types of Routing
Routing is performed in multiple stages, each focusing on a specific set of nets and design
constraints. The different types of routing include:
1. Power Routing
• Establishes power (VDD) and ground (VSS) connections to distribute power across the
design.
• Uses thicker metal layers to handle higher current loads and reduce IR drop.
• Ensures proper electromigration control to improve long-term reliability.
2. Clock Routing
• Routes the clock network while maintaining minimal skew and controlled insertion delay.
• Ensures that all sequential elements receive a synchronized clock signal.
• Requires shielding and spacing techniques to minimize crosstalk and interference.
3. Signal Routing
• Connects standard cells as per the netlist using available metal layers.
• Follows design rules such as minimum spacing, layer restrictions, and via constraints.
• Avoids short circuits, antenna violations, and excessive congestion.
4. Critical Routing
• Targets high-speed and timing-sensitive paths such as data buses, high-frequency signals,
and control logic paths.
• Uses wider metal traces and shielding techniques to minimize resistance and capacitance.
• Ensures that setup and hold timing is met for critical nets.
Conclusion
Routing is one of the most complex and optimization-intensive phases in VLSI Physical Design.
It involves:
• Connecting all components while following design constraints.
• Minimizing congestion, timing violations, and power issues.
• Ensuring signal integrity and manufacturability.
The next step after Routing is sign-off analysis, where various Design Rule Checks (DRC),
Electrical Rule Checks (ERC), and Timing Analysis are performed to validate the final layout.
Routing is one of the most critical steps in VLSI Physical Design, where electrical connections
between different components of an integrated circuit (IC) are established using metal
interconnects. The goal of routing is to ensure that all signals are connected efficiently while
minimizing wire length, reducing congestion, and adhering to design rules for manufacturability.
Routing is performed in multiple stages to manage the complexity of modern designs. This article
explores the various stages of routing, their importance, challenges, and final verification steps.
Why Is Routing Important in VLSI?
Ensures Electrical Connectivity:
Routing creates metal interconnections between different circuit components such as standard
cells, macros, IO pads, and power/ground networks.
Impacts Performance and Power:
The routing quality affects signal delay, power consumption, and overall chip performance. Poor
routing can lead to excessive resistance, capacitance, and signal integrity issues.
Reduces Congestion and Design Violations:
Efficient routing minimizes wire congestion, preventing design rule violations (DRC errors) such
as shorts, spacing violations, and antenna effects.
Optimizes Manufacturing Yield:
Adhering to foundry design rules ensures that the chip can be successfully manufactured without
defects.
Stages of Routing
1. Global Routing
Global Routing is the first stage of routing, where the tool determines an approximate path for
each net without making actual metal connections. Instead, the design is divided into smaller
regions called Global Routing Cells (GCells), and the tool assigns a high-level routing path to
these cells.
Key Tasks in Global Routing:
[Link] the design into routing tiles
• The design is partitioned into a grid of GCells.
• Each GCell contains horizontal and vertical routing resources.
[Link] nets to routing layers
• Determines which metal layers will be used for each signal.
• Ensures that critical nets have shorter, less resistive paths.
[Link] wirelength and congestion
• Optimizes the total wirelength to reduce resistance and delay.
• Balances congestion across different routing regions.
[Link] congested areas
• Congested areas are identified where multiple signals compete for the same routing
resources.
• Helps in planning design modifications to improve routability.
Limitations of Global Routing:
• Does not perform actual metal connections
• Does not resolve design rule violations
• Only provides an estimate of congestion and wirelength
2. Track Assignment
Once Global Routing determines the path for each net, Track Assignment allocates specific tracks
on each metal layer for routing. It ensures that signals are evenly distributed and overlapping
wires are minimized.
Key Tasks in Track Assignment:
[Link] horizontal and vertical tracks
• Tracks are assigned based on the available metal layers.
• Horizontal tracks are placed on even metal layers, and vertical tracks on odd metal layers
(preferred routing directions).
[Link] overlapping wires
• Nets that overlap are rerouted to different tracks.
• Helps prevent routing congestion and improves manufacturability.
[Link] global routes with actual metal paths
• Converts approximate paths (from Global Routing) into real metal interconnects.
Challenges in Track Assignment:
• Not all DRC violations are resolved
• Signal integrity (SI) and Crosstalk issues may still exist
• Some nets may still need rerouting due to congestion

3. Detailed Routing
Detailed Routing is the most critical stage of routing where actual metal connections are placed
on the chip layout. It follows the routing plan laid out in Global Routing and Track Assignment
but ensures that all design rule constraints are met.
Key Tasks in Detailed Routing:
Placing metal wires
The router determines the exact path for each wire, ensuring that all connections are completed.
• Resolving Design Rule Violations (DRC)
• Fixes spacing violations, shorts, and antenna effects.
• Ensures that all routed wires follow foundry-specific DRC constraints.
Connecting Standard Cells, IO Pads, and Macros
• Routes signals to their respective endpoints (macros, standard cells, IO pads).
Optimizing Signal Integrity (SI)
• Reduces crosstalk between neighboring signals.
• Ensures that high-speed signals are routed efficiently.
Minimizing Timing Violations
• Ensures that signals meet setup and hold time requirements.
• Critical nets are assigned shorter, less resistive paths.
Challenges in Detailed Routing:
• High routing complexity in dense designs
• DRC and Timing violations require multiple iterations to fix
• Routing congestion can still cause delays
4. Search and Repair
After the first pass of Detailed Routing, a Search and Repair process is executed to identify and
fix remaining routing violations.
Key Tasks in Search and Repair:
Locating Shorts and Spacing Violations
• The tool scans the design for overlapping wires, incorrect spacing, and routing conflicts.
Fixing Violations Through Rerouting
• Problematic nets are rerouted to alternative paths.
Optimizing Final Routing for Manufacturability
• Ensures that the design is DRC-clean and sign-off ready.

5. Post-Routing Checklist
Before finalizing the routing, a post-routing checklist is performed to verify that all constraints
are met:
Special Cells Insertion:
• Filler cells and ECO cells are inserted to maintain power continuity
Final Routing Utilization Analysis:
• Total metal layer usage is analyzed to prevent excessive congestion.
Power Analysis:
• IR drop and Electromigration checks are performed.
Timing Analysis:
• Ensures that setup and hold timing constraints are met.
Design Rule Checks (DRC):
• Ensures that the layout is DRC clean and ready for tape-out.
 Timing Closure in VLSI Design
Timing closure is one of the most crucial steps in VLSI physical design, ensuring that a circuit
meets all timing constraints across various process, voltage, and temperature (PVT) conditions.
The primary goal of timing closure is to eliminate setup violations, hold violations, clock skew,
and signal propagation delays while optimizing for performance, power, and area (PPA).
Without achieving timing closure, a chip might not function as intended, leading to functional
failures, degraded performance, higher power consumption, or even silicon re-spins, which are
costly and time-consuming.

Why Timing Closure Matters?

• Ensures Functional Correctness – Prevents timing violations that could cause logic failures.
• Optimizes Performance – Helps the circuit operate at the desired clock frequency without
timing bottlenecks.
• Enhances Reliability – Ensures the chip functions correctly under different operating
conditions.
• Reduces Power Consumption – Helps optimize the power-performance tradeoff.
• Minimizes Manufacturing Risks – Reduces costly design re-spins and accelerates time to
market.
Key Steps in Timing Closure
Timing closure is an iterative process involving multiple design steps, each contributing to the
overall optimization of timing, power, and area.
1. Static Timing Analysis (STA)
Static Timing Analysis (STA) is used to evaluate all timing paths in the design without requiring
dynamic simulation. It identifies setup and hold violations and ensures that data signals arrive at
the correct time relative to clock edges.
Inputs for STA
• Gate-Level Netlist (from synthesis or place-and-route stages)
• Library Files (Libs) & Technology Files – Define cell delays and process parameters.
• Timing Constraints (SDC File) – Defines clock period, clock skew, delays, and false paths.
• Parasitic Extraction Files (SPEF/RC Extraction Data) – Provides wire resistance and
capacitance values.
Outputs of STA
• Timing Reports (Setup & Hold Violations) – List failing paths and delay issues.
• Slack Reports – Show timing margins for paths.
• Clock Skew and Jitter Analysis – Ensures clock signal is well-distributed.
• Critical Path Report – Highlights the slowest timing paths that need optimization.

2. Iterative Optimization for Timing Closure

Once STA identifies timing violations, various optimizations are performed iteratively to fix
them.
Key Optimization Techniques:
• Cell Sizing – Resizing standard cells to adjust drive strength and propagation delay.
 • Buffer Insertion – Adding buffers to enhance signal strength and avoid signal degradation.
• Gate Duplication – Reducing the fanout load of a single gate by duplicating it.
• Logic Restructuring – Optimizing logic to reduce critical path delay.
• Metal Layer Selection – Using lower resistance higher metal layers for critical paths.
• Placement and Routing Optimization – Adjusting layout for better signal integrity and
reduced delays.

3. Clock Tree Synthesis (CTS) – Handling Clock Skew & Jitter

The clock network plays a critical role in timing closure, as it drives all sequential elements (flip-
flops) in the design. Improper clock distribution can introduce clock skew, jitter, and timing
violations.
Key Aspects of CTS:
• Clock Skew Minimization – Ensuring uniform clock arrival at all registers.
• Clock Buffering & Gating – Optimizing clock buffers to reduce power and delay.
• Jitter Reduction – Avoiding variations in clock edges that may cause timing failures.

4. Physical Design Adjustments – Placement & Routing Optimization

Once the synthesis and CTS stages are completed, further placement and routing optimizations
are applied to improve timing.
Techniques Used:
• Placement Optimization – Adjusts standard cell locations to reduce wirelength.
• Routing Optimization – Ensures signal integrity and minimizes crosstalk delays.
• Shielding High-Speed Nets – Reduces electromagnetic interference (EMI) and noise effects.
• Layer Assignment – Uses higher metal layers for timing-critical nets.
• After placement and routing are optimized, a post-route STA is performed to recheck timing
violations.

5. Sign-Off Verification – Ensuring Final Timing Closure

Before the design is finalized and sent for fabrication (tape-out), sign-off verification is performed
to ensure that timing closure has been fully achieved.
Sign-Off Inputs:
• Final Post-Route Netlist – The complete gate-level representation.
• Final Parasitic Extraction (SPEF) – Includes wire resistance and capacitance effects.
• Sign-Off Timing Constraints (SDC) – Defines clock and delay constraints.
• Process Corners (SS, FF, TT, etc.) – Ensures design works across different process variations.
Sign-Off Outputs:
• Final Setup and Hold Slack Reports – Must be zero or positive to meet timing.
• Clock Skew & Jitter Analysis – Ensures the clock distribution is optimized.
• Signal Integrity (SI) & Noise Reports – Ensures no excessive delay due to crosstalk.
• Power Analysis Reports – Checks total power consumption and IR drop.
• DRC (Design Rule Check) and LVS (Layout vs Schematic) Reports – Ensure
manufacturability.
In VLSI design, signoff is the final and most critical stage where the entire design undergoes
rigorous verification before fabrication. It ensures that the chip meets all functional, timing,
power, and manufacturability requirements. Once the design is successfully verified, it is sent for
tape-out, marking the transition from design to silicon fabrication.
1. Signoff: The Final Validation Step
Signoff is the process of performing final verification checks on the IC layout and ensuring it is
error-free and ready for fabrication. If any issues are found, designers must iterate fixes before
proceeding to tape-out.
Signoff Checks in VLSI
[Link] Signoff (Static Timing Analysis - STA)
• Ensures that setup and hold timing constraints are met across all corners (PVT variations:
Process, Voltage, and Temperature).
• Uses tools like PrimeTime (Synopsys), Tempus (Cadence), or Innovus (Cadence).
[Link] Signoff (IR Drop & Electromigration - EM)
• IR Drop Analysis: Ensures that power and ground rails provide sufficient voltage without
excessive drops.
• Electromigration (EM) Checks: Ensures metal wires can handle the required current without
degradation over time.
• Tools used: RedHawk, Voltus, PrimePower.
[Link] Integrity (SI) Check
• Ensures that there is no excessive crosstalk or glitches due to coupling capacitance between
adjacent nets.
• Tools: PrimeTime SI, RedHawk, Totem.
[Link] Signoff (Clock Skew & Jitter Analysis)
• Ensures the clock tree is optimized with minimal skew and jitter.
• Performed using STA tools.
• Physical Verification Signoff
This ensures the layout follows manufacturing rules and matches the circuit design.
2. Physical Verification in Signoff
The layout must be free of physical design errors before it is sent for manufacturing.
Design Rule Check (DRC)
• Ensures that the layout follows foundry-defined design rules (spacing, width, via
requirements, etc.).
• Violations may cause manufacturing defects or yield issues.
• Tools: Calibre DRC (Mentor), Pegasus DRC (Cadence).
Layout vs. Schematic (LVS) Check
 • Compares the layout netlist with the schematic netlist to ensure that the layout matches the
intended circuit design.
• A LVS-clean design means no missing or extra connections exist.
• Tools: Calibre LVS, PVS LVS.
Antenna Check
Prevents charge accumulation during fabrication, which can damage transistors.
If violations exist, diodes or jumper vias are inserted.
Tools: Calibre, Pegasus.
Metal Density & Planarity Checks
• Ensures uniform metal density across the chip to prevent defects in the Chemical Mechanical
Polishing (CMP) process.
• Dummy metal fills are added to maintain uniformity.
Electromagnetic Compatibility (EMC) Check
• Ensures that high-speed signals do not interfere with other signals in the design.
• Once all checks are DRC/LVS clean, the design is converted into GDSII/OASIS format, the
standard format used for fabrication.
3. Tape-Out: The Final Handoff to Fabrication
Once all signoff checks are passed, the design is ready for tape-out, which means it is being sent
to the foundry for manufacturing.
Tape-Out Process
[Link] GDSII Submission
• The verified layout is exported in GDSII/OASIS format and submitted to the semiconductor
foundry.
• The foundry uses this data to create photomasks for lithography.
[Link] Generation
• The GDSII data is used to create photomasks, which are used to etch patterns onto silicon
wafers.
• Wafer Fabrication Begins
• The actual manufacturing process starts, where the chip is fabricated layer by layer using
photolithography, deposition, and etching.
Once the fabrication is complete, silicon wafers are tested and undergo wafer-level validation
before packaging and assembly.
Thank You

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