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Physical Design Notes

The document outlines the ASIC design flow and details the physical design process, including key steps such as partitioning, floorplanning, placement, and routing. It also covers various verification and analysis methods like DRC, LVS, timing, and power analysis. The document serves as a comprehensive guide to the essential components and stages involved in ASIC physical design.

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0% found this document useful (0 votes)
3 views3 pages

Physical Design Notes

The document outlines the ASIC design flow and details the physical design process, including key steps such as partitioning, floorplanning, placement, and routing. It also covers various verification and analysis methods like DRC, LVS, timing, and power analysis. The document serves as a comprehensive guide to the essential components and stages involved in ASIC physical design.

Uploaded by

arunrevanth.n
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

ASIC Physical Design

2
Outline
• ASIC Design Flow
• Physical Design
— Introduction to Physical Design
— Physical Design Inputs
— Physical Design Flow
▫ Import Design & Partitioning
▫ Floorplanning & Power planning
▫ Placement & Placement Optimizations
▫ CTS & CTS Optimizations
▫ Routing & Routing Optimizations
▫ Physical Verification (DRC, LVS, ERC)
▫ DFM Checks
▫ Formal Verification (LEC)
▫ Parasitic Extraction (RC Extraction)
▫ Timing Analysis (STA), Power Analysis & IR Drop Analysis
▫ Tapeout
3
ASIC Physical Design
ASIC Design Flow
Partitioning
System Specification

Floor Planning
ENTITY test is Architectural Design
port a: in bit; end
ENTITY test; RTL Design Placement
and Verification
F F F F F F
F F F F F F
Synthesize the F F F F F F CTS
Design F
F
F
F
F F
F F
F
F
F
F

Placement & Routing


PHYSICAL Routing
DRC DESIGN
LVS Signoff Parasitic Extraction
ERC
Mask Preparation
Physical Verification

Fabrication
Formal Verification
Packaging and
Testing Static Timing Analysis

Chip Power Analysis


IR-Drop Analysis 4

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