ASIC Physical Design
2
Outline
• ASIC Design Flow
• Physical Design
— Introduction to Physical Design
— Physical Design Inputs
— Physical Design Flow
▫ Import Design & Partitioning
▫ Floorplanning & Power planning
▫ Placement & Placement Optimizations
▫ CTS & CTS Optimizations
▫ Routing & Routing Optimizations
▫ Physical Verification (DRC, LVS, ERC)
▫ DFM Checks
▫ Formal Verification (LEC)
▫ Parasitic Extraction (RC Extraction)
▫ Timing Analysis (STA), Power Analysis & IR Drop Analysis
▫ Tapeout
3
ASIC Physical Design
ASIC Design Flow
Partitioning
System Specification
Floor Planning
ENTITY test is Architectural Design
port a: in bit; end
ENTITY test; RTL Design Placement
and Verification
F F F F F F
F F F F F F
Synthesize the F F F F F F CTS
Design F
F
F
F
F F
F F
F
F
F
F
Placement & Routing
PHYSICAL Routing
DRC DESIGN
LVS Signoff Parasitic Extraction
ERC
Mask Preparation
Physical Verification
Fabrication
Formal Verification
Packaging and
Testing Static Timing Analysis
Chip Power Analysis
IR-Drop Analysis 4