DSDV – BEC654A

Module 3B
Dataflow Modeling
• The default value for drive strength is strong1 and strong0. The delay value
is also optional and can be used to specify delay on the assign statement.
This is like specifying delays for gates. Continuous assignments have the
following characteristics:
• The left hand side of an assignment must always be a scalar or vector net
or a concatenation of scalar and vector nets. It cannot be a scalar or vector
register.
• Continuous assignments are always active. The assignment expression is
evaluated as soon as one of the right hand- side operands changes and the
value is assigned to the left-hand-side net.
• The operands on the right-hand side can be registers or nets or function
calls. Registers or nets can be scalars or vectors.
• Delay values can be specified for assignments in terms of time units. Delay
values are used to control the time when a net is assigned the evaluated
value.
• This feature is similar to specifying delays for gates. It is very useful in
modeling timing behavior in real circuits.
Implicit Continuous Assignment
• Instead of declaring a net and then writing a continuous assignment
on the net, Verilog provides a shortcut by which a continuous
assignment can be placed on a net when it is declared.
• There can be only one implicit declaration assignment per net
because a net is declared only once.
Implicit Net Declaration
• If a signal name is used to the left of the continuous assignment, an
implicit net declaration will be inferred for that signal name.
• If the net is connected to a module port, the width of the inferred net
is equal to the width of the module port.
Delays
• Delay values control the time between the change in a right-hand-
side operand and when the new value is assigned to the left-hand
side.
• Three ways of specifying delays in continuous assignment statements
are
• regular assignment delay,
• implicit continuous assignment delay, and
• net declaration delay.
Regular Assignment Delay
• The first method is to assign a delay value in a continuous assignment
statement.
• The delay value is specified after the keyword assign.
• Any change in values of in1 or in2 will result in a delay of 10 time units
before re-computation of the expression in1 & in2, and the result will be
assigned to out.
• If in1 or in2 changes value again before 10 time units when the result
propagates to out, the values of in1 and in2 at the time of re-computation
are considered.
• This property is called inertial delay. An input pulse that is shorter than the
delay of the assignment statement does not propagate to the output.
Implicit Continuous Assignment Delay
• An equivalent method is to use an implicit continuous assignment to
specify both a delay and an assignment on the net.
//implicit continuous assignment delay
wire #10 out = in1 & in2;
//same as wire out;
assign #10 out = in1 & in2;
The declaration above has the same effect as defining a wire out and
declaring a continuous assignment on out.
Net Declaration Delay
• A delay can be specified on a net when it is declared without putting
a continuous assignment on the net. If a delay is specified on a net
out, then any value change applied to the net out is delayed
accordingly. Net declaration delays can also be used in gate-level
modeling.
Expressions
Operands
• Operands can be any one of the data types defined, Data Types.
• Some constructs will take only certain types of operands.
• Operands can be constants, integers, real numbers, nets, registers,
times, bit-select (one bit of vector net or a vector register), part-select
(selected bits of the vector net or register vector), and memories or
function calls
Operators
• Operators act on the operands to produce desired results.
• Verilog provides various types of operators.
Operator Types
Arithmetic Operators
Binary operators
• Binary arithmetic operators are
multiply (*), divide (/), add (+),
subtract (-), power (**), and
modulus (%). Binary operators
take two operands.
Logical Operators
Relational Operators
• Relational operators are greater-
than (>), less-than (=), and less-
than-or-equal-to (<=).
• If relational operators are used
in an expression, the expression
returns a logical value of 1 if the
expression is true and 0 if the
expression is false.
• If there are any unknown or z
bits in the operands, the
expression takes a value x.
Equality Operators
Bitwise Operators
 Reduction Operators
• Reduction operators are and (&), nand
(~&), or (|), nor (~|), xor (^), and xnor
(~^, ^~).
• Reduction operators take only one
operand.
• Reduction operators perform a bitwise
operation on a single vector operand
and yield a 1-bit result.
• The difference is that bitwise
operations are on bits from two
different operands, whereas reduction
operations are on the bits of the same
operand.
• Reduction operators work bit by bit
from right to left.
Shift Operators
• Shift operators are right shift ( >>), left
shift (<<), arithmetic right shift (>>>),
and arithmetic left shift (<<<). Regular
shift operators shift a vector operand
to the right or the left by a specified
number of bits.
• The operands are the vector and the
number of bits to shift.
• When the bits are shifted, the vacant
bit positions are filled with zeros.
• Shift operations do not wrap around.
Arithmetic shift operators use the
context of the expression to
determine the value with which to fill
the vacated bits.
Concatenation Operator
• The concatenation operator ( {, } )
provides a mechanism to append
multiple operands.
• The operands must be sized. Unsized
operands are not allowed because the
size of each operand must be known
for computation of the size of the
result.
• Concatenations are expressed as
operands within braces, with commas
separating the operands.
• Operands can be scalar nets or
registers, vector nets or registers, bit-
select, part-select, or sized constants.
 Replication Operator
• Repetitive concatenation of the
same number can be expressed by
using a replication constant.
• A replication constant specifies how
many times to replicate the number
inside the brackets ( { } ).
Conditional Operator
• The conditional operator(?:) takes
three operands.
• Usage: condition_expr ? true_expr :
false_expr ;
• The condition expression
(condition_expr) is first evaluated.
• If the result is true (logical 1), then the
true_expr is evaluated.
• If the result is false (logical 0), then
the false_expr is evaluated.
• If the result is x (ambiguous), then
both true_expr and false_expr are
evaluated and their results are
compared, bit by bit, to return for
each bit position an x if the bits are
different and the value of the bits if
they are the same.
Operator Precedence
4-to-1 Multiplexer
Method 2: conditional operator

• Method 1: logic equation