Microelectronics Lecture Note 2

3.1 Basic Operation of a Microprocessor: Instruction Fetch, Decode, and Execute

The microprocessor performs its tasks by following a sequence of operations known as the fetch-
decode-execute cycle. This cycle enables the CPU to retrieve instructions, interpret them, fetch
any required data, and perform the specified operation.
A. Fetching the Instruction
 The Program Counter (PC) contains the address of the next instruction.
 This address is placed on the address bus.
 The instruction at the addressed memory location is sent to the Instruction Register (IR)
through the data bus.
 The PC is incremented to point to the next instruction.
B. Decoding the Instruction
 The Control Unit reads and decodes the opcode in the IR.
 The microprocessor determines:
o What operation is to be performed.

o Which operands or registers are involved.

o Whether additional memory or I/O access is needed.

C. Fetching More Data (if needed)

 If the instruction requires data (e.g., from memory or an I/O port), the microprocessor:
o Places the address of the required data on the address bus.

o Sends a control signal (like RD̅ ) to initiate a read.

o Fetches the data into a register.

D. Executing the Instruction

 The ALU, register file, and control logic perform the required operation.
 Results may be written back to a register, memory, or I/O device.
 Processor status flags may be updated (e.g., Zero, Carry).

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3.2 Fetch-Execute Sequence for a Simple Data Transfer Instruction (Accumulator ↔
Memory/I/O Port)
Example Instruction:
LDA 3000H ; Load the contents of memory address 3000H into the accumulator (A)
Fetch-Execute Sequence:

Stage Action

Fetch Microprocessor places address of instruction (e.g., 1000H) on address bus.

Sends RD̅ to read opcode LDA.

Decode Control Unit decodes LDA, identifies memory address operand follows.

Fetch Operand Fetches 2-byte address (3000H) from next memory locations (1001H, 1002H).

Execute Places 3000H on address bus, activates RD̅ .

Reads content from 3000H into accumulator A.

I/O Port Transfer Example:

IN 01H ; Input from I/O port 01H into accumulator

Stage Action

Fetch Microprocessor reads opcode IN from memory.

Decode Control Unit decodes and identifies I/O port address.

Execute Sends I/O port address (01H) to address bus.

Activates IOR̅ , I/O port places data on data bus.

Data is loaded into the accumulator.

3.3 Execute Sequence for a Simple Jump Instruction

Example Instruction:
JMP 2050H ; Unconditional jump to memory address 2050H

Execution Steps:
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Step Description

1 Fetch opcode JMP from memory using PC.

2 Decode instruction to identify it as a jump.

3 Fetch the 2-byte operand (2050H) from next memory locations.

4 Load the address 2050H into the Program Counter (PC).

5 The next instruction fetch will begin from address 2050H.

This operation causes the microprocessor to stop sequential execution and begin fetching from a
new location, thus changing the flow of the program.
3.4 Interpreting Timing Diagrams for Instruction Execution
Purpose of Timing Diagrams
Timing diagrams show the temporal relationship between clock cycles and signal changes on
microprocessor buses (address, data, and control lines). They are essential for understanding how
instructions interact with hardware components in real time.
Timing Diagram for LDA 3000H (Simplified)

Cycle T1 T2 T3 T4

Clock ↑↓↑↓ ↑↓↑↓ ↑↓↑↓ ↑↓↑↓

Address Bus 1000H (LDA) 1001H (Low byte) 1002H (High byte) 3000H (Memory)

Control Bus RD̅ = 0 RD̅ = 0 RD̅ = 0 RD̅ = 0

Data Bus Opcode LDA 00H (Low of 3000H) 30H (High) Data from 3000H

Explanation:
 T1–T3: Fetch opcode and operand.
 T4: Actual execution of the LDA instruction, retrieving data from the effective memory
address.
Key Signal Lines in Diagram
 Clock: Provides timing reference for all operations.
 Address Bus: Changes at each T-cycle for new memory/I/O locations.
 Data Bus: Carries opcode, operand, or result.
 Control Bus: Signals like RD̅ , WR̅ , IOR̅ , IOW̅ enable or disable devices.

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Conclusion
This lecture has covered:
 How a microprocessor processes instructions through the fetch-decode-execute cycle.
 The detailed sequence for data transfer and jump instructions.
 Interpretation of timing diagrams to analyze real-time data movement and signal
coordination.
These concepts are essential for:
 Understanding the internal workings of a microprocessor.
 Designing reliable embedded systems.
 Troubleshooting hardware-level faults using logic analyzers or oscilloscopes.
4.1 Main Types of Instruction Groups with Examples
The instruction set of a microprocessor is the complete set of commands that the processor can
execute. These instructions are categorized into different groups based on their functionality.
Each group plays a unique role in executing operations involving data movement, arithmetic
processing, logical evaluation, branching, or I/O operations.
A. Data Transfer Instructions
Purpose: Move data from one location to another — between registers, memory, or I/O ports.
Examples:
 MOV A, B – Move the content of register B to register A.
 MVI C, 0AH – Load immediate data (0AH) into register C.
 LDA 3000H – Load content of memory address 3000H into the accumulator.
 STA 3050H – Store content of accumulator to memory address 3050H.
 IN 01H – Read data from I/O port 01H into the accumulator.
 OUT 02H – Write content of accumulator to I/O port 02H.

B. Arithmetic and Logic Instructions

Purpose: Perform arithmetic or logical operations on data stored in registers or memory.

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Arithmetic Examples:
 ADD B – Add contents of register B to accumulator.
 SUB C – Subtract contents of register C from accumulator.
 INR D – Increment register D by 1.
 DCR E – Decrement register E by 1.
Logic Examples:
 ANA H – Logical AND of contents of H with accumulator.
 ORA L – Logical OR of contents of L with accumulator.
 XRA A – Logical XOR of accumulator with itself (result: 00H).
 CMA – Complement the accumulator content (1’s complement).

C. Test and Branch Instructions

Purpose: Evaluate conditions and control the flow of program execution.
Test Instructions (Affect Flags):
 CMP B – Compare content of register B with accumulator.
 CPI 0AH – Compare immediate value 0AH with accumulator.
 BIT 5, A (in some architectures) – Test bit 5 of register A.
Branch Instructions:
 Unconditional Branch:
o JMP 2000H – Jump to memory location 2000H.

 Conditional Branch:
o JC 2500H – Jump to 2500H if Carry flag is set.

o JZ 3000H – Jump to 3000H if Zero flag is set.

o JNZ 4000H – Jump to 4000H if Zero flag is not set.

 Call and Return:

o CALL 5000H – Call subroutine at 5000H.

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 o RET – Return from subroutine.

 Restart:
o RST 7 – Restart from a specific vector location.

4.2 Addressing Modes and Their Differences

Addressing modes determine how the microprocessor identifies the operand of an instruction.
The choice of addressing mode affects the flexibility, size, and speed of the instruction.
A. Immediate Addressing Mode
Definition: The operand (data) is specified explicitly within the instruction.
Example:
MVI A, 0AH ; Load immediate value 0AH into A
Use Case: When a known constant is to be loaded into a register.
B. Register Addressing Mode
Definition: The operand is in a register, and the instruction specifies the register.
Example:
MOV A, B ; Copy contents of register B into A
Use Case: For fast data transfer within the CPU.
C. Direct Addressing Mode
Definition: The instruction specifies the memory address where the operand resides.
Example:
LDA 3000H ; Load accumulator with contents of memory location 3000H
Use Case: Accessing data stored at known memory addresses.

D. Indirect Addressing Mode

Definition: The memory address of the operand is held in a register pair.
Example:
MOV A, M ; Load accumulator with data from memory address in HL pair
Use Case: Useful when dealing with dynamic memory access like array traversal.

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Comparison Table of Addressing Modes

Addressing Mode Source of Operand Example Advantage

Immediate Value in instruction MVI A, 0AH Simple and fast for constants

Register Register specified MOV A, B Fast execution

Direct Specific memory location LDA 3000H Clear access to known memory

Indirect Address held in register MOV A, M Useful for dynamic memory access

Conclusion
Understanding instruction types and their addressing modes is fundamental to mastering
microprocessor programming and microelectronics. Each instruction group serves a specific
functional domain—data movement, computation, logical operations, and program control. The
addressing modes provide various levels of flexibility and control in accessing data, enabling
efficient system and application development.
5.1 Understanding Algorithms in Problem Solving
Before a problem can be solved by a microprocessor, it must be broken down into a logical
sequence of steps, called an algorithm.
Definition of Algorithm
An algorithm is a finite, step-by-step sequence of well-defined instructions that solve a problem
or perform a task.
Key Properties of an Algorithm
 Finiteness: It must terminate after a finite number of steps.
 Definiteness: Each step must be clearly and unambiguously defined.
 Input: It should have zero or more inputs.
 Output: It should produce at least one output.
 Effectiveness: Each step should be basic enough to be carried out, ideally by a machine.

5.2 Defining an Algorithm (Drawing the Program) for a Sample Problem

Problem Example
Write a program to add two 8-bit numbers, store the result in a memory location, and halt.

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Algorithm
1. Load the first number from memory (e.g., address 2000H) into the accumulator.
2. Add the second number from memory (e.g., address 2001H) to the accumulator.
3. Store the result in memory (e.g., address 2002H).
4. Halt the program.
Machine-Level Program (8085 Assembly)
LDA 2000H ;Load first number into A
ADD M ; Add number from memory (M points to 2001H)
MOV C, A ; Move result into register C
STA 2002H ; Store result into memory location 2002H
HLT ; Stop execution
5.3 Understanding the Need for Resident Software
In order to load and execute a program, the microprocessor system must already include basic
software routines stored in ROM (Read-Only Memory). These routines form the monitor
program, BIOS, or bootloader, depending on the complexity of the system.
Purposes of Existing Software
 Program loader: Loads user-defined code into memory.
 I/O routines: Handles input/output without needing to rewrite low-level code.
 Instruction interpreter: In higher-level processors, interprets instructions and handles
exceptions.
Without such resident software, the microprocessor would not know where to start executing
instructions or how to interact with memory and I/O.
5.4 Constructing Trace Tables for Program Execution
A trace table tracks the state of the processor and memory after the execution of each
instruction. It helps visualize how the algorithm operates on data.

Trace Table Example

Initial Conditions:
 Memory[2000H] = 05H

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  Memory[2001H] = 07H
 A = --
 PC = Starting Address

Step Instruction A B C M (HL) PC Memory[2002H]

1 LDA 2000H 05 1000 --

2 MOV H, 20H 05 1003 --

3 MOV L, 01H 05 07 1004 --

4 ADD M 0C 1005 --

5 MOV C, A 0C 0C 1006 --

6 STA 2002H 0C 0C 1007 0C

7 HLT 0C 0C 1008 0C

5.5 Verifying the Trace Table by Loading and Single-Stepping

Once a trace table is prepared, the program can be loaded into a simulator, emulator, or
development board.
Verification Steps:
1. Enter the machine code into memory starting at a defined address.
2. Set up initial memory values (2000H = 05H, 2001H = 07H).
3. Step through each instruction using single-step mode on a simulator.
4. Observe the contents of the accumulator, registers, and memory after each step.
5. Compare the observed results with the expected values in the trace table.
Tools Used:
 8085/8086 emulator software
 Microcontroller trainer kits
 Arduino/AVR emulators
 Proteus or Multisim simulations
5.6 Examining Bus Signals under Clock Control

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Microprocessors operate synchronously based on clock cycles. During instruction execution,
buses (address, data, and control) are activated in coordination with clock pulses.
Bus Signal Breakdown
 Address Bus: Carries address of memory or I/O location.
 Data Bus: Carries data to/from memory, I/O, or register.
 Control Bus: Sends signals like RD̅ , WR̅ , ALE, and IO/M̅ .
Execution Phase and Bus Activity

Clock Cycle Bus Signal Action

T1 Address Bus 2000H Address placed for LDA

T2 Control Bus RD̅ low, ALE high Enable read from memory

T3 Data Bus 05H Data read into accumulator

T4 Control Bus WR̅ low Write result to memory

Using Tools to Observe Signals

 CRO (Cathode Ray Oscilloscope): Observe pulse transitions and signal behavior.
 Logic Analyzer: Monitor multiple bus signals in real-time.
 Simulation Software: Provides graphical visualization of buses during program
execution.
Conclusion
This lecture emphasizes:
1. The importance of defining algorithms before coding. 2. Translating logical steps into
assembly language instructions.
[Link] execution through trace tables and simulation. [Link] how the
microprocessor uses bus signals and clock control to fetch, decode, and execute programs.

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