EXP1:full adder EXP2: 4 bit shift add
The test bench will apply different test cases and check `timescale 1ns / 1ps
the fu module tb_shift_add_multiplier;
`timescale 1ns / 1ps reg [3:0] A, B;
module tb_four_bit_adder; wire [7:0] P;
reg [3:0] A, B; shift_add_multiplier uut (
reg Cin; .A(A),
wire [3:0] Sum; .B(B),
wire Cout; .P(P)
four_bit_adder uut (A, B, Cin, Sum, Cout); );
initial begin initial begin
// Test Case 1: 0000 + 0000 // Test Case 1: 3 * 2
A = 4'b0000; B = 4'b0000; Cin = 0; #10; A = 4'b0011; B = 4'b0010; #10
$display("A=%b B=%b Cin=%b | Sum=%b Cout=%b", A, $display("A=%b B=%b | Product=%b", A, B, P);
B, Cin, Sum, Cout); // Test Case 2: 7 * 5
// Test Case 2: 0011 + 0101 A = 4'b0111; B = 4'b0101; #10;
A = 4'b0011; B = 4'b0101; Cin = 0; #10; $display("A=%b B=%b | Product=%b", A, B, P);
$display("A=%b B=%b Cin=%b | Sum=%b Cout=%b", A, // Test Case 3: 15 * 1
// Test Case 3: 1111 + 0001 A = 4'b1111; B = 4'b0001; #10;
A = 4'b1111; B = 4'b0001; Cin = 0; #10; $display("A=%b B=%b | Product=%b", A, B, P);
$display("A=%b B=%b Cin=%b | Sum=%b Cout=%b", A, // Test Case 4: 6 * 9
B, Cin, Sum, Cout); A = 4'b0110; B = 4'b1001; #10;
// Test Case 4: 1010 + 0101 $display("A=%b B=%b | Product=%b", A, B, P);
A = 4'b1010; B = 4'b0101; Ci // Test Case 5: 8 * 12
$display("A=%b B=%b Cin=%b | Sum=%b Cout=%b", A, A = 4'b1000; B = 4'b1100; #10;
B, Cin, Sum, Cout); $display("A=%b B=%b | Product=%b", A, B, P);
// Test Case 5: 1100 + 1011 with Carry $stop;
A = 4'b1100; B = 4'b1011; Cin = 1; #10; end
$display("A=%b B=%b Cin=%b | Sum=%b Cout=%b", A, endmodule
B, Cin, Sum
B, Cin, Sum, Cout);
Cin = 0; #10;
Carry-in
Sum, Cout);
$stop;
end
endmodule
EXP3: 32-BIT ALU
$display("A=%h B=%h ALU_Sel=%b |
`timescale 1ns / 1ps
ALU_Out=%h Zero=%b", A, B,
module tb_alu_32bit;
ALU_Sel,
reg [31:0] A, B;
ALU_Out, Zero);
reg [2:0] ALU_Sel;
// Test OR
wire [31:0] ALU_Out;
A = 32'h000000F0; B =
wire Zero;
32'h0000000F; ALU_Sel = 3'b101; #1
alu_32bit uut (
$display("A=%h B=%h ALU_Sel=%b |
.A(A),
ALU_Out=%h Zero=%b", A, B,
.B(B),
ALU_Sel,
.ALU_Sel(ALU_Sel),
ALU_Out, Zero);
.ALU_Out(ALU_Out),
// Test XOR
.Zero(Zero)
A = 32'hAAAAAAAA; B =
);
32'h55555555; ALU_Sel = 3'b110;
initial begin
#10;
// Test Addition
$display("A=%h B=%h ALU_Sel=%b |
A = 32'h00000005; B = 32'h00000003; ALU_Sel =
ALU_Out=%h Zero=%b", A, B, ALU_
3'b000; #10;
ALU_Out, Zero);
$display("A=%h B=%h ALU_Sel=%b |
// Test NOR
ALU_Out=%h Zero=%b", A, B, ALU_Sel,
A = 32'h00000000; B =
ALU_Out, Zero);
32'h00000000; ALU_Sel = 3'b111;
// Test Subtraction
#10;
A = 32'h00000008; B = 32'h0
$display("A=%h B=%h ALU_Sel=%b |
$display("A=%h B=%h ALU_Sel=%b |
ALU_Out=%h Zero=%b", A, B,
ALU_Out=%h Zero=%b", A, B, ALU_Sel,
ALU_Sel,
ALU_Out, Zero);
ALU_Out, Zero);
// Test Multiplication
$stop;
A = 32'h00000004; B = 32'h00000002; ALU_Sel =
end
3'b010; #10;
endmodule
$display("A=%h B=%h ALU_
ALU_Out, Zero);
// Test Division
A = 32'h00000010; B = 32'h00000002; ALU_Sel =
3'b011; #10;
$display("A=%h B=%h ALU_Sel=%b |
ALU_Out=%h Zero=%b", A, B, ALU_Sel,
ALU_Out, Zero);
// Test AND
A = 32'hFFFFFFFF; B = 32'h0000FFFF; ALU_Sel =
3'b100; #10;
Test Bench for D Flip-Flop Test Bench for SR Flip-Flop Test Bench for JK Flip-Flop
`timescale 1ns / 1ps `timescale 1ns / 1ps `timescale 1ns / 1ps
module tb_d_flip_flop; module tb_sr_flip_flop; module tb_jk_flip_flop;
reg D, clk, reset; reg S, R, clk; reg J, K, clk;
wire Q; wire Q; wire Q;
d_flip_flop uut ( sr_flip_flop uut ( jk_flip_flop uut (
.D(D), .S(S), .J(J),
.clk(clk), .R(R), .K(K),
.reset(reset), .clk(clk), .clk(clk),
.Q(Q) .Q(Q) .Q(Q)
); ); );
// Clock Generation always #5 clk = ~clk; always #5 clk = ~clk;
always #5 clk = ~clk; initial begin initial begin
initial begin clk = 0; S = 0; R = 0; #10; clk = 0; J = 0; K = 0; #10;
clk = 0; reset = 1; D = 0; #10; // Res S = 1; R = 0; #10; // Set Flip J = 1; K = 0; #10; // Set Flip
reset = 0; D = 1; #10; // Set D to 1 S = 0; R = 1; #10; // Reset Flip J = 0; K = 1; #10; // Reset Flip
D = 0; #10; // Change D to 0 S = 0; R = 0; #10; // Hold State J = 1; K = 1; #10; // Toggle State
D = 1; #10; // Change D to 1 S = 1; R = 1; #10; // Invalid State J = 0; K = 0; #10; // Hold State
$stop; $stop; J = 1; K = 1; #10; // Toggle again
end end $stop;
endmodule endmodule end
endmodule
Test Bench for MOD-N Counter
`timescale 1ns / 1ps
module tb_mod_n_counter;
reg clk, reset;
wire [3:0] count;
// Instantiate MOD-10 counter
(Change N as required)
mod_n_counter #(10) uut (
.clk(clk),
.reset(reset),
.count(count)
);
// Clock Generation
always #5 clk = ~clk; // 10ns period
initial begin
// Initialize
clk = 0; reset = 1; #10; // Apply Reset
reset = 0; #100; // Observe Counting
reset = 1; #10; // Apply Reset Again
reset = 0; #50; // Observe Counting
Again
$stop;
end
endmodule