Assignment 3
PH 207 Electronics
1) Design an ac ve band-pass filter using a single opera onal amplifier in an inver ng
configura on. The filter must sa sfy the following specifica ons:
The maximum passband gain should be −8.
The minimum input impedance at very high frequency should be 10 kΩ.
The filter should have:
o a first-order high-pass response with a 3 dB cutoff frequency of 1 kHz
o a first-order low-pass response with a 3 dB cutoff frequency of 10 kHz
The gain should remain approximately constant between 1 kHz and 10 kHz, with
a roll-off rate of 6 dB/octave below 1 kHz and above 10 kHz.
Inductors are not allowed.
To design the circuit:
a) First design a passive first-order RC high-pass filter with a 3 dB cutoff frequency of
1 kHz and an input impedance of 10 kΩ at infinite frequency. Assume a zero-
impedance source and an infinite-impedance load.
b) Next design a passive first-order RC low-pass filter with a 3 dB cutoff frequency of
10 kHz and an impedance of 10 kΩ at zero frequency, again assuming a zero-
impedance source and infinite load impedance.
c) Finally, incorporate these two passive filter sec ons into a single-op-amp
inver ng amplifier to realize the required ac ve band-pass filter with gain −8.
Determine the circuit topology and the required values of all resistors and capacitors.
2) Consider the three–opera onal amplifier differen al amplifier shown below. Using
the two fundamental rules of ideal opera onal amplifiers:
a) The input current to the op-amp terminals is zero.
b) The voltages at the inver ng and non-inver ng terminals are equal when
nega ve feedback is present.
Determine the rela onship between the output voltage 𝑣 and the two input voltages
𝑣 and 𝑣 .
You may assume all opera onal amplifiers are ideal.
3) Design a multi-stage OP-AMP network that realizes the expression
𝑑𝑥 (𝑡)
𝑦(𝑡) = 2𝑥 (𝑡) − 3𝑥 (𝑡) + 5 𝑥 (𝜏) 𝑑𝜏 − 0.1 + 7
𝑑𝑡
using only the standard building blocks in your notes. Power rails: ±12 V. Assume
ideal OP-AMPs first, then include finite-gain effects exactly as in the notes.
a) Draw the minimal cascade that implements the five terms. Label every stage
(type) and its function. (Use virtual-ground where applicable.)
b) Choose 𝑅and 𝐶so that each stage produces the required coefficients: +2, −3,
+5(integrator scale), −0.1(differentiator scale), and a constant +7via a
reference summed into the appropriate node. Show one line of math per stage
linking your selected values to each coefficient.
c) Add the stabilizing resistors exactly as recommended in the notes. Choose time
constants so the integrator’s 𝑅𝐶 is longer than the highest input period and the
differentiator does not amplify HF noise. State your corner frequencies.
d) With 𝐴 = 10 for all op-amps, compute the closed-loop gain error of each
amplifier stage using the finite-𝐴 expression from the notes, then tabulate the
percentage error of the total 𝑦(𝑡).
e) Let
𝑥 (𝑡) = 0.60sin (2000𝑡) V, 𝑥 (𝑡) = 1.20cos (2000𝑡) V, 𝑥 (𝑡) =
0.40 V (DC), 𝑥 (𝑡) = sin (1000𝑡) V.
Compute the ideal 𝑦(𝑡)(amplitudes, phases, DC) and check against rail limits
±12 V. Repeat once, including finite-𝐴 errors. State whether any stage
saturates.
4) A 4-arm 350 Ω bridge excited at 5 V produces a ±10 mV differential signal about
2.5 V common-mode. Disturbances: 50 Hz common-mode ±200 mV, 1 kHz
differential ±50 mV, and sensor DC offset ±1 mV. Design an OP-AMP chain that
outputs 0–2.0 V proportional to the sensor differential with: output CMRR ≥ 70 dB at
50 Hz, ≥ 20 dB attenuation at 1 kHz, passband ripple ≤ 0.5 dB from DC–20 Hz, and
total DC error ≤ 10 mV. Use only stages and methods from the notes.
a) Choose resistor ra os and show the equa on 𝑉 = 𝐴 (𝑉 − 𝑉 ) + 𝐴 (𝑉 + 𝑉 ).
For your component tolerances (1% and 0.1%), compute CMRR and the residual
50 Hz at the output. Explain how mismatch degrades CMRR.
b) Set the overall gain so ±10 mV → 2.0 V span with headroom (state the exact
numeric gain and one line proof). Select inver ng or non-inver ng topology and
jus fy impedance/noise implica ons using the notes.
c) Implement a first-order ac ve low-pass (integrator-style) with stabilized DC path
as in the notes. Pick 𝑅, 𝐶so that 0–20 Hz is flat (≤0.5 dB ripple), 50 Hz is
a enuated by ≥X dB (you choose X and defend it), and 1 kHz by ≥20 dB. Show
the three a enua on calcula ons.
d) Add a unity follower before the load; state in one line why it provides high input
𝑍and low output 𝑍.
e) Using defini ons of input offset voltage/current from the notes, es mate the
output offset from each stage for your chosen resistors and prove total DC error
≤ 10 mV.
5)
a) With 𝑉 = ±12 V, 𝑅 = 10 kΩ, 𝑅 = 40 kΩ, derive and numerically evaluate
the switching thresholds
𝑅 𝑅
𝑉 =+ 𝑉 ,𝑉 = − 𝑉
𝑅 +𝑅 𝑅 +𝑅
Then plot 𝑉 vs 𝑉 showing the hysteresis loop and annotate 𝑉 , 𝑉 . In 2–
3 lines, explain how regenerative feedback yields noise immunity.
b) Choose 𝑅 , 𝑅 so thresholds are ±4 V. With integrator 𝑅, 𝐶selected for ~100 Hz
operation, sketch two periods of:
(i) the integrator output 𝑣 (𝑡)(triangle) with slopes ±𝑉 /(𝑅𝐶)and crossing
times at ±4 V;
(ii) the Schmitt output (square). Label periods, amplitudes, and switching
instants clearly