Chapter 5: Synchronous Sequential Logic CSE-221: Digital Logic Design
1 Introduction to Sequential Circuits
1.1 Combinational vs Sequential Circuits
Exam Focus
Frequently Asked: Distinguish between combinational and sequential logic (2021,
2018, 2017)
Combinational Circuits:
• Output depends only on present inputs
• No memory elements
• No feedback paths
• Examples: Adders, Multiplexers, Decoders, Encoders
Sequential Circuits:
• Output depends on present inputs AND past history (state)
• Contains memory elements (flip-flops/latches)
• Has feedback paths from output to input
• Examples: Counters, Registers, State Machines
Comparison Table:
Feature Combinational Sequential
Memory No memory Has memory
Output Function of inputs only Function of inputs + state
Timing No timing/clock needed Requires timing/clock
Feedback No feedback Feedback present
Speed Generally faster Slower due to clock
Complexity Simpler More complex
1.2 Synchronous vs Asynchronous Sequential Circuits
Exam Focus
Asked in: 2021 - Distinguish between synchronous and asynchronous logic
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Chapter 5: Synchronous Sequential Logic CSE-221: Digital Logic Design
Synchronous Sequential Circuits:
• State changes occur at discrete time intervals
• Controlled by a clock signal
• All flip-flops change state simultaneously at clock edge
• More stable and easier to design
• No race conditions
• Examples: Synchronous counters, registers
Asynchronous Sequential Circuits:
• State changes occur immediately when inputs change
• No clock signal needed
• Faster response time
• Prone to timing problems and race conditions
• Harder to design and analyze
• Examples: Ripple counters, asynchronous latches
1.3 Block Diagram of Sequential Circuit
Inputs Outputs
Next State
Combinational Memory
Circuit Elements
Clock
Present State (Feedback)
Figure 1: Block diagram of a synchronous sequential circuit
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Chapter 5: Synchronous Sequential Logic CSE-221: Digital Logic Design
2 Storage Elements: Latches
2.1 Latch vs Flip-Flop
Exam Focus
Most Frequently Asked Theory Question!
Asked in: 2023, 2022, 2018, 2017, 2016
Key Differences:
Feature Latch Flip-Flop
Sensitivity Level-sensitive Edge-sensitive
Control Controlled by enable signal Controlled by clock edge
Timing Changes during HIGH/LOW Changes only at edge
level
Transparency Transparent when enabled Never transparent
Race Condition Prone to race conditions No race conditions
Speed Faster Slightly slower
Usage Asynchronous circuits Synchronous circuits
Examples SR latch, D latch D flip-flop, JK flip-flop
Latch (Level-Sensitive):
• Output can change whenever enable is HIGH (or LOW)
• “Transparent” - input directly affects output when enabled
• Used as building blocks for flip-flops
• Problem: Can lead to timing issues in sequential circuits
Flip-Flop (Edge-Sensitive):
• Output changes only at clock edge (rising or falling)
• Not transparent - input must be stable before clock edge
• Ideal for synchronous sequential circuits
• Has setup time and hold time requirements
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The Master-Slave Flip-Flop is basically
two gated flip-flops connected together in a series configuration with
the slave having an inverted "Slavepulse. The outputs from O and Q
from the flip-flop are fed back to the inputs of the "Master" with the
outputs of the "Master" flip flop being connected to the two inputs of
the "Slave" flip flop. This feedback configuration from the slave's
output to the master's input gives the characteristic toggle of the JK
flip flop as shown below.