May 16, 2026 [EE Lab II (ECEg2072) ]

DEBRETABOR UNIVERSITY
Gafat institute of Technology
ELECTRICAL ENGINEERING
LABORATORY II

ECEg2072 | Year II / Semester II | ECE Department

Complete Study Notes • All Viva Questions Answered • MCQ Practice

Experiments: PN Junction Diode |Zener Diode &

Regulator | LED | Half-Wave Rectifier | Full-Wave
Rectifier CB Config | CE Config | JFET Drain/Transfer |
CE Amplifier | CS FET Amplifier

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Experiment 1: V-I Characteristics of PN Junction Diode

1.1 Objectives
1. Plot Volt-Ampere Characteristics of Silicon P-N Junction Diode.
2. Find the cut-in voltage for the Silicon P-N Junction diode.
3. Find static resistance and dynamic resistance for P-N Junction diode.

1.2 Apparatus
[Link] Apparatus Type Range Qty
01 PN Junction Diode 1N4007 — 01
02 Resistance Carbon 470 Ω, 1 KΩ 01 each
03 Regulated Power Supply DC 0–30 V 01
04 Ammeter MC 0–100 mA, 0–100 μA 01 each
05 Voltmeter MC 0–2 V, 0–30 V 01 each
06 Breadboard and Wires — — As reqd

1.3 Theory
1.3.1 The P-N Junction
A semiconductor diode is formed by joining an N-type material (majority carrier: electrons) to a P-type
material (majority carrier: holes). At equilibrium a depletion region forms at the junction, creating a built-in
potential barrier (~0.7 V for Si, ~0.3 V for Ge).

1.3.2 Forward Bias

Positive supply to anode (P-side), negative to cathode (N-side). The potential barrier is LOWERED. Holes
from P and electrons from N cross the junction, constituting a forward current. Below the cut-in voltage
(~0.6–0.7 V for Si) the current is negligible; above it current rises exponentially. For analysis the forward-
biased diode may be approximated as a closed switch.

1.3.3 Reverse Bias

Positive supply to cathode (N-side), negative to anode (P-side). The potential barrier is RAISED; majority
carriers move away from the junction, widening the depletion region. Only thermally-generated minority
carriers produce a tiny reverse saturation current I₀. The diode approximates an open switch.

1.3.4 Shockley (Diode) Equation

I = I₀ (e^(V / ηVT) − 1)

Equation variables
I = diode current
I₀ = reverse saturation current
V = voltage across diode

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VT = kT/q = T/11 600 ≈ 26 mV at 300 K (thermal voltage)

η = 1 for Ge, η = 2 for Si (ideality factor)
For large forward bias: I ≈ I₀ · e^(V/ηVT)
For large reverse bias: I ≈ −I₀ (reverse saturation current)

1.3.5 Si vs Ge comparison

Silicon vs Germanium
Property | Silicon (Si) | Germanium (Ge)
Cut-in voltage | 0.6 – 0.7 V | 0.2 – 0.3 V
Reverse sat. curr. | nanoamperes | microamperes (larger)
Temp. tolerance | Higher (≤200°C)| Lower (≤75 °C)
Practical use | Very common | Specialised RF/detector

1.4 Circuit Connections (summary)

Forward Bias: Anode → +ve supply (through 470 Ω series resistor and mA ammeter) | Cathode → −ve supply
| Voltmeter (0–2 V) across diode.
Reverse Bias: Cathode → +ve supply (through 1 KΩ series resistor and μA ammeter) | Anode → −ve supply |
Voltmeter (0–30 V) across diode.

1.5 Procedure
Forward Bias
4. Connect circuit. Vary VS from 0 V in steps of 0.1 V.
5. Record VF (voltmeter across diode) and IF (ammeter).
6. Stop before exceeding max diode current (1 A for 1N4007).
7. Plot IF (Y-axis) vs VF (X-axis).

Reverse Bias
8. Reconnect for reverse bias. Vary VS from 0 V in steps of 1 V.
9. Record VR and IR (μA).
10. Plot IR (Y-axis, negative) vs VR (X-axis, negative).

1.6 Calculations from Graph

Static (DC) Resistance
Locate Q-point on forward characteristic. Drop perpendiculars to both axes to read VF and IF.
R_DC = VF / IF (Ohms) at the Q-point
Dynamic (AC) Resistance
Draw tangent at Q-point. Measure small increments ΔVd and ΔId along the tangent.
r_d = ΔVd / ΔId (Ohms) at Q-point

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Approximate formula (useful for quick estimate): r_d ≈ η·VT / I_DC →r_d ≈ 52 / IC(mA) Ω for Si at room
temp.

1.7 Precautions
11. Never exceed diode ratings (1N4007: IF(max)=1 A, PIV=1000 V, PD=3 W).
12. Connect ammeter and voltmeter with correct polarities.
13. Do NOT power the circuit until all connections are verified.
14. The 470 Ω/1 KΩ series resistor MUST be present to limit current.
15. Vary supply voltage slowly in the forward region near cut-in voltage.

1.8 Results (to be filled after experiment)

Cut-in voltage Vγ = _________ V
Static forward resistance R_DC = _________ Ω
Dynamic resistance r_d = _________ Ω

1.9 Viva Questions — Full Answers

Q: When does a diode act like an ideal switch?
A diode acts as an IDEAL CLOSED SWITCH (short circuit) when it is forward biased with voltage ≥ the
cut-in voltage (~0.7 V for Si). In this state, current flows freely. It acts as an IDEAL OPEN SWITCH
(open circuit) when reverse biased — no current flows (ignoring tiny I₀). In ideal-switch analysis the cut-in
voltage is assumed to be 0 V for simplicity, and the reverse blocking is assumed to be perfect. The 1N4007
has a maximum reverse voltage of 1000 V, so it behaves as a near-ideal open switch for most practical
reverse voltages.
Q: What is the cut-in voltage? Give typical values for Ge and Si.
The cut-in voltage (also called threshold voltage, knee voltage, or barrier voltage) is the minimum forward
bias at which the diode begins to conduct appreciable current. Below this voltage the exponential Shockley
equation gives negligible current; above it current rises steeply. Values: Silicon (Si) ≈ 0.6–0.7 V;
Germanium (Ge) ≈ 0.2–0.3 V. It corresponds approximately to the built-in potential of the junction. It
varies slightly with temperature — the cut-in voltage decreases by about 2 mV for every 1 °C rise in
temperature for Si.
Q: What is reverse saturation current?
The reverse saturation current I₀ is the small current that flows when a diode is reverse biased. It is caused
by thermally-generated electron-hole pairs in the depletion region and by minority carriers (electrons in P-
side, holes in N-side) that are swept across the junction by the built-in electric field. I₀ is essentially
independent of the reverse voltage magnitude (for voltages well below breakdown), but is VERY sensitive
to temperature — it roughly doubles for every 10 °C rise. For Si, I₀ is in the nanoampere range; for Ge, it is
in the microampere range. Because Ge has a smaller bandgap energy, more thermally-generated carriers
exist, so I₀(Ge) >> I₀(Si).
Q: What is dynamic resistance and static resistance?
STATIC (DC) RESISTANCE: R_DC = VF / IF at the Q-point. It is the simple ratio of DC operating
voltage to DC operating current. It is NOT related to the shape of the curve — just a ratio at one point. It
changes depending on where the Q-point is. DYNAMIC (AC) RESISTANCE: r_d = ΔVd / ΔId, found
from the slope of the tangent to the V-I curve at Q. It represents the opposition the diode presents to a small

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AC signal superimposed on the DC bias. It is more meaningful for circuit analysis because amplifiers and
AC circuits depend on how the device responds to signal changes, not just to DC. Approximate formula:
r_d = η·VT / I_Q ≈ 26/I_Q(mA) Ω for Ge, 52/I_Q(mA) Ω for Si.
Q: What is the V-I characteristics equation?
The V-I characteristic of a P-N junction diode is the Shockley equation: I = I₀(e^(V/ηVT) − 1). Here I₀ is
the reverse saturation current, V is the applied diode voltage (positive for forward, negative for reverse), η
is the ideality factor (1 for Ge, 2 for Si), and VT = kT/q is the thermal voltage (≈ 26 mV at 300 K). For
forward bias with V >> VT: I ≈ I₀ · e^(V/ηVT) — exponential increase. For reverse bias with |V| >> VT: I
≈ −I₀ — constant small current. The equation explains the asymmetric, non-linear current-voltage
relationship of the diode.
Q: Define potential barrier.
The potential barrier (built-in potential or contact potential V₀) is the electrostatic voltage difference that
develops spontaneously at a P-N junction in equilibrium — with no external bias applied. It forms because
electrons diffuse from N to P and holes from P to N, leaving behind fixed ionised donor (+) atoms on the
N-side and acceptor (−) atoms on the P-side. This creates a depletion region with an internal electric field
that opposes further diffusion, establishing equilibrium. Typical values: Si ≈ 0.6–0.8 V, Ge ≈ 0.2–0.4 V.
External forward bias reduces this barrier; reverse bias increases it.
Q: Define doping.
Doping is the controlled introduction of specific impurity atoms (dopants) into an intrinsic semiconductor
to modify its electrical conductivity. N-type doping: donor atoms (e.g., Phosphorus P, Arsenic As,
Antimony Sb in Si) each contribute one extra free electron, making electrons the majority carriers. P-type
doping: acceptor atoms (e.g., Boron B, Aluminium Al, Gallium Ga in Si) each accept one electron creating
a hole, making holes the majority carriers. The dopant concentration (atoms per cm³) determines
conductivity. Typical doping densities: 10¹⁴ to 10¹⁸ atoms/cm³ (compared to Si atom density ~5×10²²
atoms/cm³).
Q: What is the effect of temperature on I₀?
Temperature has a very strong effect on the reverse saturation current I₀. As temperature increases, more
covalent bonds break (higher thermal energy), producing more electron-hole pairs. These extra minority
carriers increase I₀. The empirical rule: I₀ approximately DOUBLES for every 10 °C rise in temperature
(valid for both Si and Ge). Mathematically: I₀(T₂) = I₀(T₁) × 2^((T₂−T₁)/10). This also means the forward
V-I characteristic shifts: for the same current the forward voltage decreases by ~2 mV/°C for Si. At high
temperatures, increased I₀ can cause thermal runaway in some circuits.
Q: Define a Q-point.
The Q-point (Quiescent Operating Point) is the DC operating point of a device — the pair of values (V_Q,
I_Q) at which the device is biased in the absence of any AC signal. On a V-I characteristic curve, the Q-
point is the intersection of the load line (determined by the supply voltage and series resistor) with the
device characteristic. The Q-point determines the static resistance, dynamic resistance, and the range over
which the device can amplify without distortion. For a diode, the Q-point is typically chosen in the forward
conduction region at a desired operating current.
Q: Explain how the diode can act as a capacitor.
A reverse-biased P-N junction acts as a voltage-controlled capacitor (varactor or varicap). The depletion
region — which is depleted of free carriers — acts as a dielectric insulator, while the P and N bulk
semiconductor regions on either side act as the two conducting 'plates'. As reverse voltage increases, the
depletion region widens → effective plate separation increases → capacitance DECREASES. Formula for

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transition (junction) capacitance: CT = K / (V₀ + VR)^n, where V₀ is built-in potential, VR is reverse

voltage, n ≈ 0.5 (abrupt junction) or 0.33 (graded junction). Varactorsare used in voltage-controlled
oscillators (VCOs), FM tuners, phase-locked loops (PLLs), and mobile phone RF circuits.

1.10 MCQ Practice — Experiment 1: PN Junction Diode

Answer all 15 questions. Check answers and read explanations carefully.
# Question & Options Answer Explanation

1 What is the approximate cut-in voltage C) 0.7 V Si has a cut-in voltage ≈ 0.6–0.7 V. Ge is 0.2–0.3 V.
of a Silicon PN junction diode? This arises from the bandgap energy of Si (1.12 eV)
A) 0.1 V which sets the built-in potential of the junction.
B) 0.3 V
C) 0.7 V
D) 1.1 V

2 In forward bias the potential barrier at C) Lowered Forward bias reduces the potential barrier by the
the PN junction is: applied voltage, allowing majority carriers to diffuse
A) Increased across. The barrier is lowered, not eliminated —
some barrier always remains in equilibrium.
B) Completely removed
C) Lowered
D) Unchanged

3 Which has a LARGER reverse B) Ge has a smaller bandgap (0.67 eV vs 1.12 eV for
saturation current? Germanium Si), so more electron-hole pairs are thermally
A) Silicon generated. I₀(Ge) is in μA; I₀(Si) is in nA — roughly
1000× difference.
B) Germanium
C) Both equal
D) Zener diode

4 In the Shockley equation I = C) 2 For Si, η = 2. For Ge, η = 1. The ideality factor
I₀(e^(V/ηVT)−1), the ideality factor η accounts for carrier recombination in the depletion
for Silicon is: region, which is more significant in Si than in Ge.
A) 0.5
B) 1
C) 2
D) 4

5 The thermal voltage VT at room C) 26 mV VT = kT/q = T/11 600 = 300/11 600 ≈ 26 mV at 300
temperature (300 K) is approximately: K. It appears in the diode equation and sets the
A) 0.7 V 'sharpness' of the turn-on characteristic.
B) 260 mV
C) 26 mV
D) 2.6 mV

6 As reverse voltage increases, the C) Widens Reverse bias sweeps majority carriers away from the
depletion region: junction, exposing more fixed ions and widening the
A) Narrows depletion region. A wider depletion region = higher
potential barrier = better blocking.
B) Stays the same
C) Widens
D) Disappears

7 Static (DC) forward resistance at the B) R_DC = Static resistance is the simple DC ratio at the
Q-point is: VF / IF operating point: R_DC = VF/IF. Dynamic resistance
A) R_DC = IF / VF (rd = ΔVF/ΔIF) is the slope of the curve. They are
different quantities.

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B) R_DC = VF / IF
C) R_DC = ΔVF / ΔIF
D) R_DC = 1/gm

8 Why is the 470 Ω series resistor used in B) To limit Without the 470 Ω resistor, the diode current would
the forward bias circuit? current be limited only by the very low forward resistance of
A) To increase diode voltage through the the conducting diode, potentially exceeding its rating
diode and destroying it. The series resistor limits I to a safe
B) To limit current through the diode
value.
C) To improve ammeter sensitivity
D) To block reverse current

9 The reverse saturation current I₀ with C) Doubles I₀ approximately doubles for every 10 °C rise,
rising temperature: every ~10 because thermal energy breaks more covalent bonds,
A) Decreases °C generating more minority carriers. This is a critical
consideration in high-temperature electronics.
B) Stays constant
C) Doubles every ~10 °C
D) Halves every ~10 °C

10 Dynamic resistance r_d at Q-point is B) The slope r_d = ΔVd/ΔId is found from the slope of the tangent
found from: of the to the V-I curve at the Q-point. It represents the
A) A single point (VF, IF) tangent at Q incremental resistance seen by a small AC signal and
is used in small-signal equivalent circuit analysis.
B) The slope of the tangent at Q
C) The ratio VF/IF
D) The x-axis intercept

11 The approximate dynamic resistance B) r_d = r_d = η·VT/ID = 2×26mV/ID = 52mV/ID(mA) Ω for
formula for Si at room temperature is: 52/ID(mA) Si (η=2). For Ge (η=1): r_d = 26/ID(mA). So at 10
A) r_d = 26/ID(mA) mA Si bias: r_d = 52/10 = 5.2 Ω.
B) r_d = 52/ID(mA)
C) r_d = 0.7/ID(mA)
D) r_d = 100/ID(mA)

12 Which 1N4007 diode parameter C) PIV PIV (also PRV — Peak Reverse Voltage) specifies
determines maximum safe reverse (Peak the maximum reverse voltage the diode can
voltage? Inverse withstand without breakdown. 1N4007 PIV = 1000
Voltage) V. Exceeding this causes avalanche breakdown and
A) IF(max)
possible destruction.
B) PD(max)
C) PIV (Peak Inverse Voltage)
D) Cut-in voltage

13 A diode acting as a capacitor uses the C) The depletion region is depleted of free carriers and
_______ region as the dielectric. Depletion acts as an insulating dielectric between the
A) P-type bulk region region conducting P and N bulk regions (which act as
capacitor plates). Wider depletion (more reverse
B) N-type bulk region
bias) = lower capacitance.
C) Depletion region
D) Metallurgical junction

14 Cut-in voltage of a Si diode changes C) −2 The forward voltage of a Si diode decreases by

with temperature at approximately: mV/°C approximately 2 mV for every 1 °C increase in
A) +2 mV/°C temperature (negative temperature coefficient). This
is because I₀ increases with temperature, so less
B) −0.2 mV/°C
forward voltage is needed to achieve the same
C) −2 mV/°C current.
D) Unchanged

15 On the V-I graph, the Q-point is the B) The load The Q-point is determined by the intersection of the
intersection of the device characteristic line device's V-I characteristic curve with the LOAD

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with: LINE. The load line is drawn from (VS/R_series, 0)

A) The origin (0,0) on the current axis to (VS, 0) on the voltage axis,
representing all possible combinations of voltage and
B) The load line
current given the supply and series resistance.
C) The breakdown voltage line
D) The x-axis

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Experiment 2: V-I Characteristics of Zener Diode & Voltage

Regulator
2.1 Objectives
16. Plot Volt-Ampere Characteristics of Zener Diode in reverse bias.
17. Find Zener Breakdown Voltage in reverse biased condition.
18. Plot load regulation characteristics of Zener voltage regulator.

2.2 Apparatus
[Link] Apparatus Type Range Qty
01 Zener Diode IMZ 5.1 V — 01
02 Resistance Carbon 470 Ω 01
03 Regulated Power Supply DC 0–30 V 01
04 Ammeter MC 0–100 mA 02
05 Voltmeter MC 0–10 V 01
06 Decade Resistance Box DRB 0–10 KΩ 01
07 Breadboard and Wires — — As reqd

2.3 Theory
2.3.1 Zener Diode
A Zener diode is a heavily-doped P-N junction diode designed to operate reliably in the reverse breakdown
region. Forward biased, it behaves like an ordinary diode. Reverse biased, it blocks until the reverse voltage
reaches VZ (Zener voltage), at which point it conducts heavily while maintaining an approximately
CONSTANT voltage VZ. This property is exploited for voltage regulation.

2.3.2 Avalanche Breakdown

Occurs in LIGHTLY doped junctions at higher reverse voltages (VZ > ~6 V for Si). The electric field across
the wide depletion region accelerates thermally-generated carriers to high velocities. These energetic carriers
collide with lattice atoms, breaking covalent bonds and generating additional electron-hole pairs (impact
ionisation). Those new carriers also accelerate and generate yet more pairs — an avalanche multiplication
chain reaction. Temperature coefficient: POSITIVE (VZ increases with temperature, because higher
temperature increases lattice vibrations, reducing carrier mean free path and requiring higher fields to achieve
avalanche).

2.3.3 Zener Breakdown

Occurs in HEAVILY doped junctions at lower voltages (VZ < ~6 V for Si). The heavy doping creates a very
narrow depletion region. Even a small reverse voltage produces an intense electric field (~10⁷ V/m) across the
narrow region. This field is strong enough to pull valence electrons directly out of their covalent bonds
through quantum-mechanical tunnelling — no high-energy collision needed. This is the true Zener effect.
Temperature coefficient: NEGATIVE (VZ decreases with temperature, because higher temperature increases
carrier energy, making tunnelling easier at lower voltages).
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Zener vs Avalanche — Key Comparison

Mechanism | Zener: tunnelling | Avalanche: impact ionisation
Doping | Zener: heavy doping| Avalanche: light doping
Voltage | Zener: VZ < 6 V | Avalanche: VZ > 6 V
Temp Coeff | Zener: negative | Avalanche: positive
Breakdown | Zener: gradual/soft| Avalanche: sharp/abrupt
Note: At ~6V for Si both mechanisms coexist and temperature coefficients nearly cancel — excellent temp
stability.

2.3.4 Zener Voltage Regulator (Shunt Regulator)

Circuit: series resistor RS = 470 Ω between input and output node; Zener diode (reverse biased: cathode to +,
anode to −) in parallel with load RL.
Operation — Input voltage variation: If Vin rises, more current flows through RS and Zener (IZ increases).
The extra voltage appears across RS. VL = VZ remains constant.
Operation — Load variation: If RL decreases (load current IL rises), Zener current IZ decreases by the same
amount to keep total I = (VS − VZ)/RS constant. VL = VZ remains constant.
% Regulation = [(VNL − VFL) / VFL] × 100%
VNL = no-load output voltage; VFL = full-load output voltage. Ideal regulator: 0%.

2.4 Procedure
V-I Characteristics (Reverse Bias)
19. Connect Zener in reverse bias (anode to −ve, cathode to +ve through 470 Ω and ammeter).
20. Vary supply in steps of 1 V; record VR and IR at each step.
21. Observe sharp increase in IR at breakdown — that voltage is VZ.
22. Plot IR (downward, −ve direction) vs VR (leftward, −ve direction).

Load Regulation
23. Set input to a voltage above VZ (confirmed from Step 1).
24. Open RL; measure VNL.
25. Connect DRB; vary RL from 1100 Ω to 100 Ω (steps of 100 Ω). Record IZ and VL.
26. Calculate % Regulation = [(VNL−VL)/VL]×100% for each RL.

2.5 Precautions
27. Never exceed power rating of Zener (PZ = VZ × IZ(max)). For IMZ 5.1V check datasheet.
28. Keep input voltage above VZ to ensure regulation; avoid excessive input that may overdrive.
29. Series resistor RS = 470 Ω MUST be present — it limits current through the Zener.
30. Electrolytic capacitors (if used) must be connected with correct polarity.

2.6 Viva Questions — Full Answers

Q: What is the difference between Zener and Avalanche breakdown?
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ZENER BREAKDOWN: Occurs in heavily doped junctions (narrow depletion region). Mechanism:
quantum-mechanical band-to-band tunnelling of electrons directly through the narrow energy barrier under
intense electric field. Occurs at VZ < ~6 V for Si. Has NEGATIVE temperature coefficient: as temperature
rises, VZ decreases (higher carrier energy makes tunnelling easier). Breakdown is relatively gradual (soft).
AVALANCHE BREAKDOWN: Occurs in lightly doped junctions (wide depletion region). Mechanism:
impact ionisation — thermally-generated carriers are accelerated by the field to high energies, collide with
lattice atoms, break covalent bonds, generating new carriers, which generate more, etc. (chain reaction).
Occurs at VZ > ~6 V for Si. Has POSITIVE temperature coefficient: as temperature rises, VZ increases
(more lattice collisions reduce carrier mean free path, requiring higher field for ionisation). Breakdown is
abrupt. At VZ ≈ 6 V for Si, both mechanisms coexist and their temperature coefficients cancel — excellent
temperature stability near 6 V.
Q: What is the difference between a Zener diode and an ordinary diode?
ORDINARY P-N JUNCTION DIODE: • Designed for forward bias operation only. • Reverse breakdown
is a destructive failure mode — the high reverse current can destroy the device. • No useful operation in
reverse breakdown region. • Forward voltage drop ≈ 0.6–0.7 V (Si). ZENER DIODE: • Designed to
operate in the REVERSE BREAKDOWN region. • Heavily doped to achieve a precise, well-defined
breakdown voltage VZ. • Breakdown is non-destructive as long as power dissipation (VZ × IZ) stays
within rated PD. • Maintains nearly constant VZ across terminals over a wide range of reverse currents —
used as voltage reference and regulator. • Forward operation: same as ordinary diode (cut-in ≈ 0.7 V for Si
Zener). • Zener diodes are specified by VZ, IZ(max), PD(max), temperature coefficient (TC), and Zener
impedance ZZ.
Q: Draw the equivalent circuit for a Zener diode.
In the breakdown region, the ideal Zener diode is modelled as a battery of voltage VZ in series with a small
resistance ZZ (Zener impedance): Anode ──[ZZ]──[Battery VZ]── Cathode The battery models the
nearly-constant voltage VZ. ZZ (typically a few ohms) models the slight slope in the breakdown V-I curve
(small increase in VZ with increasing IZ). For an ideal Zener: ZZ = 0 and VZ is perfectly constant. For a
practical Zener the slope in the breakdown region means ZZ = ΔVZR / ΔIZR where ΔVZR and ΔIZR are
small changes about the operating point. In forward bias, the equivalent circuit is the same as an ordinary
diode: a 0.7 V battery in series with small forward resistance rf.
Q: What is the Breakdown Voltage?
The breakdown voltage (VZ or VBR) is the specific reverse voltage at which a Zener diode transitions
from blocking to conducting, with a sharp increase in reverse current while the voltage remains
approximately constant. For the IMZ 5.1V used in this experiment, VZ ≈ 5.1 V. At and above VZ, small
increases in reverse voltage produce large increases in reverse current — the Zener 'clamps' the voltage at
VZ. The exact value of VZ is set during manufacture by controlling the doping concentration. Zener
voltages range from ~1.8 V to several hundred volts. The device is safe as long as IZ stays below IZ(max)
= PD / VZ.
Q: What are the applications of a Zener diode?
1. VOLTAGE REGULATOR (primary application): Maintains constant DC output voltage despite input or
load variations. 2. VOLTAGE REFERENCE: Provides a stable, precise voltage reference in ADCs, DACs,
and measurement instruments. 3. OVERVOLTAGE PROTECTION: Placed across sensitive components
to clamp voltage at VZ during transients and surges. 4. WAVEFORM CLIPPER/LIMITER: Two back-to-
back Zeners clip a signal at ±(VZ + 0.7) V — used in limiters and waveshaping circuits. 5. METER
PROTECTION: Protects delicate galvanometers and sensors from voltage surges. 6. LEVEL SHIFTER:
Shifts DC level of a signal by VZ. 7. SWITCHING REGULATOR: Provides reference voltage in switch-

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mode power supplies. 8. SIGNAL CLAMPING in communication circuits to prevent overloading

amplifiers.
Q: How does a Zener diode act as a voltage regulator?
The Zener shunt regulator circuit consists of a series resistor RS and the Zener diode (reverse biased) in
parallel with the load RL. Voltage regulation against INPUT changes: If Vin increases → total current I =
(Vin − VZ)/RS increases → extra current flows through Zener (IZ increases) → extra voltage drops across
RS → VL = VZ remains unchanged. If Vin decreases → IZ decreases → less voltage drops across RS →
VL = VZ still maintained. Voltage regulation against LOAD changes: If RL decreases → IL = VZ/RL
increases → since I = IZ + IL is approximately fixed (Vin and RS are fixed), IZ automatically decreases to
compensate → VL = VZ stays constant. Condition for regulation: The Zener must remain in breakdown at
all times: IZ must be >IZ(min). The regulator fails if RL becomes so small that all of I is needed for IL
with nothing left for IZ. The range of valid RL is determined by this condition.

2.7 MCQ Practice — Experiment 2: Zener Diode

# Question & Options Answer Explanation

1 A Zener diode is specifically C) Reverse breakdown Unlike ordinary diodes, Zener diodes are
designed to operate in: region manufactured to operate in the reverse
A) Forward active region breakdown region, maintaining a nearly
constant voltage VZ. This is non-destructive
B) Forward bias only
if the power rating (VZ × IZ) is not
C) Reverse breakdown region exceeded.
D) Cut-off region

2 Zener breakdown occurs in C) Heavily Heavy doping creates a very narrow

_______ doped junctions. depletion region. Even a small reverse
A) Lightly voltage produces an intense electric field
sufficient for quantum-mechanical tunnelling
B) Moderately
(Zener mechanism). Lightly doped junctions
C) Heavily undergo avalanche breakdown instead.
D) Undoped

3 The temperature coefficient of C) Negative Zener breakdown has a NEGATIVE

Zener breakdown is: temperature coefficient: VZ decreases as
A) Positive temperature increases, because higher carrier
energy makes tunnelling easier at lower
B) Zero
voltages. Avalanche breakdown (VZ > 6 V)
C) Negative has a positive TC. At ~6 V the two
D) Depends on frequency mechanisms coexist and the net TC ≈ 0.

4 In a Zener shunt regulator the B) Reverse bias, The Zener is reverse biased (cathode to +ve)
Zener diode is connected in: parallel with load and connected in parallel (shunt) with the
A) Forward bias, series with load load RL. This ensures VL = VZ (the Zener
clamps the output voltage). A series resistor
B) Reverse bias, parallel with load
RS absorbs input voltage variations.
C) Forward bias, parallel with load
D) Reverse bias, series with load

5 The % voltage regulation formula C) % Regulation = [(VNL − VFL)/VFL] ×

is: [(VNL−VFL)/VFL]×100 100%. VNL = no-load output voltage, VFL =
A) [(VNL+VFL)/VFL]×100 full-load voltage. Lower % = better
regulation. An ideal regulator has 0% (VNL
B) [(VNL−VFL)/VNL]×100
= VFL — output is unchanged by load).
C) [(VNL−VFL)/VFL]×100
D) [VFL/VNL]×100

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6 The IMZ 5.1V Zener diode has a B) 5.1 V The part number 'IMZ 5.1V' directly states
nominal breakdown voltage of: the Zener voltage VZ = 5.1 V. The Zener
A) 3.3 V maintains approximately 5.1 V across itself
when reverse voltage reaches this value,
B) 5.1 V
regardless of the current (within limits).
C) 6.2 V
D) 12 V

7 If load resistance RL decreases in a C) Decreases to Total current I = (VS − VZ)/RS is

Zener regulator, the Zener current maintain constant total approximately constant. If RL decreases, IL
IZ: current = VZ/RL increases. Since I = IZ + IL, IZ
must decrease by the same amount to keep I
A) Increases
constant. This self-regulation keeps VL =
B) Stays the same
VZ.
C) Decreases to maintain constant total
current
D) Becomes zero

8 At a Zener voltage of C) Near zero (both At ~6 V for Si both Zener (tunnelling, −ve
approximately 6 V for Si, the mechanisms coexist) TC) and Avalanche (impact ionisation, +ve
temperature coefficient is: TC) mechanisms coexist simultaneously.
Their temperature coefficients nearly cancel,
A) Strongly positive
producing near-zero overall TC — excellent
B) Strongly negative
temperature stability, ideal for precision
C) Near zero (both mechanisms coexist) voltage references.
D) Infinite

9 The function of the series resistor B) To limit current and RS limits the current through the Zener diode
RS in a Zener regulator is: drop the excess voltage (preventing thermal destruction) and absorbs
A) To increase Zener current the voltage difference between Vin and VZ.
Without RS, the Zenerwould be directly
B) To limit current and drop the excess
connected to the supply and could easily be
voltage
destroyed by excessive current.
C) To filter ripple
D) To set Zener breakdown voltage

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Experiment 3: V-I Characteristics of Light Emitting Diode

(LED)
3.1 Objectives
31. Obtain the V-I Characteristics of LED.
32. Understand forward voltage and current relationship of an LED.

3.2 Apparatus
[Link] Apparatus Type Range Qty
01 LED Standard — 01
02 Resistance Carbon 470 Ω 01
03 Regulated Power Supply DC 0–30 V 01
04 Ammeter MC 0–100 mA 01
05 Voltmeter MC 0–10 V 01
06 Breadboard and Wires — — As reqd

3.3 Theory
3.3.1 Structure and Materials
An LED is a P-N junction diode made from compound III-V semiconductors (elements from groups III and V
of the periodic table) that have DIRECT energy bandgaps. Direct bandgap materials allow efficient radiative
recombination (photon emission). Examples:
• GaAs (Gallium Arsenide): infrared, ~880 nm
• GaAsP (Gallium Arsenide Phosphide): red/yellow, ~620–590 nm
• GaP (Gallium Phosphide): green/red, ~560 nm
• GaN (Gallium Nitride): blue/UV, ~470 nm
• InGaN (Indium Gallium Nitride): green, blue, white, ~520–450 nm
Silicon and Germanium have INDIRECT bandgaps — recombination energy is released as heat (phonons),
not light. Hence Si/Ge cannot be used for LEDs.

3.3.2 Working Principle — Forward Bias

When forward biased: the reduced potential barrier allows electrons from the N-side and holes from the P-
side to diffuse across the junction. Near the junction, electrons and holes RECOMBINE. In direct-bandgap
materials, the recombination releases energy as a photon whose energy E = Eg (the bandgap energy). Since E
= hf = hc/λ, the wavelength λ = hc/Eg determines the colour of the emitted light.
Under REVERSE BIAS: carriers move away from the junction; no recombination → no light emission.

LED Forward Voltages by Colour

Colour | Material | Typical Vforward | Wavelength

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Infrared | GaAs | 1.2 – 1.6 V | > 750 nm

Red | GaAsP | 1.8 – 2.2 V | 620 – 750 nm
Yellow | GaAsP | 2.0 – 2.2 V | 570 – 620 nm
Green | GaP/InGaN | 2.0 – 3.0 V | 520 – 565 nm
Blue | GaN/InGaN | 2.8 – 3.5 V | 450 – 495 nm
White | InGaN+phos| 3.0 – 3.5 V | broad spectrum

3.3.3 Why LED Forward Voltage > Si Diode

For a photon to be emitted its energy must equal at least the bandgap energy: E_photon = Eg. Since E = q ×
Vforward, a higher bandgap → higher forward voltage. Si (Eg=1.12 eV, indirect) needs only ~0.7 V for
current flow, but emits no light. A red LED (Eg≈1.9 eV) needs ~1.9 V. A blue LED (Eg≈3.0 eV) needs ~3.0
V.

3.4 Procedure
33. Identify LED anode (longer lead) and cathode (shorter lead / flat side).
34. Connect anode to +ve supply through 470 Ω and ammeter; cathode to −ve supply. Voltmeter across
LED.
35. Increase supply voltage in 0.1 V steps from 0 V; record VLED and ILED.
36. Note the voltage at which LED starts to visibly glow — this is approximately Vγ.
37. Stop at rated maximum current (typically 20 mA for standard LEDs).
38. Plot ILED (Y) vs VLED (X). The curve is similar to a PN junction but shifted to higher Vγ.
39. Do NOT test in reverse bias — LEDs have very low PIV rating (~5 V typically).

3.5 Precautions
40. Never exceed maximum forward current (check datasheet; typically 20–30 mA).
41. Never apply reverse voltage exceeding LED's PIV rating (~5 V) — LEDs have very low reverse
breakdown voltage.
42. The 470 Ω series resistor is MANDATORY — without it the LED will burn out immediately.
43. Identify anode and cathode correctly before connecting.

3.6 Viva Questions — Full Answers

Q: What is an LED and how does it emit light?
An LED (Light Emitting Diode) is a P-N junction diode made from a DIRECT BANDGAP compound
semiconductor (GaAs, GaN, InGaN, GaAsP etc.) that converts electrical energy directly into light
(photons) when forward biased. Working principle — ELECTROLUMINESCENCE: When forward
biased, the potential barrier is reduced. Electrons from N-side and holes from P-side diffuse across the
junction and RECOMBINE at or near the junction. In direct bandgap materials, this electron-hole
recombination releases a quantum of light (photon) whose energy equals the bandgap energy: E_photon =
Eg = hf = hc/λ. The wavelength λ = hc/Eg determines the colour. Higher bandgap → shorter wavelength →
blue end. Lower bandgap → longer wavelength → red/infrared end.
Q: Why does an LED emit light only in forward bias?

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Light emission requires ELECTRON-HOLE RECOMBINATION at the junction. This only happens in
forward bias because: • In FORWARD BIAS: the potential barrier is reduced, allowing majority electrons
from N-side and majority holes from P-side to diffuse across the junction and meet — recombination
occurs — photon emitted. • In REVERSE BIAS: the potential barrier increases and majority carriers are
swept AWAY from the junction. There is no recombination near the junction, hence no photon emission.
Only a tiny reverse saturation current (due to minority carriers) flows — insufficient for observable light.
Q: Why is the cut-in voltage of an LED higher than that of a Si diode?
The cut-in voltage of an LED ≈ Eg/q (bandgap energy divided by electron charge). A photon of visible
light has energy 1.8–3.5 eV depending on colour. To produce that photon, the electron transitioning from
conduction band to valence band must release that much energy — which requires the forward voltage to
provide at least that energy. Si has Eg ≈ 1.12 eV but only needs ~0.7 V to conduct (the forward voltage is
lower than Eg because of the equilibrium built-in potential). Si is also indirect-bandgap so recombination
releases heat, not light. A red LED (GaAsP, Eg ≈ 1.9 eV) needs Vγ ≈ 1.8–2.2 V; a blue LED (GaN, Eg ≈
3.0 eV) needs Vγ ≈ 3.0–3.5 V. The higher the photon energy (shorter wavelength), the higher the required
forward voltage.
Q: What materials are used for different coloured LEDs?
Red/Infrared: GaAs (IR ~880 nm), GaAsP (~660 nm red). Yellow: GaAsP (~590 nm). Green: GaP (~565
nm), InGaN (~520 nm). Blue: GaN (~470 nm), InGaN (~460 nm). UV: GaN/AlGaN (~380 nm and below).
White: InGaN blue LED + yellow phosphor (YAG phosphor converts some blue to yellow; mix appears
white) — most common white LED structure. The compound composition (especially the alloy fraction,
e.g., GaAs₁₋ₓPₓ) fine-tunes the bandgap and hence the emission wavelength.
Q: What is electroluminescence?
Electroluminescence (EL) is the phenomenon in which a material emits light in response to an electric
current or electric field applied to it — without significant heat generation (unlike incandescence). In a
semiconductor LED, electroluminescence occurs at the P-N junction when electrons and holes are injected
(via forward bias) and recombine, releasing photons. This is specifically called INJECTION
ELECTROLUMINESCENCE. The process is highly efficient in direct bandgap semiconductors. Other
forms of EL exist (e.g., powder EL, thin-film EL used in displays), but LEDs are the most practical
implementation.

3.7 MCQ Practice — Experiment 3: LED

# Question & Options Answer Explanation

1 What type of semiconductor C) III-V compound LEDs need DIRECT BANDGAP materials for
material is used to make LEDs? semiconductors efficient photon emission. III-V compound
A) Silicon (Si) semiconductors (GaAs, GaN, InGaN, GaAsP)
have direct bandgaps. Si and Ge have indirect
B) Germanium (Ge)
bandgaps — recombination energy is released
C) III-V compound semiconductors as heat, not light.
(GaAs, GaN etc.)
D) Carbon

2 The colour of LED light is C) Bandgap energy λ = hc/Eg. Higher bandgap (e.g., GaN Eg≈3.0
determined by: of the eV) → shorter wavelength → blue. Lower
A) Forward current magnitude semiconductor bandgap (e.g., GaAs Eg≈1.42 eV) → longer
material wavelength → infrared. The bandgap is fixed by
B) Supply voltage
the material/alloy composition.
C) Bandgap energy of the
semiconductor material

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D) Size of LED

3 Typical forward voltage of a red C) 1.8–2.2 V Red LEDs (GaAsP, Eg≈1.8–2.1 eV) have
LED is approximately: forward voltage ≈ 1.8–2.2 V. Blue LEDs (GaN)
A) 0.3 V need ≈ 3.0–3.5 V. All LEDs require higher
forward voltage than Si diodes (0.7 V) because
B) 0.7 V
they must supply enough energy to produce
C) 1.8–2.2 V photons.
D) 5.0 V

4 Under reverse bias, an LED: C) Does not emit Reverse bias moves majority carriers away from
A) Emits brighter light any light junction → no recombination → no photon
emission. Additionally, LEDs have very low
B) Emits infrared
reverse breakdown voltage (~5 V), so excessive
C) Does not emit any light
reverse bias can damage the LED.
D) Acts as a Zener diode

5 The phenomenon by which an LED B) Electroluminescence is light emission from a

emits light is: Electroluminescence material under electric current/field. In LEDs it
A) Photoconductivity is specifically injection electroluminescence —
carriers are injected via forward bias and
B) Electroluminescence
recombine radiatively at the junction, emitting
C) Photovoltaic effect photons.
D) Photoelectric effect

6 Why can Silicon NOT be used to B) Silicon has an In indirect bandgap materials (Si, Ge), the
make LEDs? indirect bandgap — conduction band minimum and valence band
A) Silicon bandgap is too large recombination maximum occur at different crystal momenta.
releases heat not Electron-hole recombination must involve a
B) Silicon has an indirect bandgap —
light phonon (lattice vibration) to conserve
recombination releases heat not light
momentum. This makes radiative recombination
C) Silicon is too expensive very unlikely — energy is mostly released as
D) Silicon cannot be doped heat. Direct bandgap materials (GaAs, GaN)
allow direct radiative recombination.

7 Which LED colour requires the D) Blue/Violet Higher energy photons (shorter wavelength)
HIGHEST forward voltage? require higher bandgap materials → higher
A) Infrared forward voltage. Blue (GaN, Eg≈3.0 eV) needs
~3.0–3.5 V. Red (GaAsP, Eg≈1.9 eV) needs
B) Red
~1.8–2.2 V. Infrared (GaAs) needs ~1.2 V.
C) Green
D) Blue/Violet

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Experiment 4: Half-Wave Rectifier with and without Filter

4.1 Objectives
44. Plot input and output waveforms of Half-Wave Rectifier with and without Filter.
45. Find ripple factor of Half-Wave Rectifier with and without Filter.
46. Find percentage regulation of Half-Wave Rectifier.

4.2 Apparatus
[Link] Apparatus Type Range Qty
01 Step-Down Transformer Single Phase 230 V/12 V, 50 Hz 01
02 Diode 1N4007 PIV=1000 V, IF=1 A 01
03 Decade Resistance Box DRB 10–1000 Ω 01
04 Electrolytic Capacitor Filter 1000 μF/25 V 01
05 Digital Multimeter (DMM) AC/DC 0–20 V 01
06 CRO with Probes Dual Trace — 01
07 Breadboard and Wires — — As reqd

4.3 Theory
4.3.1 Rectifier — Definition
A rectifier converts AC (alternating current) into pulsating DC (unidirectional current). It exploits the one-
directional conductivity of a diode. A half-wave rectifier uses ONE diode and passes only ONE half (either
positive or negative) of the AC cycle to the load.

4.3.2 Half-Wave Rectifier Operation

POSITIVE HALF CYCLE: Diode is forward biased (anode +ve) → conducts → output ≈ input (minus ~0.7
V diode drop).
NEGATIVE HALF CYCLE: Diode is reverse biased → does NOT conduct → output = 0 V.
Result: Output is a series of positive half-sine pulses — pulsating DC at the same frequency as the input.

4.3.3 Key Parameters — Without Filter

Half-Wave Rectifier Formulas (No Filter)

Vdc (average output) = Vm / π ≈ 0.318 Vm
Vrms (output RMS) = Vm / 2 = 0.500 Vm
Ripple Factor γ = √[(Vrms/Vdc)² − 1] = √[(π/2)² − 1] ≈ 1.21
Efficiency η = 40.6%
PIV of diode = Vm (peak input voltage)
Output frequency = fin (same as input, 50 Hz for 50 Hz supply)

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4.3.4 Capacitor Filter — Working

A large capacitor (1000 μF) is connected in parallel with RL. During the peak of each positive half cycle, the
capacitor charges quickly to Vm. After the peak, the diode becomes reverse biased (input falls below
capacitor voltage). The capacitor then slowly DISCHARGES through RL, maintaining output voltage. At the
next peak the capacitor recharges. The small voltage variation between peak and trough is the RIPPLE
VOLTAGE Vr.
Ripple Factor (with capacitor filter) = 1 / (2√3 · f · C · RL)
Where f = 50 Hz, C = 1000 μF, RL = load resistance. Larger C or RL → smaller ripple → better filtering.

4.3.5 Percentage Voltage Regulation

% Regulation = [(VNL − VFL) / VFL] × 100%

4.4 Procedure
Without Filter
47. Connect HWR circuit (no capacitor). Note VNL before connecting load.
48. Vary RL from 1100 Ω to 100 Ω (steps of 100 Ω). Record VL and calculate % Regulation.
49. Measure Vac and Vdc at output using DMM; compute γ = Vac/Vdc.
50. Observe output on CRO; sketch waveform and note Vm and T.

With Filter
51. Add 1000 μF/25 V capacitor in parallel with RL. Ensure correct polarity (+ve to +ve node).
52. Measure Vac and Vdc at output. Compute γ = Vac/Vdc.
53. Observe waveform on CRO; compare with unfiltered output.

4.5 Precautions
54. Identify primary (230 V) and secondary (12 V) sides of transformer correctly.
55. Identify anode (A) and cathode (K) of 1N4007 diode correctly.
56. Connect electrolytic capacitor with correct polarity (+ve terminal to +ve node).
57. Ensure transformer secondary voltage rating matches capacitor voltage rating.

4.6 Viva Questions — Full Answers

Q: What is a rectifier?
A rectifier is an electronic circuit that converts alternating current (AC) — which periodically reverses
direction — into direct current (DC) — which flows in only one direction. This is achieved by using the
unidirectional current-conduction property of semiconductor diodes. Rectifiers are essential in all DC
power supplies (phones, computers, TVs) to convert the AC mains supply into the DC needed by electronic
circuits. Types include half-wave rectifier (one diode, uses one half of AC cycle), full-wave center-tap
rectifier (two diodes), and bridge rectifier (four diodes, full-wave, no center tap needed).
Q: What is a filter?

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A filter is a circuit element (or network) used after a rectifier to smooth the pulsating DC output into a
steady DC level by removing (filtering out) the AC ripple components. The most common filter for
rectifiers is a CAPACITOR FILTER: a large electrolytic capacitor placed in parallel with the load. The
capacitor charges during the voltage peaks and discharges through the load between peaks, filling in the
'gaps' and maintaining a nearly constant output voltage. Other filter types include inductor (choke) filters
(series with load), LC filters (inductor + capacitor), and π-filters (capacitor-inductor-capacitor). The larger
the filter capacitor and load resistance, the less the ripple.
Q: Define Ripple Factor.
The ripple factor (γ) quantifies the AC ripple remaining in the rectified DC output. It is defined as: γ = Vac
/ Vdc = √[(Vrms/Vdc)² − 1] where Vac is the RMS value of the AC ripple component, and Vdc is the
average DC output. A LOWER γ = less ripple = better DC quality. For half-wave rectifier: γ = 1.21 (the
AC ripple is 121% of the DC output — very poor) For full-wave rectifier: γ = 0.482 (better) With capacitor
filter (HWR, C=1000μF, RL=1KΩ, f=50Hz): γ = 1/(2√3×50×10⁻³×10³) ≈ 0.006 (excellent)
Q: What is Peak Inverse Voltage (PIV)?
The Peak Inverse Voltage (PIV), also called Peak Reverse Voltage (PRV), is the maximum reverse voltage
that appears across a rectifier diode when it is NOT conducting. It determines the minimum voltage rating
the diode must have to avoid reverse breakdown. For HWR: PIV = Vm (peak secondary voltage) For
Center-Tap FWR: PIV = 2Vm (the non-conducting diode sees the full secondary voltage) For Bridge
FWR: PIV = Vm (lowest PIV requirement per diode) For a 12 V secondary: Vm = 12×√2 ≈ 17 V. The
1N4007 (PIV = 1000 V) is far more than sufficient for all these configurations. PIV rating must never be
exceeded or the diode breaks down.
Q: How does a capacitor act as a filter?
A capacitor filter exploits the capacitor's ability to store charge and release it gradually. In a half-wave
rectifier:
1. CHARGING PHASE: When the rectified output rises toward Vm (during diode conduction), the
capacitor charges rapidly toward Vm through the low diode resistance.
2. DISCHARGING PHASE: After the peak, the rectified voltage falls. The diode becomes reverse biased
(capacitor voltage > diode output). The capacitor now DISCHARGES slowly through RL with time
constant τ = RL×C, maintaining the output voltage.
3. RECHARGING: At the next positive peak the diode conducts again and recharges the capacitor to Vm.
The voltage sags slightly during discharge (ripple voltage Vr). A larger C or RL means slower discharge
and smaller Vr. The ripple factor = 1/(2√3·f·C·RL) for HWR with filter.
Q: Define percentage voltage regulation.
Percentage voltage regulation measures how much the output DC voltage changes between no-load and
full-load conditions: % Regulation = [(VNL − VFL)/VFL] × 100% VNL = No-Load voltage (output when
no load is connected, RL = ∞) VFL = Full-Load voltage (output at minimum RL = maximum load current)
An IDEAL regulator has 0% regulation (output unchanged regardless of load). A practical HWR without
filter has poor regulation (high %) because the output voltage drops significantly under load due to the
diode resistance and transformer impedance. With a capacitor filter, regulation improves because the
capacitor acts as a local energy reservoir maintaining output voltage.
Q: What are the applications of rectifiers?
Rectifiers are used in virtually every electronic system:

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1. DC Power Supplies: Convert AC mains to DC for all electronic equipment.

2. Battery Chargers: AC-to-DC conversion for charging batteries.
3. AM Radio Demodulation: Half-wave rectifier (envelope detector) demodulates AM signals.
4. Signal Processing: Peak detectors, sample-and-hold circuits.
5. Welding Equipment: High-current rectifiers for DC arc welding. 6. Electrolysis and Electroplating:
Requires DC.
7. HVDC Transmission: High-voltage DC power transmission.
8. Solar Inverter Interfaces: Convert between AC and DC in renewable energy systems.
Q: Define transformer utilisation factor (TUF).
The Transformer Utilisation Factor (TUF) is the ratio of the DC output power (Pdc) to the VA (volt-
ampere) rating of the transformer secondary: TUF = Pdc / (Vs(rms) × Is(rms)) It measures how effectively
the transformer is used in the rectifier circuit. For HWR (without filter): TUF ≈ 0.287 — the transformer is
poorly utilised because only one half cycle is used, and a DC component in the secondary causes core
magnetisation (DC saturation). For Center-Tap FWR: TUF ≈ 0.693 (better). For Bridge FWR: TUF ≈
0.812 (best — no center tap needed, higher utilisation). A low TUF means a larger, more expensive
transformer is needed for the same DC output.

4.7 MCQ Practice — Experiment 4: Half-Wave Rectifier

# Question & Options Answer Explanation

1 The ripple factor of a half-wave C) 1.21 γ = √[(Vrms/Vdc)²−1] = √[(Vm/2 ÷ Vm/π)²−1] =

rectifier WITHOUT filter is √[(π/2)²−1] = √[2.467−1] = √1.467 ≈ 1.21. This
approximately: means the AC ripple is 121% of the DC — very poor
DC quality without filtering.
A) 0.48
B) 1.00
C) 1.21
D) 2.00

2 The average (DC) output of a half- B) Vm/π Vdc = (1/2π)∫₀^π Vm sin(θ) dθ = Vm/π ≈ 0.318 Vm.
wave rectifier is: Only one half cycle contributes, so the average is
A) Vm/2π Vm/π, not 2Vm/π (which is for full-wave).
B) Vm/π
C) 2Vm/π
D) Vm/√2

3 The output frequency of a half-wave B) 50 Hz HWR passes only ONE half cycle per input cycle. So
rectifier fed by a 50 Hz supply is: the output has one pulse per input period — same
A) 25 Hz frequency as the input (50 Hz). Full-wave gives 100
Hz (two pulses per cycle).
B) 50 Hz
C) 100 Hz
D) 200 Hz

4 For a HWR with C=1000μF filter, C) 0.006 γ = 1/(2√3·f·C·RL) = 1/(2×1.732×50×0.001×1000) =

f=50Hz, RL=1KΩ, the ripple factor is 1/173.2 ≈ 0.006 — excellent filtering (γ << 1).
approximately: Compare to 1.21 without filter.
A) 1.21
B) 0.482

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C) 0.006
D) 0.29

5 The PIV rating of the diode in a half- B) Vm In HWR, the non-conducting diode sees the full peak
wave rectifier must be at least: secondary voltage in reverse: PIV = Vm. For a 12V
A) Vm/2 secondary: Vm = 12√2 ≈ 17 V. The 1N4007
(PIV=1000V) is far more than sufficient.
B) Vm
C) 2Vm
D) √2·Vm

6 The rectification efficiency of a half- B) 40.6% η = Pdc/Pac = (Vdc/Vm)²/(Vrms/Vm)² = (1/π)²/(1/2)²

wave rectifier is approximately: = 4/π² ≈ 40.6%. The full-wave rectifier achieves
A) 20.3% 81.2% — double, because it uses both half cycles.
B) 40.6%
C) 81.2%
D) 100%

7 The purpose of the electrolytic B) Store The capacitor charges to peak voltage during
capacitor in the HWR filter circuit is and release conduction and discharges slowly through RL
to: energy to between peaks, filling in the voltage troughs and
smooth the reducing ripple. The bigger C and RL, the better the
A) Block DC from reaching the load
output smoothing (smaller ripple).
B) Store and release energy to smooth the
output
C) Increase the output frequency
D) Protect the diode from PIV

8 Which has BETTER voltage regulation B) With With a filter capacitor, the output stays close to Vm
— HWR with filter or without filter? filter even under load (capacitor acts as a local charge
A) Without filter reservoir). Without filter, the output drops
significantly under load (VFL << VNL). So %
B) With filter
regulation is lower (better) with filter.
C) Both are equal
D) Depends on frequency

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Experiment 5: Full-Wave Rectifier with and without Filter

5.1 Objectives
58. Plot input and output waveforms of Full-Wave Rectifier with and without Filter.
59. Find ripple factor for Full-Wave Rectifier with and without Filter.
60. Find regulation for Full-Wave Rectifier.

5.2 Apparatus
[Link] Apparatus Type Range Qty
01 Center-Tapped Transformer Single Phase 230 V/(12-0-12) V, 50 Hz 01
02 Diode 1N4007 PIV=1000 V, IF=1 A 02
03 Load Resistance Carbon 1 KΩ 01
04 Electrolytic Capacitor Filter 1000 μF/25 V 01
05 Digital Multimeter AC/DC 0–20 V 01
06 CRO with Probes Dual Trace — 01
07 Breadboard and Wires — — As reqd

5.3 Theory
5.3.1 Full-Wave Center-Tap Rectifier
Uses TWO diodes (D1, D2) and a center-tapped transformer (12-0-12 V). The center tap is the common
reference (neutral). D1 connects to the top of the secondary; D2 to the bottom.
POSITIVE HALF CYCLE: Top of secondary is positive → D1 forward biased (conducts), D2 reverse biased.
Current flows: Top → D1 → RL → Center tap.
NEGATIVE HALF CYCLE: Bottom of secondary is positive → D2 forward biased (conducts), D1 reverse
biased. Current flows: Bottom → D2 → RL → Center tap.
Both half cycles produce current in the SAME direction through RL — full-wave rectification.

5.3.2 Key Parameters — Without Filter

Full-Wave Rectifier Formulas (No Filter)

Vdc (average output) = 2Vm / π ≈ 0.636 Vm (double HWR)
Vrms (output RMS) = Vm / √2 = 0.707 Vm
Ripple Factor γ = √[(Vrms/Vdc)² − 1] = √[π²/8 − 1] ≈ 0.482
Efficiency η = 81.2% (double HWR!)
PIV per diode = 2Vm (non-conducting diode sees full secondary)
Output frequency = 2 × fin = 100 Hz for 50 Hz input

5.3.3 With Capacitor Filter

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Ripple Factor (FWR with C filter) = 1 / (4√3 · f · C · RL)

The factor 4 (vs 2 for HWR) means FWR with filter has HALF the ripple of HWR with same C, RL, f. This is
because the capacitor only needs to hold the voltage for half the period (1/100 s instead of 1/50 s), resulting in
less droop.

5.4 Procedure
Without Filter
61. Connect FWR circuit per diagram (no capacitor). Apply AC mains to primary.
62. Measure Vac and Vdc at output with DMM; compute γ = Vac/Vdc.
63. Observe CRO waveform; verify output frequency = 100 Hz (two pulses per 20 ms cycle).

With Filter
64. Add 1000 μF/25V capacitor across RL (correct polarity).
65. Measure Vac and Vdc; compute γ. Compare with unfiltered value.
66. Observe CRO; note smoother DC with only small residual ripple.

5.5 Precautions
67. Correctly identify primary (230 V) and secondary (12-0-12 V) of transformer.
68. The CENTER TAP must be connected to the negative terminal of output (common ground).
69. Identify anode and cathode of each 1N4007 diode carefully.
70. Capacitor polarity: +ve terminal to positive output node.

5.6 Viva Questions — Full Answers

Q: What are the advantages of a full-wave rectifier over a half-wave rectifier?
1. HIGHER DC OUTPUT VOLTAGE: Vdc(FWR) = 2Vm/π ≈ 0.636 Vm vs Vdc(HWR) = Vm/π ≈ 0.318
Vm — DOUBLE the DC output.
2. LOWER RIPPLE FACTOR: γ(FWR) = 0.482 vs γ(HWR) = 1.21 — much smoother DC, far less
filtering needed.
3. HIGHER EFFICIENCY: η(FWR) = 81.2% vs η(HWR) = 40.6% — FWR is twice as efficient.
4. HIGHER OUTPUT FREQUENCY: Output is 100 Hz (for 50 Hz input) vs 50 Hz (HWR). Higher
frequency ripple is easier to filter — smaller capacitor needed for the same ripple reduction.
5. BETTER TRANSFORMER UTILISATION (TUF): TUF(FWR) ≈ 0.693 vs TUF(HWR) ≈ 0.287 —
transformer is used more efficiently (no DC saturation of core). 6. LESS RIPPLE WITH FILTER:
γ(FWR+filter) = 1/(4√3·f·C·RL) vs γ(HWR+filter) = 1/(2√3·f·C·RL) — FWR with filter has HALF the
ripple of HWR with same components.
Q: Compare the PIV of half-wave and full-wave rectifiers.
HALF-WAVE RECTIFIER: PIV = Vm. The single diode sees the full peak reverse voltage of the
secondary when reverse biased. CENTER-TAP FULL-WAVE RECTIFIER: PIV = 2Vm per diode. When
D1 conducts (positive half cycle), D2 is reverse biased and sees the full secondary voltage (2Vm = sum of
both halves: +Vm across D1 output and −Vm from the other half of secondary). This is a

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DISADVANTAGE of the center-tap design. BRIDGE RECTIFIER (4 diodes): PIV = Vm per diode —
same as HWR, but achieves full-wave rectification. This is why bridge rectifiers are preferred over center-
tap designs for high-voltage applications. For a 12-0-12 V transformer: Vm = 12√2 ≈ 17 V. Center-tap
FWR needs diodes rated ≥ 34 V PIV. 1N4007 (1000 V PIV) is vastly over-rated — deliberately chosen for
safety margin.
Q: Why is a center-tapped transformer required for full-wave rectification (two-diode circuit)?
The center-tapped transformer is required because the two-diode FWR needs TWO AC voltage sources
that are equal in magnitude but 180° out of phase, sharing a common reference point (center tap). During
the positive half cycle, the upper end of secondary (+Vm) drives D1 forward, while D2 (connected to lower
end, −Vm) is reverse biased. Current returns via the center tap. During the negative half cycle, the lower
end (+Vm relative to center) drives D2 forward, D1 is reverse biased. Current again returns via center tap.
Without the center tap, both D1 and D2 would be in different loops with no common return path — correct
rectification would be impossible with two diodes. ALTERNATIVE: The 4-diode BRIDGE rectifier
achieves full-wave rectification without a center-tapped transformer, at the cost of two extra diodes and
double the diode voltage drop (~1.4 V total vs ~0.7 V for two-diode FWR).

5.7 MCQ Practice — Experiment 5: Full-Wave Rectifier

# Question & Options Answer Explanation

1 The ripple factor of a full-wave B) 0.482 γ(FWR) = √[(Vrms/Vdc)²−1] = √[(Vm/√2 ÷

rectifier WITHOUT filter is 2Vm/π)²−1] = √[(π/(2√2))²−1] = √[π²/8−1] =
approximately: √0.234 ≈ 0.482. Much better than HWR (1.21) —
both half cycles contribute to DC.
A) 1.21
B) 0.482
C) 0.707
D) 2.00

2 The DC output voltage of a full-wave C) 2Vm/π Vdc(FWR) = (1/π)∫₀^π Vm sin(θ) dθ = 2Vm/π ≈

rectifier is: 0.636 Vm. Both half cycles contribute, doubling the
A) Vm/π average compared to HWR (Vm/π).
B) Vm/2π
C) 2Vm/π
D) Vm/√2

3 Output frequency of a full-wave C) 100 Hz FWR rectifies both half cycles → two pulses per
rectifier (50 Hz input) is: input period (20 ms) → output frequency = 2 × 50
A) 25 Hz Hz = 100 Hz. This higher frequency is easier to
filter (smaller C needed for same ripple).
B) 50 Hz
C) 100 Hz
D) 200 Hz

4 PIV per diode in a center-tapped C) 2Vm When D1 conducts (upper half cycle), D2 is reverse
FWR is: biased and sees the combined voltage of the D1
A) Vm/2 output (+Vm) plus the lower secondary (−Vm
referenced to center tap, so +Vm reversed = another
B) Vm
Vm). Total PIV = 2Vm per diode — higher than
C) 2Vm HWR (Vm) or bridge (Vm).
D) √2·Vm

5 The ripple factor formula for FWR B) γ = γ(FWR+filter) = 1/(4√3·f·C·RL) — HALF of

with capacitor filter is: 1/(4√3·f·C·RL) HWR filter (which is 1/(2√3·f·C·RL)). The factor 4
A) γ = 1/(2√3·f·C·RL) vs 2 reflects the fact that FWR output pulses are at

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B) γ = 1/(4√3·f·C·RL) 100 Hz (C discharges for only 10 ms between

C) γ = Vm/(2fCRL) peaks vs 20 ms for HWR).
D) γ = 1/(f·C·RL)

6 The rectification efficiency of a full- C) 81.2% η(FWR) = 8/π² ≈ 81.2% — exactly DOUBLE the
wave rectifier is approximately: HWR efficiency (40.6%). This is because FWR
A) 40.6% uses both half cycles of the AC input, converting
twice as much input power to useful DC output.
B) 60%
C) 81.2%
D) 100%

7 Compared to HWR, the FWR C) Higher TUF(HWR) ≈ 0.287 — very poor because only one
transformer utilisation factor (TUF) (≈0.693) half cycle is used and DC flows in secondary
is: (causing core saturation risk). TUF(FWR center-
tap) ≈ 0.693 — better because both halves are used
A) Lower (≈0.287)
and the DC components in the two halves cancel in
B) Equal
the core. Bridge TUF ≈ 0.812 (best).
C) Higher (≈0.693)
D) Always 1.0

8 A key advantage of the bridge B) Does NOT Bridge rectifier uses 4 diodes but works with ANY
rectifier over the center-tap FWR is: require a transformer secondary (no center tap required).
A) Higher output voltage center-tapped Center-tap FWR uses only 2 diodes but needs a
transformer special center-tapped transformer (more expensive,
B) Does NOT require a center-tapped
heavier, harder to obtain in some voltages). Also
transformer
bridge PIV = Vm vs center-tap PIV = 2Vm per
C) Fewer diodes needed diode.
D) Lower ripple factor

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Quick Reference: Part 1 — All Key Formulas

Parameter Formula / Value Notes
Shockley equation I = I₀(e^(V/ηVT) − 1) η=1 Ge, η=2 Si; VT=26mV at 25°C
Static resistance R_DC = VF / IF At Q-point; DC ratio
Dynamic resistance r_d = ΔVd / ΔId Tangent slope at Q; ≈ η·VT/ID
Zener regulation % Reg = [(VNL−VFL)/VFL]×100 Ideal = 0%
HWR Vdc (no filter) Vdc = Vm / π ≈ 0.318 Vm One half cycle averaged
HWR Vrms (no filter) Vrms = Vm / 2 = 0.500 Vm RMS of half-sine
HWR ripple (no filter) γ = 1.21 Theoretical value
HWR ripple (C filter) γ = 1/(2√3·f·C·RL) Smaller C/RL → larger γ
FWR Vdc (no filter) Vdc = 2Vm/π ≈ 0.636 Vm Double HWR
FWR Vrms (no filter) Vrms = Vm/√2 ≈ 0.707 Vm Full-sine RMS
FWR ripple (no filter) γ = 0.482 Theoretical value
FWR ripple (C filter) γ = 1/(4√3·f·C·RL) Half of HWR with same C
PIV — HWR PIV = Vm Single diode
PIV — Center-tap FWR PIV = 2Vm per diode Higher rating needed
PIV — Bridge FWR PIV = Vm per diode 4 diodes, lower PIV

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Bipolar Junction Transistor (BJT)

The BJT is a three-terminal (Emitter E, Base B, Collector C) semiconductor device. Two types: NPN
(majority carriers: electrons) and PNP (majority carriers: holes). The base is very thin and lightly
doped — key to transistor action. A small base current or base-emitter voltage controls a much
larger collector current.

BJT Key Relationships

IE = IC + IB
α (hfb) = IC/IE < 1 | β (hfe) = IC/IB >> 1
β = α/(1−α) | α = β/(1+β)

Regions of Operation
ACTIVE: EBJ forward, CBJ reverse | IC = β·IB | Used for AMPLIFICATION
SATURATION: Both junctions forward | VCE ≈ 0.1–0.2 V | Transistor fully ON (closed switch)
CUT-OFF: Both junctions reverse | IC ≈ 0, IB = 0 | Transistor fully OFF (open switch)

Experiment 6: Common Base (CB) BJT Configuration

6.1 Objectives
1. Plot input characteristics (IE vs VEB) at constant VCB.
2. Plot output characteristics (IC vs VCB) at constant IE.
3. Compute h-parameters: hib, hrb, hob, hfb.

6.2 Apparatus
[Link] Apparatus Type Range Qty
01 NPN Transistor BC107 — 01
02 Resistance Carbon 1 KΩ 02
03 Regulated Power Supply DC 0–30 V 02
04 Ammeter MC 0–100 mA, 0–50 mA 01 each
05 Voltmeter MC 0–2 V, 0–20 V 01 each
06 Breadboard and Wires — — As reqd

6.3 Theory
6.3.1 CB Configuration

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Base is COMMON to both input (Emitter-Base) and output (Collector-Base) circuits. Input signal
applied between Emitter and Base; output taken between Collector and Base.

CB Configuration Properties
Input current: IE (large, mA range) | Output current: IC (slightly < IE)
Current gain hfb = α = IC/IE < 1 (typically 0.95–0.999)
Input impedance hib: LOW (20–50 Ω) — E-B is forward biased junction
Output impedance 1/hob: VERY HIGH (MΩ range)
Phase relationship: NO phase inversion (non-inverting)
Application: High-frequency amplifiers, impedance matching (low→high), cascode amplifier

6.3.2 Input Characteristics

Plot IE vs VEB at constant VCB (0 V, 5 V, 10 V). The curves resemble a forward-biased diode. As
VCB increases, curves shift slightly right — more VEB needed for same IE at higher VCB. This shift
is the EARLY EFFECT: higher VCB widens depletion region into the base, narrowing effective base
width, reducing recombination.

6.3.3 Output Characteristics

Plot IC vs VCB at constant IE (10 mA, 15 mA, 20 mA). In the ACTIVE REGION (VCB > 0), IC ≈ α·IE
— nearly independent of VCB. Curves are nearly flat (ideal current source). Slight upward slope
due to Early Effect (narrower base → more carriers reach collector as VCB increases).

6.3.4 h-Parameters for CB

Parameter Symbol Formula Typical Value

Input Impedance hib (Ω) ΔVEB / ΔIE | VCB=const 20–50 Ω

Reverse Voltage hrb ΔVEB / ΔVCB | IE=const 10⁻³ – 10⁻⁴

Gain
Forward Current hfb = α ΔIC / ΔIE | VCB=const 0.95–0.999
Gain

Output Admittance hob (S) ΔIC / ΔVCB | IE=const 0.1–1 μS

6.4 Procedure
Input Characteristics
4. Connect BC107 in CB config (Base grounded). Set VCB=0V.
5. Vary VEE to change VEB in 0.1 V steps. Record IE for each VEB.
6. Repeat for VCB = 5 V and VCB = 10 V.
7. Plot IE (Y) vs VEB (X) at each constant VCB.

Output Characteristics
8. Set IE = 10 mA (adjust VEE). Vary VCC to change VCB from 0–20 V (steps of 1 V). Record
IC.
9. Repeat for IE = 15 mA and 20 mA.

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10. Plot IC (Y) vs VCB (X) at each constant IE.

11. Calculate h-parameters from the graphs (see formulas above).

6.5 Precautions
12. Never exceed BC107 ratings: IC(max)=100 mA, VCE(max)=45 V, PD(max)=300 mW.
13. Correctly identify Emitter, Base, Collector terminals of BC107.
14. Connect ammeters and voltmeters with correct polarities.
15. Do not switch ON supply until all connections are verified.

6.6 Viva Questions — Full Answers

Q: What is the Early Effect?
The Early Effect (base-width modulation) is the phenomenon where the effective width of the BJT
base region changes with the collector-base voltage VCB. As VCB increases (greater reverse
bias on CBJ), the depletion region at the collector-base junction widens and encroaches into the
base, reducing the effective base width WB. A narrower base means: • Fewer electron-hole
recombinations in the base → more injected carriers reach the collector. • IC increases slightly
with VCB even in the active region (the output curves are NOT perfectly flat). • On output
characteristics, the slightly rising curves, when extrapolated backward, all converge at a point on
the negative VCB axis called the EARLY VOLTAGE VA (typically −50 V to −200 V). VA
characterises the output impedance in the active region. Higher |VA| = flatter curves = better
current source behaviour.
Q: Draw the small signal model of BJT Common Base Configuration.
The small-signal equivalent circuit (T-model or h-parameter model) for CB: T-MODEL: Emitter
(E) ──[re]── Base (B) | [αie source] | Collector (C)
←────────── Where re = η·VT/IC ≈ 26/IC(mA) Ω (Si, η=1 for CB), and the controlled
current source α·ie delivers collector current. h-PARAMETER MODEL: Input: VEB = hib·ie +
hrb·VCB Output: ic = hfb·ie + hob·VCB Key values: hib ≈ 20–50 Ω (low input Z), hfb = α ≈ 0.95–
0.999, hob ≈ 0.1–1 μS (high output Z), hrb ≈ 10⁻³–10⁻⁴ (very small feedback).
Q: What is Reach-Through (Punch-Through) Effect?
Reach-through (punch-through) occurs when the reverse bias on the collector-base junction
(VCB) is so high that the collector depletion region extends COMPLETELY THROUGH the base
and physically reaches the emitter depletion region. When punch-through occurs: • The base
region is entirely depleted — the collector depletion region touches the emitter depletion region
directly. • The transistor loses all control — collector current becomes very large, uncontrolled by
base current, determined only by the external circuit. • This is generally a destructive condition
and can permanently damage the transistor. • Prevention: Never exceed VCBmax (for BC107:
VCBmax = 50 V). Punch-through voltage VPT depends on base doping and width — lightly
doped, narrow bases are more susceptible.
Q: What are the applications of Common Base configuration?
Common Base (CB) has a current gain α < 1, so it is NOT used where current gain is needed.
However CB has specific advantages that make it useful for: 1. HIGH-FREQUENCY
AMPLIFIERS: CB has no Miller effect (CBC is not amplified as in CE), giving much better high-
frequency performance. Used in VHF/UHF/microwave amplifiers, TV tuners, satellite receivers. 2.

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CASCODE AMPLIFIER: CE stage (for high gain) followed by CB stage (for wide bandwidth and
high output impedance). Combines benefits of both. 3. IMPEDANCE MATCHING: Converts a
low-impedance source (hib ≈ 20–50 Ω) to a high-impedance output (1/hob ≈ 1 MΩ) — useful for
matching between stages. 4. CURRENT BUFFER: Unity current gain (approximately), extremely
low input Z, very high output Z. 5. PHASE PRESERVATION: Non-inverting — used when 180°
phase shift is undesirable.
Q: What will be the h-parameters of CB configuration?
The four h-parameters for CB configuration, their symbols, and typical values for BC107: hib
(Short-circuit input impedance): hib = ΔVEB/ΔIE |VCB=const ≈ 20–50 Ω. Very LOW because E-B
is a forward-biased junction. hrb (Open-circuit reverse voltage gain): hrb = ΔVEB/ΔVCB
|IE=const ≈ 10⁻³ to 10⁻⁴. Very small — little feedback from output to input in CB. hfb (Short-circuit
forward current gain): hfb = ΔIC/ΔIE |VCB=const = α ≈ 0.95 to 0.999. Less than 1 — a
characteristic property of CB (no current amplification). hob (Open-circuit output admittance):
hob = ΔIC/ΔVCB |IE=const ≈ 0.1–1 μS. Very small → 1/hob ≈ 1–10 MΩ output impedance (very
HIGH).
Q: Explain transistor operation.
A BJT operates by controlling a large collector current IC with a small base current IB (CE) or a
large emitter current IE (CB). For NPN in ACTIVE region:
1. The emitter-base junction (EBJ) is forward biased (VBE ≈ 0.7 V). This injects large numbers of
electrons from the N-type emitter into the P-type base.
2. In the base, most injected electrons do NOT recombine with holes (the base is very thin and
lightly doped — few recombination sites). Most electrons diffuse across the base.
3. The collector-base junction (CBJ) is reverse biased. The electric field at the CBJ sweeps the
electrons that reach it into the collector.
4. Since most emitter electrons (≈99%) reach the collector: IC ≈ IE, so α = IC/IE ≈ 0.99.
5. Only a small fraction (~1%) of emitter electrons recombine in the base, forming the small base
current IB.
6. Since IB = IE − IC and IC ≈ αIE: IB = IE(1−α) = very small. Thus β = IC/IB = α/(1−α) >> 1. This
current-control principle makes BJT a useful amplifier and switch.

6.7 MCQ Practice — Experiment 6: Common Base

# Question & Options Answer Explanation

1 In Common Base configuration, B) Base In CB, the BASE is the common terminal. Input
which terminal is common to input is applied between Emitter-Base; output is
and output? taken between Collector-Base. The base
terminal is shared (common) between the input
A) Emitter
and output loops.
B) Base
C) Collector
D) None

2 Forward current gain (hfb = α) in C) Less α = IC/IE < 1 (typically 0.95–0.999). Some
CB is: than 1 emitter-injected carriers recombine in the base,
A) Greater than 1 so IC is always slightly less than IE. This is why
CB does not provide current amplification — it

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B) Equal to 1 is not used for current gain.

C) Less than 1
D) Much greater than 1

3 Input impedance (hib) of CB C) Very low The CB input port (E-B junction) is a forward-
configuration is: (20–50 Ω) biased junction with very low dynamic
A) Very high (MΩ) resistance re. hib ≈ re = ηVT/IE ≈ 26/IE(mA) Ω.
At IE=1 mA: hib ≈ 26 Ω. This low input Z limits
B) Medium (KΩ)
CB's versatility but makes it good for matching
C) Very low (20–50 Ω) low-Z sources.
D) Zero

4 In CB output characteristics B) Nearly IC = α·IE in the active region. Since α and IE

(active region), IC is: independent are approximately constant, IC is nearly
A) Proportional to VCB of VCB independent of VCB. This gives the CB output
curves a nearly flat (horizontal) shape — ideal
B) Nearly independent of VCB
current source behaviour.
C) Zero
D) Equal to IB

5 The Early Effect in BJT refers to: B) Base- The Early Effect is the modulation of effective
A) Breakdown at low temperature width base width by the collector-base voltage VCB.
modulation Higher VCB widens the CBJ depletion region
B) Base-width modulation by VCB
by VCB into the base, narrowing it. Narrower base →
C) Emitter efficiency decreasing with
less recombination → slightly higher IC. This
current
causes a slight positive slope in CB/CE output
D) Thermal runaway characteristics.

6 Reach-through (punch-through) B) Collector Punch-through happens at very high VCB

occurs when: depletion when the CBJ depletion region expands
A) IE exceeds IC region through the entire base and reaches the EBJ
touches the depletion region. The base is completely
B) Collector depletion region touches
emitter depleted; transistor loses control — large
the emitter depletion region
depletion uncontrolled IC flows. Prevent by not
C) Temperature exceeds 100°C exceeding VCBmax.
D) VBE exceeds 0.7 V region

7 CB configuration is preferred for C) It has no The Miller effect multiplies the feedback
high-frequency amplifiers Miller effect capacitance CBC (or CGD in FET) by the
because: voltage gain, dramatically increasing effective
input capacitance at high frequencies. In CB
A) It has the highest current gain
configuration, the collector is not at the input
B) It has the lowest noise side, so the feedback from CBC does not
C) It has no Miller effect cause Miller multiplication. CB maintains wider
D) It has highest input impedance bandwidth than CE at high frequencies.

8 The relationship between α and β A) β = From IE = IC + IB: divide by IC gives IE/IC = 1

is: α/(1−α) + IB/IC → 1/α = 1 + 1/β → β = α/(1−α). Also α =
A) β = α/(1−α) β/(1+β). For α=0.99: β = 0.99/0.01 = 99. For
α=0.995: β = 0.995/0.005 = 199.
B) α = β/(1−β)
C) β = α + 1
D) α = β − 1

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Experiment 7: Common Emitter (CE) BJT Configuration

7.1 Objectives
16. Plot input characteristics (IB vs VBE) at constant VCE.
17. Plot output characteristics (IC vs VCE) at constant IB.
18. Compute h-parameters: hie, hre, hoe, hfe.

7.2 Apparatus
[Link] Apparatus Type Range Qty
01 NPN Transistor BC107 — 01
02 Resistance Carbon 300 KΩ, 1 KΩ 01 each
03 Regulated Power Supply DC 0–30 V 01
04 Ammeter MC 0–100 mA, 0–100 μA 01 each
05 Voltmeter MC 0–2 V, 0–20 V 01 each
06 Breadboard and Wires — — As reqd

7.3 Theory
7.3.1 CE Configuration — Why Most Widely Used
Emitter is COMMON to both input (Base-Emitter) and output (Collector-Emitter) circuits. CE is the
most widely used configuration because:
• Highest current gain: β = hfe = IC/IB typically 50–300 (far exceeds CB's α < 1)
• Highest power gain of the three configurations
• Moderate input impedance: hie ≈ 1–10 KΩ (suitable for most sources)
• Moderate output impedance: 1/hoe ≈ 10–100 KΩ
• Phase inversion: output is 180° inverted relative to input

7.3.2 Input Characteristics (IB vs VBE at constant VCE)

The curves resemble forward-biased diode V-I curves (B-E is forward biased). As VCE increases,
the curves shift right (more VBE needed for same IB) due to Early Effect narrowing the base.

7.3.3 Output Characteristics (IC vs VCE at constant IB)

• ACTIVE REGION (VCE >VCE(sat), VBE ≈ 0.7V): IC ≈ β·IB — nearly constant for a given IB.
Slight upward slope = Early Effect. These nearly flat lines are the amplification region.
• SATURATION REGION (VCE < ~0.2V): Both junctions forward biased. Transistor fully ON.
IC limited by external circuit.
• CUT-OFF (IB = 0, VBE < 0.5V): IC ≈ ICEO (tiny leakage). Transistor fully OFF.

7.3.4 h-Parameters for CE

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Parameter Symbol Formula Typical Value

Input Impedance hie (Ω) ΔVBE / ΔIB | VCE=const 1–10 KΩ

Reverse Voltage hre ΔVBE / ΔVCE | IB=const 10⁻³ – 10⁻⁴

Gain
Forward Current hfe = β ΔIC / ΔIB | VCE=const 50 – 300
Gain

Output Admittance hoe (S) ΔIC / ΔVCE | IB=const 10–50 μS

7.4 Procedure
Input Characteristics
19. Connect BC107 in CE config (Emitter grounded). Set VCE=0V.
20. Vary VBB to change VBE in 0.1 V steps. Record IB (μA) for each VBE.
21. Repeat for VCE = 5 V and VCE = 10 V.
22. Plot IB (Y, μA) vs VBE (X, V) at each constant VCE.

Output Characteristics
23. Set IB = 0μA. Vary VCC to change VCE from 0–20 V (steps 1 V). Record IC.
24. Repeat for IB = 10 μA, 20 μA, 30 μA, 40 μA.
25. Plot IC (Y, mA) vs VCE (X, V) at each constant IB.
26. Calculate hfe from active region: hfe = ΔIC / ΔIB at constant VCE.

7.5 Precautions
27. Do not exceed BC107 ratings.
28. Identify E, B, C terminals correctly.
29. Ammeter for IB must be sensitive (μA range); for IC use mA range.
30. Verify all connections before powering the circuit.

7.6 Viva Questions — Full Answers

Q: Why is CE configuration most widely used?
CE (Common Emitter) is the most widely used transistor configuration for the following reasons:
1. HIGHEST CURRENT GAIN: β = IC/IB = 50–300. This is far greater than CB (α < 1) and CE's
high β means a tiny base current controls a large collector current — ideal for current
amplification.
2. HIGHEST POWER GAIN: Power gain = voltage gain × current gain. CE achieves the highest
power gain of all three configurations, making it most efficient for power amplification.
3. SUITABLE IMPEDANCE LEVELS: hie ≈ 1–10 KΩ input impedance — high enough not to
excessively load most signal sources. Output impedance 1/hoe ≈ 10–100 KΩ — good match for
typical loads.

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4. SIMPLE BIASING: A single supply can bias a CE stage with a straightforward voltage divider.
5. VERSATILITY: Can be used as voltage amplifier, current amplifier, power amplifier, oscillator
building block, switching circuit, and logic gate. Disadvantage: 180° phase inversion (output is
inverted relative to input) — easily handled by design.
Q: Draw the equivalent circuit of CE configuration.
SMALL-SIGNAL h-PARAMETER EQUIVALENT CIRCUIT for CE: Base (B) ─────[hie]────
Collector (C) | | [hre·Vce] [hfe·Ib]↑ [1/hoe] | | Emitter
(E) ─────────────────── Emitter (E) Input loop: Vbe = hie·ib + hre·Vce Output loop: ic
= hfe·ib + hoe·Vce Simplified T-MODEL (for hand calculations): • hre ≈ 0 (neglect feedback):
simplifies to re model • b-e: small signal resistance re = VT/IC (or β×re = hie) • Collector:
controlled current source ic = β·ib • Simplified: input impedance Zin = hie = β·re; output is current
source β·ib in parallel with large 1/hoe.
Q: What is the current gain, voltage gain, input and output impedance in CE?
CURRENT GAIN (AI): β = hfe = IC/IB typically 50–300. This is the key advantage of CE — the
base current is amplified by β to give the collector current. VOLTAGE GAIN (AV): AV = −β·RL /
hie = −gm·RL, where RL is the load resistance and gm = β/hie = IC/VT is the transconductance.
The negative sign indicates 180° phase inversion. For typical values (β=100, RC=4.7KΩ,
hie=2.6KΩ): AV ≈ −100×4700/2600 ≈ −181. Voltage gain is HIGH. INPUT IMPEDANCE (Zi): Zi =
hie = β·re ≈ 1–10 KΩ. With bias resistors R1||R2 in parallel: Zi = R1||R2||hie — typically hundreds
of ohms to a few KΩ. OUTPUT IMPEDANCE (Zo): Zo = 1/hoe ≈ 10–100 KΩ (with RL in parallel:
Zo(loaded) = RL||1/hoe ≈ RL for typical RL < 10KΩ).
Q: What is the relation between α (alpha), β (beta), and γ (gamma)?
Alpha (α): Common Base current gain. α = IC/IE = hfb. Range: 0.95–0.999. Always < 1. Beta (β):
Common Emitter current gain. β = IC/IB = hfe. Range: 50–300. Always > 1. Gamma (γ): Not a
standard BJT parameter notation in this context. However, the third configuration (Common
Collector or Emitter Follower) has current gain AI = 1+β (current gain > β, close to β+1). Key
relationships: β = α/(1−α) ←→ α = β/(1+β) IE = IC + IB [fundamental Kirchhoff's current law for
BJT] IC = α·IE = β·IB IB = IE − IC = IE(1−α) = IC/β Example: If α = 0.98: β = 0.98/(1−0.98) =
0.98/0.02 = 49. If β = 100: α = 100/101 ≈ 0.99.
Q: Give the conditions to operate the transistor in Active, Saturation, and Cut-off regions.
ACTIVE REGION (used for amplification): • EBJ: Forward biased (VBE ≈ 0.6–0.7 V for Si NPN) •
CBJ: Reverse biased (VCB > 0, or VCE > VCE(sat) ≈ 0.2 V) • IC = β·IB; IC is controlled by IB •
Device acts as a voltage-controlled current source SATURATION REGION (used as closed
switch, ON state): • EBJ: Forward biased (VBE ≈ 0.7 V) • CBJ: Also forward biased (VBC > 0,
i.e., VCE < VBE) • VCE(sat) ≈ 0.1–0.2 V for Si BJT • IC is NOT controlled by IB; determined by
external circuit • Transistor is fully ON; acts like a closed switch (low VCE) CUT-OFF REGION
(used as open switch, OFF state): • EBJ: Reverse biased (VBE < 0.5 V or negative) • CBJ:
Reverse biased • IB ≈ 0, IC ≈ ICEO (collector-emitter leakage, very small) • Transistor is fully
OFF; acts like an open switch
Q: What is Emitter Efficiency?
Emitter efficiency (γ, sometimes called injection efficiency) is defined as the fraction of the emitter
current that is due to minority carrier injection from the emitter into the base: γ = Injected minority
carrier current from emitter into base / Total emitter current IE For NPN: γ = electron current
component of IE / IE = In_E / IE High emitter efficiency is essential for high transistor

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performance because only the carriers injected from the emitter into the base can be swept
across to the collector. Carriers injected from base into emitter (holes from P-base into N-emitter)
contribute to IE but NOT to IC — they are wasted. To maximise γ: • Emitter should be HEAVILY
DOPED (high donor concentration in N-emitter) — so emitter can inject many more electrons
than the base can inject holes • Base should be LIGHTLY DOPED — to minimise hole injection
from base into emitter For BC107: emitter doping >> base doping → γ ≈ 0.995 → excellent.
Emitter efficiency directly contributes to high α (α ≈ γ × base transport factor).

7.7 MCQ Practice — Experiment 7: Common Emitter

# Question & Options Answer Explanation

1 In CE configuration, the phase shift C) 180° CE is an INVERTING amplifier. When input

between input and output is: (inversion) (base) voltage rises, IB increases → IC
A) 0° increases → voltage drop across RC increases
→ VCE = VCC − IC·RC DECREASES. Output
B) 90°
falls when input rises → 180° phase inversion.
C) 180° (inversion)
D) 270°

2 CE forward current gain hfe (beta) B) IC/IB β = hfe = IC/IB. This is the CE short-circuit
equals: current gain — a small base current IB controls
A) IC/IE a large collector current IC, with β = 50–300 for
BC107. This is CE's primary advantage.
B) IC/IB
C) IB/IC
D) IE/IC

3 In saturation region of CE D) Both In saturation BOTH EBJ and CBJ are forward
configuration: junctions biased. VCE ≈ 0.1–0.2 V (very low). The
A) Only EBJ forward biased forward transistor is fully ON. IC is determined by the
biased external circuit (not β·IB). The transistor acts
B) Only CBJ forward biased
like a closed switch with very low VCE across it.
C) Both junctions reverse biased
D) Both junctions forward biased

4 The approximate small-signal input B) 1–10 KΩ hie = β·re = β·(VT/IC). For β=100, IC=1mA: hie
impedance of CE configuration is: = 100×26 = 2600 Ω = 2.6 KΩ. This is much
A) 20–50 Ω higher than CB (hib ≈ 26 Ω) because CE input
current is IB (tiny) while CB input current is IE
B) 1–10 KΩ
(large). Same VBE → higher impedance for
C) 1 MΩ smaller current.
D) Zero

5 Emitter efficiency γ is maximised B) Heavy Emitter efficiency γ = electron injection from

by: emitter emitter / total IE. For NPN, to maximise electron
A) Heavy base doping and light emitter doping injection (useful) and minimise hole injection
doping and light (wasted), the emitter should be HEAVILY doped
base (high electron concentration → more electrons
B) Heavy emitter doping and light base
doping injected) and base should be LIGHTLY doped
doping
(fewer holes → less back-injection into emitter).
C) Equal doping of emitter and base This gives γ → 1.
D) No doping of either region

6 In the output characteristics of CE, B) Nearly In the active region (VCE >VCE(sat) ≈ 0.2V), IC
the ACTIVE REGION is identified flat IC lines = β·IB is nearly constant for a given IB,
by: above a independent of VCE (ideally). The output
small VCE characteristics show nearly horizontal (flat) lines
A) IC rapidly rising with VCE
for each value of IB. The slight positive slope is
B) Nearly flat IC lines above a small
due to the Early Effect.

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VCE
C) IC = 0
D) VCE = 0

7 For BC107 NPN transistor, the C) 110–220 BC107 is specified with hFE (DC current gain β)
typical β (hFE) range is: typically in the range 110–220, with a minimum
A) 1–10 of about 75 and maximum of 300 depending on
the collector current and temperature. This
B) 10–50
relatively high β makes BC107 suitable for audio
C) 110–220 amplifier and switching applications.
D) 1000–5000

8 The voltage gain of a CE amplifier B) AV = AV = −β·RC/hie = −gm·RC, where the negative

(with RC and bypassed RE) is −β·RC/hie sign indicates phase inversion. Since hie = β·re,
approximately: this simplifies to AV = −RC/re. For re =
26/IC(mA) Ω and RC = 4.7 KΩ, IC = 1mA: AV =
A) AV = +RC/re
−4700/26 ≈ −181. High voltage gain is a key
B) AV = −β·RC/hie
advantage of CE.
C) AV = +β/RC
D) AV = RC/RE

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Section 3: Field Effect Transistors (FET)

The FET is a UNIPOLAR (single carrier type) VOLTAGE-CONTROLLED device. Gate voltage VGS
controls drain current ID. Gate draws virtually no current — extremely high input impedance. FETs
dominate modern VLSI (CMOS technology). Types: JFET (junction gate), MOSFET (insulated
gate).
Property BJT JFET

Type Bipolar (electrons + holes) Unipolar (one carrier type)

Control Current-controlled (IB→IC) Voltage-controlled (VGS→ID)

Input Impedance Low-moderate (KΩ for CE) Very High (MΩ gate junction)

Gain Parameter β = IC/IB (dimensionless) gm = ΔID/ΔVGS (Siemens)

Noise Higher Lower (no minority carriers)

Temperature Prone to thermal runaway More thermally stable

Use Discrete amplifiers, linear ICs VLSI, switches, low-noise amps

Experiment 8: Drain and Transfer Characteristics of

JFET
8.1 Objectives
31. Study Drain characteristics (ID vs VDS) and Transfer characteristics (ID vs VGS).
32. Find Drain resistance rd, Transconductance gm, and Amplification Factor μ.

8.2 Apparatus
[Link] Apparatus Type Range Qty
01 N-Channel JFET BFW10 — 01
02 Resistance Carbon 1 KΩ 01
03 Regulated Power Supply DC 0–30 V 01
04 Ammeter MC 0–100 mA 01
05 Voltmeter MC 0–10 V, 0–20 V 01 each
06 Breadboard and Wires — — As reqd

8.3 Theory
8.3.1 N-Channel JFET Structure

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BFW10: N-channel JFET. An N-type semiconductor bar (channel) with Source (S) and Drain (D) at
opposite ends. P-type Gate (G) is diffused into both sides of the N-channel. Positive VDD drives
conventional current from Drain to Source through the N-channel. Negative VGS (Gate-Source
voltage) reverse-biases the P-gate/N-channel junctions, creating depletion regions that squeeze the
channel.

8.3.2 BFW10 Specifications

BFW10 JFET Key Specifications

Type: N-Channel JFET | Package: TO-18
IDSS: 5–30 mA (ID when VGS=0) | VP (Pinch-off): −2 to −7 V
Max VDS: 30 V | Max VGS: 30 V reverse | Max PD: 300 mW
Pin Assignment (from flat side, left to right): Source | Gate | Drain

8.3.3 JFET Operation Regions

• OHMIC REGION (VDS < VGS − VP): Channel resistance approximately constant. ID rises
nearly linearly with VDS. FET acts as voltage-controlled resistor. Used in variable gain
amplifiers, analog switches.
• PINCH-OFF / SATURATION REGION (VDS ≥ VGS − VP): Channel pinched at drain end. ID
saturates ≈ IDSS(1−VGS/VP)². Nearly independent of VDS. Device acts as voltage-
controlled current source. Used for amplification.
• BREAKDOWN REGION: Very large VDS causes avalanche breakdown at gate-drain
junction. Avoid by not exceeding VDS(max).

8.3.4 JFET Shockley Equation

ID = IDSS × (1 − VGS/VP)² for VP ≤ VGS ≤ 0
At VGS=0: ID=IDSS (maximum). At VGS=VP: ID=0 (pinched off, transistor OFF). gm varies with
bias: gm = gmo(1−VGS/VP), where gmo = 2IDSS/|VP| is the maximum transconductance at
VGS=0.

8.3.5 Key Parameters Calculation

Drain resistance: rd = ΔVDS / ΔID (Ω) at const VGS (from
drain characteristics)
Transconductance: gm = ΔID / ΔVGS (A/V or Siemens) at const
VDS (from transfer charac.)
Amplification factor: μ = ΔVDS / ΔVGS atconst ID | also μ = rd
× gm

8.4 Procedure
Drain Characteristics
33. Set VGS=0 (VGG=0). Vary VDD to change VDS in 0.5 V steps (0 to ~15 V). Record ID.
34. Observe:ohmic region (linear rise) then saturation (ID constant at IDSS).
35. Repeat for VGS=−1V and VGS=−2V.
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36. Plot ID (Y) vs VDS (X) at each constant VGS.

Transfer Characteristics
37. Set VDS=1V (constant VDD). Vary VGG to change VGS from 0 to VP in 0.5 V steps. Record
ID.
38. Repeat for VDS=2V and VDS=3V.
39. Plot ID (Y) vs VGS (X) at each constant VDS. Curves are parabolic (Shockley equation).

8.5 Precautions
40. NEVER forward bias the gate junction — this destroys the JFET. Always keep VGS ≤ 0 for
N-channel.
41. Do not exceed JFET ratings: VDS(max)=30V, PD(max)=300mW for BFW10.
42. Identify S, G, D terminals correctly before connecting.
43. Verify connections before powering circuit.

8.6 Viva Questions — Full Answers

Q: What is meant by Field Effect Transistor?
A Field Effect Transistor (FET) is a three-terminal semiconductor device (Source, Gate, Drain) in
which current flow through a semiconductor channel is controlled by an electric FIELD
established by a voltage applied to the Gate terminal — hence the name. Unlike the BJT (a
current-controlled device where base CURRENT controls IC), the FET is a VOLTAGE-
CONTROLLED device: the Gate-Source VOLTAGE (VGS) controls the Drain current (ID). The
gate draws virtually no current (extremely high input impedance). The channel carries current by
majority carriers only (hence UNIPOLAR), unlike BJT which uses both electrons and holes
(BIPOLAR).
Q: What is meant by Unipolar and Bipolar?
UNIPOLAR (FET): Current conduction uses only ONE type of carrier. In an N-channel FET
(JFET, MOSFET), current flows through the N-channel by electrons only. In a P-channel FET,
only holes carry current. Because only majority carriers are involved, FETs have lower noise (no
minority carrier generation/recombination noise) and are less temperature-sensitive than BJTs.
BIPOLAR (BJT): Current conduction involves BOTH types of carriers — electrons AND holes —
working together. In an NPN BJT, electrons are injected from emitter into base (minority carriers
in base), and holes flow from base to emitter. Both carriers are essential to transistor action. This
is why BJT is called 'bipolar' — the operation fundamentally requires both polarities of charge
carriers. The distinction has practical consequences: FETs have higher input Z, lower noise,
better thermal stability; BJTs have higher transconductance, faster switching in some
configurations.
Q: What is the difference between BJT and FET?
CONTROL MECHANISM: BJT is current-controlled (IB → IC); FET is voltage-controlled (VGS →
ID). CARRIER TYPE: BJT is bipolar (uses both electrons and holes); FET is unipolar (one carrier
type). INPUT IMPEDANCE: BJT moderate (1–10 KΩ for CE); FET extremely high (MΩ to TΩ for
MOSFET). GAIN PARAMETER: BJT uses β (current gain, dimensionless); FET uses gm
(transconductance, A/V or Siemens). NOISE: BJT has higher 1/f and shot noise; FET has lower
noise (no minority carrier injection). TEMPERATURE: BJT prone to thermal runaway (IC
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increases with T → more heat → higher IC); FET is self-stabilising (ID decreases with T for most
bias points). SIZE: MOSFET can be made far smaller → VLSI with billions of transistors per
chip. SPEED: Both can be fast; MOSFET has advantage in large integrated circuits due to
smaller size and no minority carrier storage delay. APPLICATION: BJT preferred for discrete
linear circuits; FET (MOSFET) dominates digital ICs and VLSI.
Q: What are the characteristics of FET?
The key V-I characteristics of a JFET are:
1. DRAIN CHARACTERISTICS (ID vs VDS at constant VGS): • Ohmic/linear region: ID rises
linearly with VDS (FET acts as resistor rDS = 1/gmo for VGS=0). • Saturation region: ID saturates
at approximately IDSS(1−VGS/VP)² — nearly flat, independent of VDS. • Higher VGS (less
negative) = higher ID curve. VGS=0 gives maximum ID = IDSS. • Breakdown: Very large VDS
causes device breakdown.
2. TRANSFER CHARACTERISTICS (ID vs VGS at constant VDS): • Parabolic curve following
Shockley equation: ID = IDSS(1−VGS/VP)². • At VGS=0: ID = IDSS (maximum). At VGS=VP: ID
= 0 (cut-off). • Transconductance gm is the slope at any point: gm = 2IDSS/|VP| × (1−VGS/VP). •
gm is maximum at VGS=0 and decreases toward VP.
Q: What is Pinch-Off Voltage?
The Pinch-Off Voltage (VP) is the gate-source voltage VGS at which the JFET channel is
completely depleted of free carriers, reducing the drain current to zero. For N-channel JFET: VP
is NEGATIVE (e.g., −3 V for BFW10). At VGS = VP, the P-gate depletion regions from both sides
of the N-channel meet in the middle, 'pinching off' the channel — no conductive path for
electrons. Physical interpretation: VP is also equal to the drain-source voltage at which the drain
end of the channel just reaches pinch-off when VGS=0: VDS = |VP| (at VGS=0 pinch-off begins).
Shockley equation: ID = IDSS(1−VGS/VP)² = 0 when VGS = VP. For BFW10: VP is typically −2
V to −7 V. The operating range of VGS is: VP ≤ VGS ≤ 0 V. Practical implication: To turn the N-
channel JFET OFF, apply VGS = VP or more negative. To get maximum current, set VGS = 0.
Q: Why is FET called a Voltage-Controlled Device?
The FET is called a VOLTAGE-CONTROLLED DEVICE because the drain current ID is
controlled by the gate-to-source VOLTAGE VGS, not by a gate current. Mechanism: For an N-
channel JFET, the P-gate/N-channel junctions are REVERSE BIASED. A reverse-biased junction
draws virtually zero current. The gate voltage VGS creates an electric FIELD across the narrow
channel. This field modulates the width of the depletion regions in the channel, changing its
effective cross-sectional area and hence its resistance. A more negative VGS → wider depletion
regions → narrower channel → higher resistance → less ID. Consequences: • Gate current IG ≈
0 → input impedance = ∞ (practically MΩ) • No input power consumed by gate (P = VGS × IG ≈
0) • Gain is characterised by transconductance gm = ΔID/ΔVGS (Siemens) rather than current
gain β • FET is an efficient voltage amplifier: ID = gm × VGS (in small-signal model) Contrast
with BJT: IB (current) controls IC → current-controlled. BJT input consumes power (IB × VBE).
Q: Draw the small-signal model of FET.
The small-signal equivalent circuit of a JFET (CS configuration): Gate (G)
──────────────────────── Drain (D) | | | (open) Cgs
[gm·Vgs] ↑ [rd] | | | Source (S)───────────────────────
Source (S) Elements: • Cgs: Gate-Source capacitance (important at high frequencies; causes
gain rolloff) • Cgd: Gate-Drain capacitance (causes Miller effect at high frequencies — not shown

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for simplicity) • gm·Vgs: Controlled current source — models the transconductance action • rd:
Drain resistance = 1/gds = ΔVDS/ΔID (from drain characteristic slope) • Input impedance: ideally
infinite (gate draws no current); practically limited by Cgs at high frequencies Voltage gain (CS,
with load RD): AV = −gm × (RD || rd) ≈ −gm × RD (when rd>> RD)
Q: What are the advantages of FET over BJT?
FET has several important advantages over BJT:
1. EXTREMELY HIGH INPUT IMPEDANCE: Gate draws essentially zero current (reverse-
biased junction for JFET; insulated gate for MOSFET → input Z can be 10¹² Ω). BJT base
requires input current. FET is ideal for high-impedance sources (pH meters, electrometers,
microphones, biosensors).
2. LOWER NOISE: FET current is carried by majority carriers only — no minority carrier injection
or recombination. These processes generate shot noise and generation-recombination noise
which are absent in FET. FET has lower 1/f noise at low frequencies in many designs. Critical for
radio receivers, audio preamplifiers, scientific instruments.
3. BETTER THERMAL STABILITY: FET transconductance gm ∝ 1/√T (decreases with
temperature). Higher temperature → lower ID at same bias → negative feedback → prevents
thermal runaway. BJT IC increases with temperature → positive feedback → risk of thermal
runaway.
4. SMALLER SIZE / SIMPLER FABRICATION: MOSFET can be made with extremely small
dimensions (sub-nanometer gate lengths today). Entire modern computing (CPUs, RAM) is built
with CMOS MOSFETs. Billions of transistors on a single chip.
5. NO OFFSET VOLTAGE: FETs can handle signals all the way down to 0 V (both polarities in
depletion mode), useful in chopper amplifiers and analog switches.
6. SQUARE-LAW CHARACTERISTIC: The parabolic ID-VGS relationship makes JFET useful for
analog multiplication and modulation circuits.

8.7 MCQ Practice — Experiment 8: JFET

# Question & Options Answer Explanation

1 The JFET is a _____ and _____ D) UNIPOLAR: current flows through one carrier
device. Unipolar, type only (electrons for N-channel). VOLTAGE-
A) Bipolar, current-controlled voltage- CONTROLLED: gate voltage VGS controls ID;
controlled gate draws no current. Both properties
B) Unipolar, current-controlled
fundamentally distinguish FET from BJT
C) Bipolar, voltage-controlled (bipolar, current-controlled).
D) Unipolar, voltage-controlled

2 For an N-channel JFET, VGS must B) Zero or For N-channel JFET, VGS ranges from 0 V
be _____ for normal operation. negative (0 (maximum ID = IDSS) to VP (typically −2 to −7
A) Positive to VP) V, where ID = 0). Positive VGS would forward-
bias the gate-channel P-N junction, causing
B) Zero or negative (0 to VP)
gate current and potentially destroying the
C) Exactly zero device.
D) Any value

3 Transconductance gm of JFET is B) gm = ΔID/ΔVGS at constant VDS, in Siemens

defined as: ΔID/ΔVGS | (A/V). It quantifies how effectively VGS controls
A) ΔVDS/ΔID | VGS=const VDS=const ID. Higher gm → higher voltage gain in CS
amplifier (AV = −gm·RD). Measured from the

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B) ΔID/ΔVGS | VDS=const SLOPE of the transfer characteristics (ID vs

C) ΔID/ΔVDS | VGS=const VGS curve).
D) ΔVGS/ΔID | VDS=const

4 In JFET Shockley equation ID = C) ID = 0 When VGS = VP: ID = IDSS(1−VP/VP)² =

IDSS(1−VGS/VP)², when VGS=VP: IDSS(0)² = 0. The device is pinched off —
A) ID = IDSS channel completely depleted — transistor OFF.
When VGS=0: ID=IDSS (maximum). The device
B) ID = IDSS/2
operates between these extremes.
C) ID = 0
D) ID = 2·IDSS

5 The amplification factor μ of JFET C) μ = rd × μ = rd × gm. Derivation: μ = ΔVDS/ΔVGS

relates to rd and gm as: gm |ID=const = (ΔVDS/ΔID) × (ΔID/ΔVGS) = rd ×
A) μ = rd + gm gm. Represents the open-circuit (no-load)
voltage amplification factor. It is an intrinsic
B) μ = rd/gm
device parameter independent of circuit
C) μ = rd × gm configuration.
D) μ = gm/rd

6 The drain characteristics of JFET C) Nearly In the saturation (pinch-off) region, ID ≈

in the SATURATION region show: flat ID lines IDSS(1−VGS/VP)² — nearly independent of
A) Steeply rising ID (ID ≈ const) VDS. The channel is pinched at the drain end;
increasing VDS only extends the pinch-off
B) ID = 0
region without significantly increasing current.
C) Nearly flat ID lines (ID ≈ const) Nearly horizontal curves on the drain
D) Linear increase of ID with VDS characteristics represent the saturation region.

7 JFET is preferred for low-noise B) Current JFET current flows by majority carriers only
amplifiers because: flows by (electrons for N-channel). No minority carrier
A) It has higher gain majority injection or recombination means no
carriers generation-recombination (G-R) noise and no
B) Current flows by majority carriers
only — no shot noise from minority carriers. This gives
only — no minority carrier noise
minority FET amplifiers significantly lower noise than
C) It has lower input impedance BJT amplifiers at audio and RF frequencies —
D) It requires lower supply voltage carrier
noise critical for microphone preamplifiers,
instrumentation amps, radio receivers.

8 Self-bias for N-channel JFET is B) Self-bias: RS is placed between source and

achieved by: Connecting ground. Drain current ID flows through RS,
A) Connecting a negative battery to the RS creating VS = ID×RS > 0. Since VG = 0
gate between (through RG to ground), VGS = VG − VS = 0 −
source and ID×RS = −ID×RS < 0. This automatically
B) Connecting RS between source and
ground creates the required negative VGS for N-
ground
channel JFET without a separate negative
C) Shorting gate to source supply — self-stabilising bias.
D) Using a centre-tapped supply

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Section 4: Amplifier Frequency Response

An amplifier's frequency response describes how its voltage gain varies with the frequency of the
input signal. Understanding frequency response is essential for designing amplifiers that work over
a specified bandwidth.

Key Concepts
Gain (dB) = 20 × log₁₀(Vo/Vi)
Bandwidth (BW) = fH − fL

3-dB Frequencies
fL = Lower 3-dB frequency: gain falls to (max gain − 3 dB) on the low side
fH = Upper 3-dB frequency: gain falls to (max gain − 3 dB) on the high side
At 3-dB points: voltage gain = 0.707 × Av(max) | Power gain = 0.5 × Ap(max)
Mid-band region (fL to fH): gain is maximum and constant
Low freq roll-off: caused by coupling capacitors C1,C2 and bypass capacitor CE (or CS)
High freq roll-off: caused by transistor junction capacitances (CBE, CBC or CGS, CGD)

Experiment 9: Frequency Response of CE Amplifier

9.1 Objectives
44. Obtain frequency response characteristics of Common Emitter amplifier.
45. Determine Bandwidth (BW = fH − fL).

9.2 Apparatus
[Link] Apparatus Type Range Qty
01 NPN Transistor BC107 — 01
02 Resistors Carbon 33KΩ, 4.7KΩ, 2.2KΩ, 01 each
8.2KΩ, 1KΩ
03 Regulated Power Supply DC 0–30V (use 10V) 01
04 Capacitors Electrolytic 10μF (×3) 03
05 Signal Generator AF 10Hz–1MHz 01
06 CRO with Probes Dual trace — 01
07 Breadboard and Wires — — As reqd

9.3 Theory

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9.3.1 CE Amplifier Circuit (VCC=10V)

Component Values and Functions

R1 = 33 KΩ | R2 = 8.2 KΩ → Voltage divider bias (sets Q-point VB)
RC = 4.7 KΩ → Collector resistor (output voltage developed across RC)
RE = 1 KΩ → Emitter resistor (DC stability via negative feedback)
RS = 2.2 KΩ → Series input resistor
C1 = 10 μF → Input coupling capacitor (blocks DC, couples AC to base)
C2 = 10 μF → Output coupling capacitor (blocks DC, couples AC to load)
CE = 10 μF → Emitter bypass capacitor (shorts RE for AC → maximises gain)

9.3.2 Effect of Each Capacitor on Frequency Response

LOW FREQUENCY EFFECTS (coupling and bypass capacitors):
• C1 (input coupling): At low f, XC1=1/(2πfC1) is large → significant signal voltage dropped
across C1 → less VBE → gain reduces. At mid/high f: C1 ≈ short circuit.
• C2 (output coupling): Similar — at low f, XC2 is large, loading the output and reducing
effective signal to load.
• CE (emitter bypass): At mid/high f, CE ≈ short → RE bypassed → full gain AV = −RC/re. At
low f, CE has high XCE → RE partially unbypassed → gain decreases to AV =
−RC/(re+RE). CE dominates the low-frequency cutoff determination.
HIGH FREQUENCY EFFECTS (transistor junction capacitances):
• CBE and CBC: Internal transistor capacitances (BC107: CBE ≈ 7 pF, CBC ≈ 4 pF). At high f,
these have low XC → shunt the signal to ground → gain decreases.
• MILLER EFFECT: CBC appears at the input as CM = CBC(1+|AV|). For AV=−100: CM =
4pF×101 = 404 pF! This large effective capacitance severely limits high-frequency gain.

9.3.3 Mid-Band Voltage Gain

AV(mid) = −β × RC / hie = −gm × RC = −RC / re
where re = VT/IC ≈ 26/IC(mA) Ω and hie = β × re. All capacitors act as shorts; junction capacitances
act as opens.

9.4 Procedure
46. Connect circuit per diagram. VCC=10V.
47. Set input: VS=20mV peak-to-peak, f=1kHz from signal generator.
48. Connect CRO at output (across load, through C2).
49. KEEP INPUT AMPLITUDE CONSTANT (20mV). Change only FREQUENCY.
50. Vary f from 10Hz to 1MHz. At each frequency, measure output VO from CRO.
51. Calculate: Av = Vo/Vi and Gain(dB) = 20×log₁₀(Av).
52. Plot Gain(dB) vs Frequency (use log scale for frequency axis).
53. Draw horizontal line at [maximum gain − 3dB]. Find intersections → fL and fH.
54. Calculate BW = fH − fL.

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9.5 Observation Table (Vi = 20 mV)

[Link] Frequency (Hz) Vo (mV) Av = Vo/Vi Gain(dB) = 20log(Av)

1 10 Hz

2 50 Hz

3 100 Hz

4 500 Hz

5 1 kHz

6 5 kHz

7 10 kHz

8 50 kHz

9 100 kHz

10 500 kHz

11 1 MHz

9.6 Precautions
55. Keep input signal amplitude strictly constant (20mV) throughout. Use CRO to verify input.
56. Use log-scale for frequency axis when plotting Bode plot.
57. BC107 ratings must not be exceeded.
58. Verify correct polarity of electrolytic capacitors C1, C2, CE.

9.7 Viva Questions — Full Answers

Q: What is an amplifier?
An amplifier is an electronic circuit or device that increases the power, voltage, or current of an
input signal using energy drawn from a DC power supply (VCC or VDD). The input signal controls
the larger output signal, which is an amplified replica of the input. Key amplifier parameters: •
Voltage gain AV = VO/VI (ratio of output to input voltage) • Current gain AI = IO/II • Power gain
AP = PO/PI = AV × AI • Input impedance Zi (should be high → does not load source) • Output
impedance ZO (should be low → can drive loads) • Bandwidth BW (frequency range over which
gain is within 3 dB of maximum) • Noise figure (measure of amplifier-added noise) The CE BJT
amplifier and CS FET amplifier are the most common single-stage voltage amplifier topologies in
discrete electronics.
Q: Explain the effect of capacitors on frequency response.
THREE categories of capacitors affect CE amplifier frequency response:
1. INPUT COUPLING CAPACITOR C1 — LOW FREQUENCY: At very low f: XC1 = 1/(2πfC1) is
large. Voltage divider action: most input voltage drops across C1 → less signal reaches base →
gain drops. At mid/high f: XC1 ≈ 0 (short) → full signal to base.

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2. EMITTER BYPASS CAPACITOR CE — LOW FREQUENCY (DOMINANT): At mid/high f:

XCE ≈ 0 (short across RE) → RE bypassed → AC gain = −RC/re (maximum). At low f: XCE is
large → RE not fully bypassed → AC gain reduced to −RC/(re+RE) (much lower). CE typically
causes the most significant low-frequency gain reduction.
3. OUTPUT COUPLING CAPACITOR C2 — LOW FREQUENCY: At low f: XC2 large → output
loaded → gain decreases. At mid/high f: XC2 ≈ 0.
4. TRANSISTOR JUNCTION CAPACITANCES — HIGH FREQUENCY: CBE and CBC (internal
BJT capacitances) have low reactance at high f → shunt signal to ground. MILLER EFFECT:
CBC appears as CM = CBC(1+|AV|) at the input — much larger effective capacitance → severe
gain reduction at high f. Result: gain is constant in mid-band (all capacitors at their 'ideal'
values), falls at both low and high extremes.
Q: Why is gain constant in the mid-frequency region?
In the mid-frequency (mid-band) region, ALL capacitors are at their 'ideal' state simultaneously:
1. Coupling capacitors C1 and C2: XC is very low → they act as SHORT CIRCUITS → full signal
passes, no signal loss.
2. Bypass capacitor CE: XCE is very low → acts as SHORT CIRCUIT → RE fully bypassed →
maximum gain AV = −RC/re achieved.
3. Transistor junction capacitances (CBE, CBC, CGS, CGD): These are very small (pF range). At
mid-frequencies, their reactances XC = 1/(2πfC) are very HIGH → they act as OPEN CIRCUITS
→ no shunting of signal. Result: The gain is determined ONLY by the transistor's
transconductance (gm or β) and the circuit resistors: AV(mid) = −gm × RC = −β × RC / hie = −RC
/ re This value is constant throughout the mid-band because none of the capacitors are affecting
the gain.
Q: What is bandwidth?
Bandwidth (BW) is the range of frequencies over which the amplifier gain remains within 3 dB of
its maximum (mid-band) value: BW = fH − fL Where: fL = Lower 3-dB frequency (low-frequency
cutoff) — the frequency below which gain falls to 0.707 × AV(mid) fH = Upper 3-dB frequency
(high-frequency cutoff) — the frequency above which gain falls to 0.707 × AV(mid) The 3-dB
criterion: At the 3-dB points, power gain = 0.5 × max power gain, and voltage gain = (1/√2) × max
voltage gain = 0.707 × AV(mid). For RC-coupled amplifiers: fL is typically tens of Hz to a few kHz
(determined by coupling/bypass capacitors), and fH is typically tens of kHz to MHz (limited by
transistor junction capacitances). BW represents the 'useful' frequency range of the amplifier —
the range where it amplifies without significant distortion or attenuation.
Q: What is the relation between bandwidth and gain?
The Gain-Bandwidth Product (GBP) is approximately CONSTANT for a given transistor: GBP =
AV(mid) × BW ≈ fT (constant for a given transistor) Where fT is the transistor's unity-gain
bandwidth (transition frequency) — a device specification. Implications: • If you INCREASE gain
(e.g., by using larger RC), the bandwidth DECREASES proportionally. • If you DECREASE gain
(e.g., by NOT bypassing RE), the bandwidth INCREASES. • You CANNOT increase both gain
and bandwidth simultaneously without changing the transistor or using feedback techniques.
This is a fundamental trade-off in amplifier design known as the GAIN-BANDWIDTH TRADE-
OFF. For BC107: fT ≈ 150 MHz. If AV(mid) = 100 (40 dB): BW ≈ fT/AV = 150MHz/100 = 1.5
MHz. If AV(mid) = 10 (20 dB): BW ≈ 15 MHz (wider bandwidth at lower gain). Negative feedback
reduces gain but greatly extends bandwidth — used in operational amplifiers.

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9.8 MCQ Practice — Experiment 9: CE Amplifier Frequency Response

# Question & Options Answer Explanation

1 The voltage gain of a CE amplifier B) Internal At high f, CBE and CBC have low reactance
falls at HIGH frequencies due to: transistor and shunt signal to ground. CBC creates the
A) Coupling capacitors becoming junction Miller effect: effective input capacitance =
open capacitances CBC(1+|AV|), which is very large and severely
(Miller effect) loads the input at high frequency, causing
B) Internal transistor junction
gain rolloff.
capacitances (Miller effect)
C) Bypass capacitor short circuit
D) Power supply dropping

2 If mid-band gain = 46 dB, the 3-dB B) 43 dB 3-dB points are where gain = peak gain − 3
frequency points are where gain = dB = 46 − 3 = 43 dB. At this level, voltage
A) 23 dB gain = 0.707 × Av(peak) and power gain = 0.5
× Ap(peak). The frequency axis intersections
B) 43 dB
with the 43 dB line give fL and fH.
C) 49 dB
D) 3 dB

3 Bandwidth of an amplifier is: D) BW = fH − BW = fH − fL, where fH is the upper and fL is

A) BW = fH only fL the lower 3-dB frequency. Since typically
fH>>fL for RC-coupled amplifiers, BW ≈ fH.
B) BW = fL only
Bandwidth is the useful operating frequency
C) BW = fH + fL
range of the amplifier.
D) BW = fH − fL

4 The emitter bypass capacitor CE B) Bypasses CE shorts out RE for AC signals, giving AV =
in a CE amplifier: RE for AC to −RC/re (maximum). Without CE: AV =
A) Blocks DC from input maximise gain −RC/(re+RE) (much lower). CE does NOT
affect DC bias. For CE to be effective at a
B) Bypasses RE for AC to maximise
given frequency, XCE << RE: CE must be
gain
large enough for the operating frequency
C) Filters high-frequency noise range.
D) Sets the Q-point

5 The Gain-Bandwidth Product C) GBP = AV × BW ≈ fT (transition frequency), a

(GBP) for an amplifier is: Approximately fixed device parameter. Doubling the gain
A) Increases with gain constant for a halves the bandwidth. This fundamental trade-
given off cannot be overcome for a single transistor
B) Decreases with gain
transistor stage, though negative feedback and multi-
C) Approximately constant for a given stage designs can achieve both higher
transistor bandwidth and gain.
D) Independent of bandwidth

6 At the mid-band, the gain of a CE B) AV = −gm × With CE bypass capacitor present (shorts RE
amplifier is approximately: RC = −RC/re at mid-band): AV = −gm×RC = −RC/re =
A) AV = −RC/(re+RE) when CE −β×RC/hie. The negative sign = 180° phase
present inversion. re = VT/IC ≈ 26/IC(mA) Ω.
Example: IC=1mA, RC=4.7KΩ: AV =
B) AV = −gm × RC = −RC/re
−4700/26 ≈ −181.
C) AV = +β/RC
D) AV = RE/RC

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Experiment 10: Frequency Response of Common

Source FET Amplifier
10.1 Objectives
59. Obtain frequency response characteristics of a Common Source FET amplifier.
60. Determine bandwidth (BW = fH − fL).

10.2 Apparatus
[Link] Apparatus Type Range Qty
01 N-Channel JFET BFW10 — 01
02 Resistors Carbon 6.8KΩ (RD), 1MΩ (RG), 01 each
1.5KΩ (RS)
03 Regulated Power Supply DC 0–30V (VDD=12V) 01
04 Capacitors Mixed 0.1μF (×2 coupling), 03
47μF (bypass CS)
05 Signal Generator AF 10Hz–1MHz 01
06 CRO with Probes Dual trace — 01
07 Breadboard and Wires — — As reqd

10.3 Theory
10.3.1 CS Amplifier Circuit (VDD=12V)

Component Values and Functions

RD = 6.8 KΩ → Drain resistor (output voltage developed across RD)
RG = 1 MΩ → Gate bias resistor (holds gate at DC ground; input Z ≈ RG = 1 MΩ)
RS = 1.5 KΩ → Source resistor (self-bias: VGS = −ID×RS; DC stabilisation)
CGin = 0.1 μF → Input coupling capacitor (blocks DC, couples signal to gate)
CGout = 0.1 μF→ Output coupling capacitor (blocks DC, couples drain output to load)
CS = 47 μF → Source bypass capacitor (shorts RS for AC; maximises AC gain)

10.3.2 Voltage Gain of CS Amplifier

AV = −gm × RD (with CS bypassing RS for AC)
The negative sign indicates 180° phase inversion. Without CS: AV = −gm×RD/(1+gm×RS) —
significantly lower gain. CS bypass capacitor is essential for maximum gain in the mid-band.

10.3.3 Why CS has Higher Input Impedance than CE

CS input impedance Zi ≈ RG = 1 MΩ (because JFET gate draws no current, so gate resistor RG is
the only path for input signal). CE input impedance Zi = R1||R2||hie ≈ a few KΩ (limited by bias

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resistors and BJT base resistance hie). FET's zero gate current makes RG the sole determinant of
input Z — simply choose a large RG (1 MΩ typical).

10.4 Procedure
61. Connect CS FET amplifier circuit per diagram. VDD=12V.
62. Set signal generator: VS=20mV, f=1kHz. Connect to input.
63. Connect CRO at output (drain side of CGout). Verify phase inversion (180°).
64. Keep input amplitude constant (20mV). Vary frequency from 10Hz to 1MHz.
65. At each frequency, measure VO from CRO. Calculate Av and Gain(dB).
66. Plot Gain(dB) vs frequency (log scale). Determine fL, fH, BW from 3-dB points.

10.5 CS vs CE Comparison
Parameter CE (BJT) Amplifier CS (FET) Amplifier

Voltage Gain High (−β×RC/hie, up to 200+) Moderate (−gm×RD, typically 5–50)

Input Impedance Few KΩ (limited by hie& bias R) Very high (≈RG = 1 MΩ)

Noise Figure Higher (minority carriers) Lower (majority carriers only)

Phase Inversion Yes (180°) Yes (180°)

Thermal Stability Less stable More stable (self-stabilising gm)

Biasing Voltage divider (R1, R2, RE) Self-bias (RG, RS, CS)

Low Freq. fL Set by C1, CE, C2 Set by coupling caps, CS

High Freq. fH CBE, CBC (Miller effect) CGS, CGD (Miller effect)

10.6 Viva Questions — Full Answers

Q: What is an amplifier?
An amplifier is an electronic circuit that increases the amplitude (voltage, current, or power) of a
weak input signal, using energy supplied by a DC power source (VCC/VDD). The key
specifications are: Voltage gain AV = VO/VI (can be up to hundreds or thousands), Input
impedance Zi (high Zi avoids loading the signal source), Output impedance ZO (low ZO for
maximum power transfer to load), Bandwidth (range of frequencies over which gain is usable),
and Noise figure (amplifier-added noise). The CS JFET amplifier is particularly valued for its
extremely high input impedance (≈1 MΩ) and low noise, making it ideal for the input stage of
sensitive measurement equipment, audio preamplifiers, and radio receivers.
Q: Explain the effect of capacitors on frequency response (CS amplifier).
The CS amplifier has three capacitors that affect frequency response:
1. INPUT COUPLING CAPACITOR (0.1 μF) — LOW FREQUENCY EFFECT: At low f: XC =
1/(2π×f×0.1μF) is large → signal voltage divides between XC and gate resistor → less signal at
gate → gain drops. At mid/high f: XC ≈ 0 (short) → full signal to gate.
2. SOURCE BYPASS CAPACITOR CS (47 μF) — LOW FREQUENCY EFFECT (most
significant): At mid/high f: XCS << RS → CS shorts RS for AC → VGS = Vin → full
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transconductance action → AV = −gm×RD (maximum). At low f: XCS is large → RS not

bypassed → signal reduced by source degeneration → AV = −gm×RD/(1+gm×RS) (lower gain).
3. OUTPUT COUPLING CAPACITOR (0.1 μF) — LOW FREQUENCY EFFECT: At low f: XC
large → output loading → gain reduces. At mid/high f: XC ≈ 0.
4. TRANSISTOR CAPACITANCES (CGS, CGD) — HIGH FREQUENCY EFFECT: At high f:
CGS and CGD (few pF each) have low XC → shunt signal to ground. CGD causes Miller effect:
effective input C = CGD(1+|gm×RD|) → limits high-frequency response.
Q: Why is gain constant in the mid-frequency region?
In the mid-frequency region of the CS amplifier:
1. Coupling capacitors (0.1 μF): XC << RG (1 MΩ) → effectively short circuits → full signal from
source to gate, and from drain to load.
2. Source bypass capacitor CS (47 μF): XCS << RS → effectively short circuit → RS is fully
bypassed for AC → maximum gain AV = −gm×RD.
3. Transistor capacitances CGS and CGD (few pF): At mid-band frequencies (kHz range),
reactance 1/(2πf×CGS) >> RG → capacitances are effectively open → do not shunt the signal.
With all capacitors at their ideal states (coupling = shorts, transistor C = opens), the gain is set
purely by gm and RD: AV(mid) = −gm × RD This is constant over the mid-band since gm and RD
are fixed by the bias point and component values.
Q: What is bandwidth?
Bandwidth (BW) of the CS FET amplifier is the range of frequencies over which the voltage gain
remains within 3 dB of its mid-band maximum: BW = fH − fLfL (lower 3-dB frequency): typically a
few Hz to tens of Hz for a CS amplifier with 47 μF bypass cap and 0.1 μF coupling caps (the
large capacitors extend fL to low values).fH (upper 3-dB frequency): typically tens of kHz to MHz,
limited by FET internal capacitances CGS and CGD (and Miller effect of CGD). The CS FET
amplifier typically has a WIDER bandwidth than a CE BJT amplifier for the same gain, because: •
FET gm values are typically lower than BJT gm → lower gain → wider bandwidth (GBP trade-off)
• Miller effect is less severe (smaller effective input capacitance) because the gain is lower
Q: What is the relation between bandwidth and gain?
For the CS FET amplifier, the Gain-Bandwidth Product (GBP) is approximately constant — a
fundamental property related to the FET's transition frequency fT: GBP = |AV(mid)| × BW ≈ fT
For the BFW10 JFET, fT is typically a few hundred MHz. Key implications: • Increasing RD →
higher gain (AV = −gm×RD) → narrower bandwidth. More gain = less bandwidth. • Decreasing
RD → lower gain → wider bandwidth. • Source resistance RS (without CS bypass) reduces gain
but increases bandwidth. Comparison with CE amplifier: • CE BJT: Higher gain
(β×RC/hie>>gm×RD typically) but narrower bandwidth (Miller effect more severe). • CS FET:
Lower gain but wider bandwidth — better gain-bandwidth trade-off in some high-frequency
applications. Negative feedback (source degeneration, not bypassing RS) reduces gain but
extends bandwidth significantly — useful in wideband amplifier design.

10.7 MCQ Practice — Experiment 10: CS FET Amplifier

# Question & Options Answer Explanation

1 Mid-band voltage gain of a CS FET B) AV = −gm AV = −gm × RD. The negative sign indicates
× RD 180° phase inversion (same as CE). gm is the

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amplifier (CS bypass present) is: JFET transconductance (A/V) and RD is the
A) AV = β × RD drain resistor. With CS bypass cap, RS is AC
shorted, eliminating source degeneration and
B) AV = −gm × RD
giving maximum gain.
C) AV = −gm × RS
D) AV = RD/RS

2 Input impedance of CS FET C) Gate bias JFET gate current ≈ 0 → intrinsic gate
amplifier is primarily set by: resistor RG impedance is essentially infinite (GΩ). The
A) Gate-source capacitance CGS input impedance is limited by the external gate
bias resistor RG = 1 MΩ. This is why FET
B) Transconductance gm
amplifiers have very high Zi ≈ RG = 1 MΩ,
C) Gate bias resistor RG compared to CE'shie ≈ 1–10 KΩ.
D) Drain resistor RD

3 Compared to CE BJT amplifier, CS C) Lower FET advantages: (1) Higher Zi ≈ 1 MΩ vs CE's

FET amplifier has: noise and few KΩ. (2) Lower noise: FET is unipolar (no
A) Lower input impedance much higher minority carrier noise). CE typically has higher
input gain (β×RC/hie>gm×RD for same bias
B) Higher noise
impedance current), so there is a gain-vs-impedance/noise
C) Lower noise and much higher input trade-off between CE and CS.
impedance
D) Higher gain

4 Source bypass capacitor CS (47 B) Short- CS provides a low-impedance path across RS

μF) in CS amplifier serves to: circuit RS for for AC signals. Without CS: AV =
A) Block DC from reaching the gate AC to −gm×RD/(1+gm×RS) — source degeneration
maximise reduces gain. With CS (XCS << RS at mid-
B) Short-circuit RS for AC to maximise
gain band): RS is shorted → AV = −gm×RD
gain
(maximum). CS does not affect DC bias (RS
C) Filter drain supply ripple remains for self-bias DC operation).
D) Set the self-bias Q-point

5 Self-bias of N-channel JFET uses B) ID flows Self-bias mechanism: VG = 0 (through RG to

RS to create a negative VGS through RS ground). VS = ID×RS (positive, since ID flows
because: creating VS down through RS from source to ground). VGS
= ID×RS, and = VG − VS = 0 − ID×RS = −ID×RS < 0. This
A) VDD is negative
VG=0 → VGS automatically provides the required negative
B) ID flows through RS creating VS =
= −ID×RS VGS for N-channel JFET — no separate
ID×RS, and VG=0 → VGS = −ID×RS
negative supply needed.
C) The gate is connected to negative
supply
D) RS reduces drain current to zero

6 The high-frequency gain rolloff in C) FET At high f, CGS and CGD (few pF each) have
a CS FET amplifier is caused by: internal low reactance → shunt signal to ground. CGD
A) Source bypass capacitor capacitances (gate-drain capacitance) is multiplied by the
CGS and Miller effect: effective CM = CGD(1+gm×RD) at
B) Input coupling capacitor
CGD (Miller the input. This large effective capacitance limits
C) FET internal capacitances CGS and the high-frequency response. Analogous to
CGD (Miller effect of CGD) effect of
CGD) CBC in CE amplifier causing Miller effect.
D) Drain resistor RD

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Quick Reference: Parts 2 & 3 — All Key Formulas

Parameter Formula / Value Notes

BJT current law IE = IC + IB Always valid; fundamental

CB current gain α α = IC/IE = hfb 0.95–0.999; < 1

CE current gain β β = IC/IB = hfe 50–300; >> 1

α–β relation β = α/(1−α) α = β/(1+β)

CE input impedance hie = β × re = β × VT/IC Also hie = VT / IB

CE voltage gain AV = −β×RC/hie = −RC/re With CE bypass; phase inversion

Small signal re re = VT / IC ≈ 26/IC(mA) Ω For Si at 25°C

JFET Shockley eqn ID = IDSS(1−VGS/VP)² VP≤VGS≤0 for N-ch

JFET drain resistance rd = ΔVDS/ΔID | VGS=const From drain characteristics

JFET transconductance gm = ΔID/ΔVGS | VDS=const Siemens; from transfer char.

JFET amplif. factor μ = rd × gm = ΔVDS/ΔVGS Open-circuit voltage gain

CS amplifier gain AV = −gm × RD With CS bypass; phase inversion

Gain in dB Gain(dB) = 20×log₁₀(Vo/Vi) Use log scale for f axis

Bandwidth BW = fH − fL BW ≈ fH when fH>>fL

Gain-BW product GBP = AV × BW ≈ fT Constant; fundamental limit

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