EE-320: Electronics-I
Tutorial on Module-1 and 2
Dr Sharif, Sheikh
Engineering and Technology
Ref: Textbook
Problem 1: Use the constant voltage drop model of real Si diodes:
1(a) Use the constant voltage drop model
of the silicon diodes to find the
current flowing through resistor ‘R’
1(b) What type of basic logic gate can be
constructed using this circuit?
2(a) Use the constant voltage drop model
of the silicon diodes to find the
current flowing through resistor ‘R’
2
AND/OR GATES with real diodes:
• The analysis of AND/OR gates is made easier by using the approximate
equivalent for a diode rather than the ideal because we can stipulate
that the voltage across the diode must be 0.7 V positive for the silicon
diode to switch to the “on” state.
3
AND/OR GATES with real diodes
4
Problem 2:
Q1. Use constant voltage drop model of the
silicon diode to find VD, VR, and ID.
Solution:
5
Summary of Rectifier Circuits (updated):
• In the center tapped transformer rectifier circuit, the peak AC
voltage is the transformer secondary voltage to the tap.
Rectifier PIV Approximate Approximate values Realistic values
values (with higher %) (with improved % error)
See slides 19-21 for derivation
Half Wave V0_dc= (1/ ) {vs}p - VD0
(vs)p (v0)p (vs)p - VD0 V0_dc= (1/ ) {v0}p ;
Rectifier as diode only conducts half cycle
Center-Tapped
Transformer 2(vs)p (v0)p= (vs)p - VD0 V0_DC = (2/ ) [v0]p ; V0_dc= (2/ ) {vs}p - VD0
Rectifier
Bridge Rectifier (vs)p - VD0 (v0)p = {(vs)p - 2VD0 } V0_DC = (2 / ) [v0]p ; V0_dc= (2/ ) {vs}p - 2VD0
• (vs)p = the peak AC secondary input voltage See slides 19-21 for derivation of V0_dc
• (v0)p = the peak AC output/load voltage
• (v0)0_DC = the average or DC output/load voltage 6
Summary of Rectifier Circuits (updated):
• In the center tapped transformer rectifier circuit, the peak AC
voltage is the transformer secondary voltage to the tap.
Rectifier PIV Approximate Approximate values Realistic values
values (with higher %) (with improved % error)
See slides 19-21 for derivation
Half Wave V0_dc= (1/ ) {vs}p - VD0
(vs)p (v0)p (vs)p - VD0 V0_dc= (1/ ) {v0}p ;
Rectifier as diode only conducts half cycle
Center-Tapped
Transformer 2(vs)p (v0)p= (vs)p - VD0 V0_DC = (2/ ) [v0]p ; V0_dc= (2/ ) {vs}p - VD0
Rectifier
Bridge Rectifier (vs)p - VD0 (v0)p = {(vs)p - 2VD0 } V0_DC = (2 / ) [v0]p ; V0_dc= (2/ ) {vs}p - 2VD0
• (vs)p = the peak AC secondary input voltage See slides 19-21 for derivation of V0_dc
• (v0)p = the peak AC output/load voltage
• (v0)0_DC = the average or DC output/load voltage 7
Problem 3: Design a Regulated DC Power supply (pg-1)
A center-tip full-wave rectifier with regulated output voltage is shown in the figure.
Assume the following the calculate the required parameters.
• Transformer has 5:1 turns ratio with primary connected to 120V (60 Hz).
• Rectifier diodes (IN4007) have forward drop 0.7 V, and negligible rZ and PIV=1000V
• Smoothing capacitor C=100 µF and a series resistor RS
• Zener diode (1N4733A has rZ = 7 Ω, VZ = 5.1 v, PZ,max = 1 watt.
• Load: RL = 2.2 kΩ nominal (≈ 5 mA), but your design should hold regulation up to
IL,max = 20 mA. Also to maintain regulation, keep IZ ≥ IZ,min = 5 mA at worst case of
low line (lowest available VS-out) with full load (IL = ILmax)
8
Problem 3: Design a C.T Regulated DC Power supply (pg-2)
Tasks for students:
1) Estimate the peak voltages at the output of the C.T. transformer (VS-out).
2) Calculate the peak to peak ripple voltage (VR)
3) Choose the series resistor RS to ensure IZ ≥ IZ,min at VS-out,minimum with IL = IL,max.
3) Check IZ and Zener power at 𝑽𝒔−𝒐𝒖𝒕,𝒎𝒊𝒏𝒊𝒎𝒖𝒎 with IL,min = 5 mA, and check the
resistor power.
4) Calculate the power ratings for the Zener diode and check if the diode is operating
safely. Also find the power rating needed for RS for safe operation.
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Problem 3: Design a C.T Regulated DC Power supply (3)
Solution:
(1). Peak voltage in the primary side of the transformer:
𝑉𝑃,𝑝𝑒𝑎𝑘 = 𝑉𝑅𝑀𝑆 × 2 = 169.7 𝑣
Peak voltage in the secondary of the C.T transformer:
1 𝑁𝑆
𝑉𝑆,𝑝𝑒𝑎𝑘 = 𝑉𝑃,𝑝𝑒𝑎𝑘 × = 16.97 𝑣
2 𝑁𝑃
Peak voltage output of the C.T. transformer is:
𝑉𝑆−𝑜𝑢𝑡,𝑝𝑒𝑎𝑘 = 16.97 − 𝑉𝐷 = 16.97 − 0.7 = 16.27 𝑣 = 16.3 𝑣
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Problem 3: Design a C.T Regulated DC Power supply (4)
(2). For given values of IZ = IZ,min = 5mA at VR,min with IL = IL,max = 20 mA.
The Ripple (𝑉𝑅 ) at 120 Hz (Note for full wave rectifier, fr=2*fsource) as with
worst-case current I = IL,max + IZ,min:
𝑉𝑠−𝑜𝑢𝑡,𝑝𝑒𝑎𝑘 I
𝑉𝑅 = 𝛥𝑉𝑅 = =
𝑓𝑟 𝐶 𝑅 𝑓𝑟 𝐶
Using I = IZ,min+IL,max= 25 mA, fr = 120 Hz, C = 100 µF
gives p-p ripple, VR ≈ 2.08 V
Thus, the minimum input to the regulator is:
𝑉𝑠−𝑜𝑢𝑡,𝑚𝑖𝑛𝑖𝑚𝑢𝑚 = 𝑉𝑠−𝑜𝑢𝑡,𝑝𝑒𝑎𝑘 − 𝑉𝑅 ≈ 16.3 − 2.08 = 14.22 𝑉
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Problem 3: Design a C.T Regulated DC Power supply (5)
(3) Series resistor chosen so IZ ≥ IZ,min at VS-out,minimum with IL = IL,max:
𝑉𝑠−𝑜𝑢𝑡,𝑚𝑖𝑛𝑖𝑚𝑢𝑚 − 𝑉𝑍 14.22 − 5.1
𝑅𝑆 = = ≈ 365 𝛺
𝐼𝐿,𝑚𝑎𝑥 + 𝐼𝑍,𝑚𝑖𝑛 0.020 + 0.005
(4) Currents at the high-line or light-load corner (𝑉𝑠−𝑜𝑢𝑡 = 𝑉𝑠−𝑜𝑢𝑡,𝑝𝑒𝑎𝑘 , IL = ILmin = 5 mA):
𝑉𝑠−𝑜𝑢𝑡,𝑝𝑒𝑎𝑘 −𝑉𝑍 16.3−5.1
𝐼𝑅 = ≈ ≈ 0.0311 𝐴 and 𝐼𝑍 = 𝐼𝑅 − 𝐼𝐿 ≈ 0.0311 − 0.005 = 0.0261 𝐴
𝑅 360
Zener diode power checks: 𝑃𝑍 = 𝑉𝑍 𝐼𝑍 ≈ 5.1 × 0.0261 = 0.133 𝑊
Due to light-load IL 0, So, IRs IZ. So the power absorbed by RS is: 𝑃𝑅 = 𝐼𝑅𝑠 2 𝑅𝑆
𝑃𝑅 ≈ (0.0311)^2 · 360 ≈ 0.35 𝑊
With these values the Zener is operating well below given Zener power rating of 1 W.
Also the safe power rating for and Rs is 0.5 or 1 watt.
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Problem 3: Design a C.T Regulated DC Power supply (6)
Both Line vs. Load Regulation are at
work in this design.
Load regulation: The Zener shunt maintains the output voltage near VZ as the load
current varies between its minimum and maximum values. When the load current
increases, the Zener current decreases; when the load current decreases, the Zener
current increases. This current sharing keeps the output voltage approximately constant
over specified load range.
Line regulation: The design also tolerates input (line) variation from the rectifier stage.
The sizing uses the lowest expected rectifier valley voltage to guarantee regulation at
low line and checks the high-line/light-load corner to ensure the Zener current and
power remain within limits. Variations in input voltage are absorbed mainly by changes
in the Zener current, keeping the output voltage close to VZ. 13
Problem 4: Design a Bridge Regulated DC Power supply (1)
Design the voltage regulator shown in the Figure below to maintain a fixed output voltage
of 8v across a variable load (RL) when the source is VS-peak = 17.4v, VD = 0.7v, VZ = 8
V, 𝑅𝑆 = 400 Ω and the Zener current 𝐼𝑍𝑀𝑎𝑥 = 15 mA and 𝐼𝑍𝑚𝑖𝑛 0 mA (at the knee).
That is, determine:
(a) Proper range of the load resistor (RL) and the proper range of the load current (IL).
(b) Maximum wattage rating of the diode.
14
Problem 4: Design a Bridge Regulated DC Power supply (2)
Solution:
(a) VS-out = VS-peak - 2VD = 17.4 – 2(0.7) = 16 v
Current IS through the series resistor RS can be calculated as:
𝑉𝑆 − 𝑉𝑍 16 − 8
𝐼𝑆 = = = 0.02 𝐴 = 20 𝑚𝐴
𝑅𝑆 400
Current split: 𝐼𝑆 = 𝐼𝐿 + 𝐼𝑍
and IL=IL,max occurs when IZ=IZmin≈ 0 mA (at the knee),
So IL,max = IS = 20 mA.
Again, IL= IL,min occurs when IZ = IZMax,
So IL,min = IS − IZMax = 20 mA − 15 mA = 5 mA.
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Problem 4: Design a Bridge Regulated DC Power supply (3)
With VL = VZ in regulation:
𝑉𝑍 8
𝑅𝐿𝑚𝑖𝑛 = = = 400 Ω and
𝐼𝐿𝑚𝑎𝑥 20 mA
𝑉𝑍 8
𝑅𝐿𝑀𝑎𝑥 = = = 1600 Ω
𝐼𝐿𝑚𝑖𝑛 5 mA
(b) Diode power (worst case at IZ = IZMax): 𝑃𝑍 = 𝑉𝑍 × 𝐼𝑍𝑀𝑎𝑥
= 8 × 15 𝑚𝐴 = 0.12 𝑤
So we can safely select at least a 0.25 W as diode rating to satisfy safely margin.
This problem implements a Load regulation. It wants to keep 𝑉𝑂 = 8 V , while 𝑅𝐿 and
thus 𝐼𝐿 varie(. The solution computes the allowable 𝑅𝐿 𝑎𝑛𝑑 𝐼𝐿 range and Zener diode
power rating with a fixed input derived from 𝑉𝑆−peak That is classic load regulation, as
line isn’t varied here (no low-line/high-line check) 16