Great! Below are the VTU-style, lengthy answers for BCS402 – All 28 Ques ons.

These are
detailed and structured to fetch full 10 marks each, with clear headings, points, and
explana ons as per university expecta ons.

1. Differen ate between i) RISC & CISC architecture ii) Microcontroller & Microprocessor

i) RISC (Reduced Instruc on Set Computer):

 Simplified instruc ons: Only a few instruc ons are available, designed to execute in
one clock cycle.

 Fixed-length instruc ons: Easier to decode and pipeline.

 Load/Store architecture: Only load and store instruc ons access memory.

 Registers oriented: Heavy use of registers for opera ons.

 Simple hardware: Easier implementa on and debugging.

 Examples: ARM, MIPS, SPARC.

CISC (Complex Instruc on Set Computer):

 Large instruc on set: Many instruc ons, each capable of execu ng complex tasks.

 Variable-length instruc ons: Difficult to pipeline.

 Memory-to-memory opera ons: Instruc ons can directly access memory.

 Fewer lines of code: Due to powerful single instruc ons.

 Complex hardware: Requires microprogramming.

 Examples: Intel x86, VAX.

ii) Microcontroller:

 Defini on: A compact integrated chip with CPU, RAM, ROM, and I/O peripherals.

 Used in: Embedded systems, IoT devices, home automa on, etc.

 Power efficient: Operates on low voltage.

 Memory: In-built flash and RAM.

 Example: 8051, AVR, ARM Cortex-M3.

Microprocessor:

 Defini on: A compu ng engine (CPU) that requires external components like RAM,
ROM, I/O.
  Used in: Desktops, Laptops, Servers.

 More powerful: Handles heavy computa on.

 Power-hungry: Requires proper cooling.

 Example: Intel i7, AMD Ryzen.

2. Explain ARM registers used under various modes and ARM philosophy.

ARM Register Set:

 ARM uses 37 registers out of which 31 are general-purpose and 6 are status
registers.

 User Mode: R0–R15, CPSR

 FIQ Mode: Addi onal R8_fiq to R14_fiq, SPSR_fiq

 IRQ Mode: R13_irq, R14_irq, SPSR_irq

 Supervisor (SVC) Mode: R13_svc, R14_svc, SPSR_svc

 Abort/Undefined Mode: Have banked R13, R14 and corresponding SPSR.

ARM Philosophy:

1. Load/store architecture: Only LDR/STR access memory.

2. Orthogonality: Any instruc on can use any register.

3. Condi onal Execu on: Almost all instruc ons can be condi onally executed.

4. Efficient pipelining: Due to uniform instruc on length.

5. Low power: Designed for embedded and mobile environments.

6. Simplicity: Easier compiler genera on and efficient execu on.

3. What is pipelining? Illustrate it with an example.

Defini on:

Pipelining is a technique in which mul ple instruc on phases are overlapped to improve
performance.

ARM 3-stage Pipeline:

1. Fetch: Instruc on is fetched from memory.

2. Decode: Instruc on is decoded to understand what to perform.

 3. Execute: Instruc on is executed and result is wri en.

Example:

Cycle Fetch Decode Execute

1 Instruc on 1 - -

2 Instruc on 2 Instruc on 1 -

3 Instruc on 3 Instruc on 2 Instruc on 1

4 Instruc on 4 Instruc on 3 Instruc on 2

 This overlaps execu on and increases throughput.

 Effec ve instruc on execu on rate: 1 instruc on per cycle.

4. Explain the architecture of a typical embedded system based on ARM.

Block Diagram Components:

1. ARM Processor Core: The central unit performing computa on and control.

2. ROM/Flash Memory: Stores permanent code.

3. RAM: Temporary data storage.

4. Timers/Counters: For me-cri cal opera ons.

5. I/O Ports: Communicates with external devices.

6. Communica on Modules: UART, SPI, I2C for serial communica on.

7. ADC/DAC: Convert signals from analog to digital and vice versa.

8. Power Supply: Regulated supply to the board.

Features:

 Compact, cost-effec ve.

 Designed for a specific task.

 Real- me performance.

 Power efficiency.

 Examples: Digital camera, Microwave, Smartwatch.

5. Discuss with diagram: i) Von Neumann architecture with cache ii) Harvard architecture
with TCM

i) Von Neumann Architecture:

 Shared bus for data and instruc ons.

 Single memory for both code and data.

 Limita on: Von Neumann bo leneck (can’t fetch data & instruc on simultaneously).

 Use of cache memory improves performance.

 Simpler design and cheaper.

ii) Harvard Architecture with TCM (Tightly Coupled Memory):

 Separate buses and memory for data and instruc ons.

 Simultaneous access improves performance.

 TCM: Special fast-access memory for real- me use.

 Suitable for embedded systems with determinis c ming.

Diagram:

 Show both architectures with labeled buses, CPU, memory, and TCM.

Let me now con nue with ques ons 6 to 10. Stay tuned – this will be a long text but worth
saving and studying.

Perfect — I’ll now con nue with detailed VTU-style 10-mark answers, fully expanded and
structured. Below are the answers for Ques ons 6 to 10, wri en to meet full mark
expecta ons.

6. Explain the ARM architecture with a neat diagram.

Introduc on:

ARM (Advanced RISC Machine) is a 32-bit load/store RISC-based processor architecture

designed for low power consump on and high performance. It is widely used in embedded
systems and mobile devices.

Key Features of ARM Architecture:

 RISC (Reduced Instruc on Set Computer) based

 Load/store architecture (only LDR/STR access memory)

  Uniform and fixed-length instruc ons (32-bit or 16-bit in Thumb)

 Condi onal execu on for all instruc ons

 3-stage pipeline (Fetch, Decode, Execute)

 Mul ple opera ng modes (User, FIQ, IRQ, Supervisor, Abort, Undefined, System)

 Register bank with 16 general-purpose registers (R0–R15)

 Program Counter (R15), Link Register (R14), Stack Pointer (R13)

 Status Registers: CPSR and SPSRs (Saved Program Status Registers)

Block Diagram Descrip on:

Labelled Diagram Should Include:

1. Register File (R0–R15)

2. ALU (Arithme c Logic Unit)

3. Barrel Shi er

4. Instruc on Decoder

5. Data Bus and Address Bus

6. Cache (op onal)

7. Instruc on Pipeline Stages

Func onal Units:

 Register File: Stores temporary data and results.

 ALU: Performs arithme c and logical opera ons.

 Barrel Shi er: Performs shi and rotate opera ons in a single cycle.

 Decoder: Decodes instruc ons and generates control signals.

 Pipeline: Increases instruc on throughput.

 Control Logic: Manages instruc on flow and pipeline stages.

Conclusion:

ARM architecture is known for its efficient pipeline, low power opera on, and simple
instruc on set, making it ideal for embedded applica ons.

7. Explain the modes of opera on of ARM with its registers and their func ons.
ARM Opera ng Modes:

ARM has 7 dis nct modes of opera on, each tailored for specific tasks. Modes affect the
availability of certain registers and the type of excep ons handled.

Mode Descrip on

User Normal execu on mode (non-privileged)

FIQ Fast interrupt handling

IRQ Normal interrupt handling

Supervisor OS kernel mode (a er reset)

Abort Memory access viola on handling

Undefined Handling undefined instruc ons

System Privileged user mode

Register Structure:

 Total registers: 37

o 31 General Purpose

o 6 Status Registers (CPSR + 5 SPSRs)

Common Registers:

 R0–R12: General purpose

 R13: Stack Pointer (SP)

 R14: Link Register (LR)

 R15: Program Counter (PC)

 CPSR: Current Program Status Register

Banked Registers:

 FIQ Mode: R8_fiq to R14_fiq, SPSR_fiq

 IRQ Mode: R13_irq, R14_irq, SPSR_irq

 SVC Mode: R13_svc, R14_svc, SPSR_svc

 Abort/Undefined: Have their own SP, LR, and SPSR

Purpose of Status Registers:

  CPSR: Holds flags (N, Z, C, V), interrupt enable bits, processor mode.

 SPSR: Stores CPSR when excep on occurs.

Conclusion:

ARM modes enhance its flexibility in handling excep ons and tasks. Mode-specific registers
improve interrupt handling efficiency and system robustness.

8. List and explain various ARM instruc on types.

ARM has a powerful instruc on set that is uniform and easy to decode. Instruc ons fall into
several categories:

1. Data Processing Instruc ons:

 Used for arithme c and logical opera ons.

 Example: ADD R0, R1, R2 → R0 = R1 + R2

 Other examples: SUB, AND, ORR, EOR, MOV, CMP, etc.

2. Data Transfer Instruc ons:

 Used for memory access (Load/Store).

 Example: LDR R0, [R1] → Load content at address in R1 into R0.

 STR R0, [R1] stores R0 content to address in R1.

3. Control Flow Instruc ons:

 Alters the sequence of execu on.

 B label: Uncondi onal branch

 BL label: Branch with link (stores return address in R14)

 BX Rn: Branch to address in Rn

4. Program Status Register Transfer:

 Used to read/write CPSR/SPSR.

 MRS Rd, CPSR: Move status to Rd

 MSR CPSR, Rm: Update CPSR from Rm

5. Load/Store Mul ple:

 Transfers mul ple registers at once.

 LDMIA R0!, {R1-R4}

  STMFD SP!, {R0-R3, LR}

6. So ware Interrupt (SWI):

 Generates excep on and switches to supervisor mode.

 SWI #0

7. Condi onal Execu on:

 All instruc ons can have condi on codes like EQ, NE, GT, LT, etc.

 Example: MOVEQ R0, #1 (executes only if Zero flag is set)

Conclusion:

ARM’s instruc on set is highly orthogonal and efficient. It ensures low memory usage, easy
decoding, and faster execu on.

9. Explain the concept of barrel shi er in ARM processor.

Introduc on:

The Barrel Shi er in ARM is a special hardware block that performs shi and rotate
opera ons during instruc on execu on.

Role of Barrel Shi er:

 Integrated with ALU

 Can shi /rotate an operand before it enters ALU

 Saves extra instruc on cycles

 Commonly used with data processing instruc ons

Types of Shi Opera ons:

1. Logical Shi Le (LSL): Shi s bits le , fills with 0

o Example: LSL R0, R1, #2

2. Logical Shi Right (LSR): Shi s bits right, fills with 0

3. Arithme c Shi Right (ASR): Fills MSB with sign bit

4. Rotate Right (ROR): Rotates bits to the right

5. Rotate Right Extended (RRX): Rotates with carry

Example:

ADD R0, R1, R2, LSL #2

  R2 is shi ed le by 2 bits (R2 × 4)

 Result is added to R1

Advantages:

 Performs shi /rotate inline with ALU opera ons

 Reduces need for mul ple instruc ons

 Enhances performance and reduces code size

Conclusion:

The barrel shi er enhances the ARM processor’s performance by allowing combined
opera ons like shi and add in a single instruc on cycle.

10. Describe the PSR (Program Status Register) and its func ons in ARM.

Types of Program Status Registers:

1. CPSR (Current Program Status Register):

o Holds flags and processor status.

o Present in all modes.

2. SPSR (Saved Program Status Register):

o Saves the CPSR during excep on handling.

o Only available in privileged modes (not User mode).

CPSR Structure (32-bits):

Bits Field Descrip on

31 N (Nega ve) Result is nega ve

30 Z (Zero) Result is zero

29 C (Carry) Carry occurred

28 V (Overflow) Overflow occurred

27-8 Reserved -

7 I (IRQ disable) Disables IRQ

6 F (FIQ disable) Disables FIQ

Bits Field Descrip on

5 T (Thumb state) 1 = Thumb, 0 = ARM mode

4-0 Mode bits Current processor mode

Instruc ons for Access:

 MRS R0, CPSR – Move CPSR to R0

 MSR CPSR, R0 – Update CPSR from R0

Func on of PSR:

 Reflects result of arithme c/logical opera ons

 Controls processor mode (User, SVC, IRQ, etc.)

 Enables/disables interrupts

 Determines instruc on set (ARM/Thumb)

SPSR Use Case:

 On excep on, CPSR is copied to SPSR.

 When returning (MOVS PC, LR), SPSR is copied back to CPSR.

Conclusion:

The PSRs (especially CPSR) are cri cal in ARM for managing system behavior, handling
interrupts, and ensuring proper mode control.

I will now con nue with Ques ons 11 to 15 in the next response. Would you like me to
proceed immediately or pause for a moment to let you review this part?

Great! Let's proceed with VTU-style 10-mark answers for Ques ons 11 to 15 of BCS402.
These are wri en in a fully detailed manner to ensure maximum score in exams.

11. Explain the Thumb instruc on set of ARM.

Introduc on:

The Thumb instruc on set is a compressed 16-bit version of the ARM instruc on set. It was
introduced to improve code density and performance in memory-constrained systems like
embedded devices.
Key Features:

 16-bit instruc ons instead of 32-bit.

 Improved code density (30–40% smaller).

 Same register set as ARM (R0–R15).

 Trade-off: Fewer instruc ons and more cycles in some opera ons.

 Conversion between ARM and Thumb via BX instruc on.

 Thumb mode is selected via T-bit in CPSR.

Thumb Instruc on Categories:

1. Data Movement:

o MOV Rd, #imm → Move immediate

o LDR Rd, [Rn, #offset] → Load data from memory

2. Arithme c & Logic:

o ADD Rd, Rn, Rm

o SUB Rd, Rn, #imm

3. Compare & Branch:

o CMP Rn, #imm

o B label, BL label (branch with link)

4. Stack Instruc ons:

o PUSH {R4-R7, LR}

o POP {R4-R7, PC}

5. Special Instruc ons:

o BX Rm: Branch and switch between ARM/Thumb

Advantages of Thumb Mode:

 Smaller code size, hence reduced memory usage.

 Faster access in memory-limited embedded systems.

 Be er performance in slow memory (e.g., flash).

  Compa ble with standard ARM processors.

Example:

MOV R0, #5 ; Load 5 into R0

ADD R1, R0, #3 ; Add 3 to R0 and store in R1

These two instruc ons in Thumb take 32 bits (16-bit each) instead of 64 bits in ARM.

Switching Between Modes:

 BX Rm: Branch to address in Rm

 If LSB = 1, switches to Thumb

 If LSB = 0, switches to ARM

Conclusion:

The Thumb instruc on set offers a good balance of performance and code compactness,
which is cri cal in embedded and mobile applica ons.

12. Explain excep ons in ARM processor with suitable examples.

Introduc on:

Excep ons in ARM are special condi ons that change the normal flow of execu on. On
excep on, the processor:

 Switches to an excep on mode.

 Saves CPSR to SPSR.

 Sets the PC to a specific excep on vector.

Types of Excep ons in ARM:

Excep on Type Mode Entered Vector Address Trigger

Reset Supervisor 0x00000000 Power-on or reset signal

Undefined Instruc on Undefined 0x00000004 Invalid opcode

Excep on Type Mode Entered Vector Address Trigger

So ware Interrupt (SWI) Supervisor 0x00000008 SWI instruc on

Prefetch Abort Abort 0x0000000C Instruc on fetch failure

Data Abort Abort 0x00000010 Memory access viola on

IRQ (Interrupt Request) IRQ 0x00000018 External hardware interrupt

FIQ (Fast Interrupt) FIQ 0x0000001C High-priority interrupt

General Flow:

1. Store CPSR into SPSR_

2. Store return address in LR_

3. Set appropriate mode bits in CPSR

4. Disable further interrupts (IRQ/FIQ)

5. Jump to excep on vector address

Example: So ware Interrupt (SWI)

MOV R0, #1

SWI #0x0

 Triggers a supervisor call.

 Switches to SVC mode.

 Saves PC and CPSR, jumps to 0x08.

Importance:

 Enables system calls

 Handles illegal opera ons gracefully

 Ensures robust interrupt handling

Conclusion:
Excep on handling in ARM ensures system reliability by gracefully responding to errors,
hardware signals, and opera ng system requests.

13. Explain the memory management system of ARM.

Introduc on:

ARM supports various memory types and memory protec on mechanisms. It includes
Memory Management Unit (MMU) or Memory Protec on Unit (MPU) for advanced
systems.

Memory Regions in ARM:

 ROM: Read-only memory for firmware.

 SRAM: Fast temporary data storage.

 Flash: Used to store code.

 Peripherals: Memory-mapped I/O

 TCM (Tightly Coupled Memory): Low-latency memory close to CPU.

Memory A ributes:

 Access Permissions: Read, Write, Execute

 Cacheable / Non-cacheable

 Bufferable / Non-bufferable

 Shareable between cores (in mul core)

MMU in ARM:

 Translates virtual addresses to physical addresses.

 Provides access control per region.

 Supports paging and segmenta on.

 Implements virtual memory (used in Linux on ARM).

MPU (Memory Protec on Unit):

  Simpler than MMU.

 Provides region-based access control.

 Used in Cortex-M processors (no virtual memory).

Example of Memory Map:

0x00000000 – 0x000FFFFF → ROM

0x00100000 – 0x001FFFFF → RAM

0x40000000 – 0x4000FFFF → I/O

Conclusion:

ARM memory management allows flexible, secure, and fast memory access. MMU/MPU
helps in OS support, safety, and performance op miza on.

14. Compare ARM and Intel architectures.

Feature ARM Intel (x86)

Instruc on Set RISC (Simple, few instruc ons) CISC (Complex, many instruc ons)

Power Consump on Very low (mobile-focused) High (desktop/server)

Code Density Higher (Thumb mode) Lower

Performance Op mized for embedded, mobile Op mized for high compu ng

Clock Speed Lower Higher

Pipelines Simpler Complex with out-of-order

Registers R0–R15 EAX, EBX, ECX, etc. (fewer)

Hardware Complexity Low High

Cost Cheaper Costlier

Examples Smartphones, IoT Desktops, Laptops

Conclusion:
ARM is be er suited for embedded and mobile environments where power and size ma er.
Intel dominates the desktop and server markets due to its high-performance capabili es.

15. Write and explain the ARM assembly language program to find the factorial of a
number.

Problem Statement:

To write an ARM Assembly program to compute the factorial of a number stored in R0 and
store the result in R1.

ARM Assembly Code:

AREA FACTORIAL, CODE, READONLY

ENTRY

MOV R0, #5 ; Number to find factorial of

MOV R1, #1 ; Ini alize result = 1

FACTOR_LOOP

CMP R0, #1 ; Compare R0 with 1

BLE END ; If R0 <= 1, exit loop

MUL R1, R1, R0 ; R1 = R1 * R0

SUB R0, R0, #1 ; R0 = R0 - 1

B FACTOR_LOOP ; Repeat

END

STOP B STOP ; Infinite loop to stop

Explana on:

 MOV R0, #5: Load number (e.g., 5) into R0.

 MOV R1, #1: Result ini alized to 1.

  MUL R1, R1, R0: Mul ply result by current value.

 SUB R0, R0, #1: Decrement the value.

 BLE END: Exit when R0 <= 1.

Result:

A er execu on, R1 contains 5! = 120.

Conclusion:

This simple loop demonstrates arithme c, condi onal, and branching opera ons in ARM
assembly, suitable for learning and embedded logic programming.

That completes Q11–Q15 in VTU 10-mark format. Shall I con nue with Q16 to Q20 now?

Excellent! Here's the next batch: VTU-style detailed answers for Ques ons 16 to 20 of
BCS402 — all structured to help you score full 10 marks.

16. Write and explain the ARM assembly language program to add N numbers.

Problem Statement:

Write an ARM assembly program to input N numbers and compute their sum. Assume N is
provided in a register.

ARM Assembly Code:

AREA ADDNUM, CODE, READONLY

ENTRY

MOV R0, #5 ; Number of elements (N)

LDR R2, =NUMBERS ; Base address of numbers

MOV R1, #0 ; Ini alize sum = 0

LOOP LDR R3, [R2], #4 ; Load number from address and increment
 ADD R1, R1, R3 ; Add number to sum

SUB R0, R0, #1 ; Decrement counter

CMP R0, #0

BNE LOOP ; Loop un l all numbers are added

STOP B STOP ; End of program

NUMBERS DCD 10, 20, 30, 40, 50 ; Sample 5 numbers

Explana on:

 MOV R0, #5: Number of values to be added (N).

 LDR R2, =NUMBERS: Load base address of the number list.

 LDR R3, [R2], #4: Load value at R2, then post-increment R2 by 4 (next word).

 ADD R1, R1, R3: Accumulate the value in R1.

 Final result: Sum stored in R1 (R1 = 10+20+30+40+50 = 150)

Conclusion:

This program demonstrates register use, loops, and memory addressing in ARM assembly.
The result is efficiently computed using minimal instruc ons.

17. Write and explain the ARM assembly program to reverse a number.

Problem Statement:

To reverse a decimal number stored in a register and store the result in another register
using ARM Assembly.

ARM Assembly Code:

AREA REVERSE, CODE, READONLY

ENTRY
 MOV R0, #1234 ; Input number

MOV R1, #0 ; Reversed result

LOOP MOV R2, R0

MOV R3, #10

UDIV R2, R2, R3 ; R2 = R0 / 10

MLS R4, R2, R3, R0 ; R4 = R0 - (R2 * 10) => R4 = R0 % 10

MUL R1, R1, #10 ; Mul ply R1 by 10

ADD R1, R1, R4 ; Add remainder

MOV R0, R2 ; R0 = R0 / 10

CMP R0, #0

BNE LOOP

STOP B STOP

Explana on:

 UDIV and MLS are used to get quo ent and remainder.

 Reversal logic: %10 gives digit, then number = number / 10.

 Each digit is appended in reverse by mul plying the result by 10.

Result:

If R0 = 1234, a er loop R1 = 4321.

Conclusion:

This program shows how to perform arithme c opera ons, condi onal branching, and loops
using ARM assembly effec vely.
18. Write and explain the ARM assembly program to sort N numbers in ascending order.

Problem Statement:

To sort an array of numbers using Bubble Sort in ARM assembly.

ARM Assembly Code (Simplified Bubble Sort):

AREA SORT, CODE, READONLY

ENTRY

MOV R0, #5 ;N=5

LDR R1, =NUMBERS ; Base address of array

OUTER MOV R2, R0

SUB R2, R2, #1 ; Inner loop count

INNER LDR R3, [R1] ; Load A[i]

LDR R4, [R1, #4] ; Load A[i+1]

CMP R3, R4

BLE SKIP

STR R4, [R1] ; Swap if A[i] > A[i+1]

STR R3, [R1, #4]

SKIP ADD R1, R1, #4 ; Next pair

SUB R2, R2, #1

CMP R2, #0

BNE INNER

LDR R1, =NUMBERS

SUB R0, R0, #1

 CMP R0, #1

BNE OUTER

STOP B STOP

NUMBERS DCD 50, 20, 10, 30, 40

Explana on:

 Uses nested loops (outer and inner) for bubble sort.

 CMP, BLE, and condi onal execu on used for comparisons and swapping.

 Uses memory indirect addressing for array elements.

Result:

Ini al: [50, 20, 10, 30, 40]

Final Sorted: [10, 20, 30, 40, 50]

Conclusion:

Sor ng logic in ARM assembly enhances understanding of memory access and control flow.
Bubble sort is simple but demonstrates core instruc on usage.

19. Write and explain the ARM assembly program to check for palindrome.

Problem Statement:

To check if a number (e.g., 121 or 1331) is a palindrome (same forward and backward).

ARM Assembly Code:

AREA PALIN, CODE, READONLY

ENTRY

MOV R0, #1221 ; Input number

 MOV R5, R0 ; Copy of original

MOV R1, #0

LOOP MOV R2, R0

MOV R3, #10

UDIV R2, R2, R3

MLS R4, R2, R3, R0 ; R4 = R0 % 10

MUL R1, R1, #10

ADD R1, R1, R4

MOV R0, R2

CMP R0, #0

BNE LOOP

CMP R1, R5 ; Compare reversed and original

BEQ PALINDROME

B NOT_PALINDROME

PALINDROME

; Code for palindrome

STOP B STOP

NOT_PALINDROME

; Code for not a palindrome

STOP B STOP

Explana on:
  Reverses the number and compares with original.

 UDIV and MLS used for division and modulus.

 If original == reversed, it's a palindrome.

Conclusion:

ARM Assembly code for palindrome checking uses arithme c, branching, and comparison,
useful in pa ern recogni on in embedded applica ons.

20. Explain load-store architecture with an example.

Introduc on:

ARM follows a load-store architecture, which means:

 Only LDR (load) and STR (store) instruc ons access memory.

 All data processing opera ons happen between registers only.

 Memory access is separate from computa on.

Characteris cs:

 Promotes simplicity in instruc on decoding.

 Enables uniform execu on mes.

 Encourages effec ve pipelining.

 Enhances compiler efficiency.

Example:

LDR R0, [R1] ; Load value from address in R1 into R0

LDR R2, [R3] ; Load another value

ADD R4, R0, R2 ; Add both values

STR R4, [R5] ; Store result to memory

Advantages:

1. Faster execu on due to pipelining.

 2. Reduced instruc on complexity.

3. Hardware simplifica on: No need for complex addressing.

4. Predictable behavior: Each instruc on does one thing.

Comparison with CISC:

 CISC can perform memory opera ons in ALU instruc ons, e.g., ADD [A], B

 ARM cannot. It must load first, then operate.

Conclusion:

Load-store architecture simplifies processor design, ensures consistent instruc on mings,

and supports high-speed execu on — a key reason why ARM is favored in embedded
systems.

That wraps up Q16–Q20. Next, I’ll con nue with Q21–Q25 in the same detailed style.

Would you like me to proceed?

Great! Let’s now con nue with Ques ons 21 to 25, wri en in VTU 10-mark detailed format
for BCS402 ARM-based Embedded System. These are structured for clarity and to help you
maximize your marks.

21. Write and explain ARM assembly program to count the number of ones in a binary
number.

Problem Statement:

To count the number of 1s (set bits) in a 32-bit binary number using ARM assembly.

ARM Assembly Code:

AREA COUNT_ONES, CODE, READONLY

ENTRY

MOV R0, #0xF0F0F0F0 ; Input number (e.g., 1111000011110000...)

MOV R1, #0 ; Counter ini alized to 0

LOOP CMP R0, #0 ; Check if input is 0

BEQ END

AND R2, R0, #1 ; Isolate LSB

ADD R1, R1, R2 ; Add to counter if bit is 1

LSR R0, R0, #1 ; Logical shi right

B LOOP

END STOP B STOP ; Infinite stop

Explana on:

 AND R2, R0, #1: Extracts the least significant bit.

 ADD R1, R1, R2: Increments counter if bit is 1.

 LSR R0, R0, #1: Shi s number right to access next bit.

Example:

If R0 = 0b1011 (11 in decimal), result in R1 = 3 (since there are three 1s).

Conclusion:

This simple bitwise loop demonstrates how to use ARM’s logical instruc ons for coun ng
and scanning bits in an embedded scenario.

22. Explain the concept of stack in ARM processor with examples.

Stack Overview:

 Stack: A data structure (LIFO) used for storing return addresses, register contents,
local variables.

 In ARM, stack typically grows downward (toward lower memory).

 Managed using Stack Pointer (SP) → usually R13.

Stack Opera ons:

1. PUSH: Store register(s) on stack

2. PUSH {R0, R1, LR}

o Decrements SP and stores contents.

3. POP: Restore register(s) from stack

4. POP {R0, R1, PC}

o Loads values from stack and increments SP.

Full Descending Stack:

 Commonly used.

 Stack pointer points to the last used loca on.

 Conforms to Full Descending Stack Conven on (used in ARM’s AAPCS standard).

Example Func on Call:

PUSH {R4-R6, LR} ; Save registers before func on

; Func on body

POP {R4-R6, PC} ; Restore and return

Importance of Stack:

 Supports nested func on calls.

 Preserves context during interrupts or mode switches.

 Used in recursive func ons.

Conclusion:

Stack is essen al in ARM for context saving, subrou ne calls, and structured memory usage.
ARM instruc ons like PUSH/POP simplify stack opera ons with efficiency.

23. Explain the concept of condi onal execu on in ARM.

Introduc on:

One unique feature of ARM is that almost all instruc ons can be condi onally executed
based on flags in the CPSR (Current Program Status Register).

Why Condi onal Execu on?

 Reduces need for branches (jumps).

 Improves pipeline efficiency.

 Reduces code size.

Condi on Codes:

ARM instruc ons can be suffixed with condi on codes like:

Suffix Meaning Condi on Checked

EQ Equal Z=1

NE Not Equal Z=0

GT Greater Than Z = 0 and N=V

LT Less Than N≠V

GE Greater or Equal N = V

LE Less or Equal Z=1 or N ≠ V

AL Always (default) -

Example:

CMP R0, #0

MOVEQ R1, #0 ; If R0 == 0, then R1 = 0

MOVNE R1, #1 ; If R0 != 0, then R1 = 1

Benefits:

 Avoids branching, hence no branch penal es.

  Keeps execu on smooth and linear.

 Ideal for real- me systems where ming is cri cal.

Conclusion:

Condi onal execu on makes ARM code efficient, compact, and pipeline-friendly. It allows
decisions without costly branches.

24. Explain the concept of memory-mapped I/O with an example.

Introduc on:

In Memory-Mapped I/O, peripherals (like LEDs, motors, sensors) are assigned unique
memory addresses.

 No special I/O instruc ons required.

 Peripherals can be accessed like normal memory.

Working:

 Each peripheral has a register (control/data).

 You use LDR/STR to access those registers.

 Example: LED at address 0x40000000

Example:

LDR R0, =0x40000000 ; Load address of LED register

MOV R1, #1

STR R1, [R0] ; Turn ON LED

Benefits:

 Uniform addressing model.

 Faster and simpler programming.

 Direct control over hardware.

Comparison:

Feature Memory-Mapped I/O Port-Mapped I/O (CISC)

Addressing Uses normal memory Uses special ports

Instruc ons LDR/STR IN/OUT (not in ARM)

Speed Faster Slower

Uniform Access Yes No

Conclusion:

Memory-mapped I/O is a powerful ARM feature for embedded systems, giving programmers
easy access to external hardware using standard instruc ons.

25. Explain the ARM instruc on set format in detail.

ARM Instruc on Word:

Each ARM instruc on is 32 bits long (unless in Thumb mode). The instruc on is divided into
fields that determine its func on.

General Format:

| Cond | Op | S | Rn | Rd | Operand2 |

4 bit 6bit 1b 4b 4b 12b

Key Fields:

 Cond (bits 31-28): Condi on code (EQ, NE, AL)

 Opcode (bits 27-21): Specifies opera on (ADD, SUB, MOV)

 S (bit 20): Set condi on codes if 1

 Rn (bits 19-16): First operand register

 Rd (bits 15-12): Des na on register

 Operand2 (bits 11-0): Second operand (register/immediate/shi ed)

Example: ADD R0, R1, R2

 Cond: 1110 (Always)

 Opcode: 0100 (ADD)

 Rn: R1

 Rd: R0

 Operand2: R2

Instruc on Categories:

1. Data Processing: Arithme c and logical ops (ADD, SUB, AND)

2. Branch: B, BL (branch with link)

3. Memory Access: LDR, STR (load/store)

4. Status Register Transfer: MRS, MSR

Instruc on Format Variants:

 Immediate Format: Uses constants (e.g., MOV R0, #5)

 Register Format: Both operands are registers

 Shi ed Register: Supports inline shi ing

Conclusion:

ARM instruc ons follow a fixed and orthogonal format, enabling efficient decoding and
execu on. The uniform structure improves performance and supports condi onal execu on.

This completes Ques ons 21–25 in full 10-mark format. Next, I’ll deliver the final
Ques ons 26–28. Shall I go ahead?

Awesome! Let’s now complete the full set with VTU-style detailed 10-mark answers for
Ques ons 26 to 28 — the final part of the BCS402 prepara on set.

26. Write a short note on barrel shi er and its types with examples.

Introduc on:
A barrel shi er in ARM is a combina onal logic circuit used to shi or rotate register values
efficiently. It allows shi /rotate opera ons to occur in a single instruc on cycle as part of
ALU opera ons.

Importance:

 Embedded in data-processing instruc ons.

 Saves execu on me by avoiding separate shi instruc ons.

 Supports dynamic shi s (shi amount from register).

Types of Barrel Shi er Opera ons in ARM:

Type Opera on Effect

LSL Logical Shi Le Mul plies by 2n

LSR Logical Shi Right Divides by 2n, fills with 0

ASR Arithme c Shi Right Preserves sign (MSB filled with original)

ROR Rotate Right Wrap-around shi

RRX Rotate Right Extended (1-bit with carry) Includes carry flag

Syntax Example:

ADD R0, R1, R2, LSL #2 ; R0 = R1 + (R2 << 2)

 Here, R2 is shi ed le by 2 bits before being added to R1.

Examples:

 LSL (Logical Shi Le ):

 MOV R1, #5 ; 0000 0101

 LSL R2, R1, #1 ; 0000 1010 → R2 = 10

 ASR (Arithme c Shi Right):

 MOV R1, #-8 ; 1111 1000

 ASR R2, R1, #2 ; 1111 1110 → keeps sign

  ROR (Rotate Right):

 MOV R1, #0x80000001

 ROR R2, R1, #1 ; Wraps MSB to LSB

Advantages:

 Enhances performance by combining shi and arithme c in one instruc on.

 Reduces code size.

 Supports dynamic shi values (e.g., from another register).

Conclusion:

The barrel shi er is a powerful built-in unit in ARM processors that enables fast and flexible
bit-level opera ons without extra cycles, especially valuable in embedded control
applica ons.

27. Describe so ware interrupts in ARM with example.

Introduc on:

So ware Interrupt (SWI) in ARM is an instruc on used to request a system service from the
opera ng system or switch to a supervisor mode.

 Syntax: SWI <immediate value>

 Executes an excep on and branches to 0x08, the SWI vector.

When is SWI used?

 To invoke system calls (e.g., file I/O).

 To switch from user mode to privileged mode.

 To access kernel services safely.

How SWI Works:

1. SWI instruc on executed.

2. PC and CPSR are saved into LR_svc and SPSR_svc.

 3. Processor enters Supervisor mode.

4. Jumps to 0x08, the SWI handler address.

5. Handler decodes SWI number and provides appropriate service.

Example:

MOV R0, #1 ; Load service number

SWI #0 ; Request OS service

 SWI #0 could mean print, exit, etc., depending on OS.

Registers Affected:

 LR (R14_svc): Stores return address.

 SPSR: Stores CPSR.

 CPSR: Updated with Supervisor mode bits.

Implemen ng SWI Handler (in OS or simulator):

SWI_Handler:

CMP R0, #1

BEQ PRINT_MSG

; More service checks

Advantages:

 Protects system from unauthorized access.

 Provides structured way to interact with OS.

 Facilitates mul -user and mul tasking environments.

Conclusion:

SWIs provide a secure and structured mechanism for reques ng system-level services from
user applica ons. They play a vital role in opera ng system interac ons on ARM.
28. Write and explain an ARM assembly program to compute GCD of two numbers.

Problem Statement:

Find the Greatest Common Divisor (GCD) of two integers using the Euclidean algorithm.

Euclidean Algorithm:

1. GCD(a, b) = GCD(b, a % b)

2. Con nue un l b = 0

3. Result = a

ARM Assembly Code:

AREA GCD, CODE, READONLY

ENTRY

MOV R0, #48 ; First number (a)

MOV R1, #18 ; Second number (b)

GCD_LOOP

CMP R1, #0

BEQ DONE

MOV R2, R0

UDIV R3, R0, R1 ; R3 = R0 / R1 (not used)

MLS R2, R3, R1, R0 ; R2 = R0 - R3*R1 = R0 % R1

MOV R0, R1

MOV R1, R2

B GCD_LOOP
DONE

; GCD result is in R0

STOP B STOP

Explana on:

 UDIV computes division.

 MLS efficiently computes modulus: R0 % R1.

 Loop con nues un l R1 = 0.

 Final GCD stored in R0.

Example:

 For R0 = 48 and R1 = 18:

o GCD = 6

Conclusion:

ARM assembly efficiently implements GCD using loops and arithme c instruc ons. This
demonstrates condi onal branching, register opera ons, and hardware-accelerated math.

All 28 ques ons of BCS402 have now been completed in VTU 10-mark long-answer
format, fully detailed and ready for review or export.

Would you like me to generate a single PDF of all these answers for easy reading and
prin ng?