UNIT – 4: 8051 INTERRUPT (PROGRAMMING & SERIAL COMMUNICATION WITH 8051):

Definition of an interrupt, types of interrupts, Timers and Counter programming with interrupts in assembly. 8051
Serial Communication: Data communication, Basics of Serial Data Communication, 8051 Serial Communication.

Interrupt Programming:

Interrupts vs. Polling Method:

A single microcontroller can serve several devices. There are two ways to do that: interrupts and polling.

In the interrupt method, whenever any device needs its service, the device notifies the microcontroller by sending
it an interrupt signal. Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and
serves the device. The program which is associated with the interrupt is called the interrupt service routine (ISR)
or interrupt handler.

In polling method, the microcontroller continuously monitors the status of a given device; when the status
conditions met, it performs the service. After that, it moves on to monitor the next device until each one is
serviced.

In polling method there is no efficient use of microcontroller. Though in interrupt method not all devices can be
serviced at the same time, each device can get the attention of microcontroller based on priority assigned to it. In
polling method priority cannot be assigned since it checks all devices in a round-robin fashion. In interrupt
method, microcontroller can also ignore (mask) a device request for service which is not possible in polling
method. In polling method, microcontroller wastes its time by polling devices that do not need service. To save
the time, interrupt method is employed.

For example, in timer programming, microcontroller waits till the TF flag is set to 1. In interrupt method,
microcontroller will perform some useful task while the timer is running. It does not wait till the TF is set to 1.
Once the TF flag is set to 1, timer generates interrupt.

Dept. of ECE, TJIT Page 1

Interrupt service routine:

For every interrupt, there must be an interrupt service routine (ISR) or interrupt handler. When an interrupt is
invoked, the microcontroller runs ISR. For ever interrupt; there is a fixed location in memory that holds the
address of its ISR. The group of memory locations set aside to hold the addresses of ISRs is called the interrupt
vector table.

Dept. of ECE, TJIT Page 2

Steps in executing an interrupt:

Upon activation of an interrupt, the microcontroller goes through the following steps:
1. It finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e.: not on the stack)
3. It jumps to a fixed location in memory, called the interrupt vector table that holds the address of the ISR. 4.
The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. It starts to
execute the interrupt service subroutine until it reaches the last instruction of the subroutine which is RETI
(return from interrupt).
5. Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted. First,
it gets the program counter (PC) address from the stack by popping the top two bytes of the stack into the PC.

Types of Interrupts:

There are two types of interrupts: a.

External interrupts
b. Internal interrupts

8051 has three external interrupts and three internal interrupts. They are:
i. Reset: When the reset pin is activated, the 8051 jumps to address location 0000h.

ii. Timer 0 and Timer 1 interrupt: Two interrupts are set aside for the timers: one for timer 0 and one for
timer 1. Memory locations 000BH and 001BH in the interrupt vector table belongs to timer 0 and timer 1
respectively.

iii. INT0 and INT1: Two interrupts are set aside for external hardware interrupts. Pin numbers 12 (P3.2)
and 13 (P3.3) of Port 3 are INT0 and INT1 respectively. They are also referred as EX1 and EX2. Memory
locations 0003H is assigned to INT0 and 0013H is assigned to INT1 in the interrupt vector table.

iv. Serial Communication: It has single interrupt that belongs to both receive and transmit. Memory location
0023H belongs to this interrupt.

From interrupt vector table, it is evident that limited number of bytes is set aside for each interrupt. For Reset
interrupt only 3 bytes of location is allocated. For example, a total of 8 bytes from location 0003H to 000AH is
set aside for INT0, 8 bytes from location 000BH to 0012H for Timer 0, 8 bytes from location 0013H to 001AH
for INT1, 8 bytes from location 001BH to 0022H for timer 1. If the service routine for a given interrupt is short
enough to fit in the memory space allocated to it, it is placed in the vector table; otherwise an LJMP instruction
is placed in the vector table to point to the address of the ISR and rest of the bytes allocated to that interrupt are
unused.
ORG 0 ; wake-up ROM reset location
LJMP MAIN ; by-pass int. vector table
;----- the wake-up program
ORG 30H
MAIN:
....
END

Dept. of ECE, TJIT Page 3

Enabling and disabling an interrupt:

Upon reset, all interrupts are disabled (masked), meaning that none will be responded to by the microcontroller if
they are activated. The interrupts must be enabled by software in order for the microcontroller to respond to them.
There is a register called IE (interrupt enable) that is responsible for enabling (unmasking) and disabling (masking)
the interrupts.

Interrupt Enable (IE) register:

It is a bit addressable register.

EA: If 0, disables all interrupts, no interrupt is acknowledged. If 1, each interrupt source is individually enabled
or disabled by setting or clearing individual bit.
--: Not implemented, reserved for future use.
ET2: Enables or disables timer 2 overflows or capture interrupt (8052) only.
ES: Enables or disables the serial port interrupt.
ET1: Enables or disables timer 1 overflow interrupt.
EX1: Enables or disables external interrupt 1 (INT1).
ET0: Enables or disables timer 0 overflow interrupt.
ET0: Enables or disables external interrupt 0 (INT0).

Show the instructions to (a) enable the serial interrupt, timer 0 interrupt, and external hardware interrupt
1 (EX1),and (b) disable (mask) the timer 0 interrupt, then (c) show how to disable all the interrupts with a
single instruction.

Solution:
(a) MOV IE, #10010110B; enable serial, timer 0,
EX1 (b) CLR IE.1; mask (disable) timer 0 interrupt
only (c) CLR IE.7; disable all interrupts.
Another way to perform the same manipulation is
SETB IE.7; EA=1, global enable
SETB IE.4; enable serial interrupt
SETB IE.1; enable Timer 0 interrupt
SETB IE.2; enable EX1

Programming Timer Interrupts:

Roll-over timer flag and interrupt:

Dept. of ECE, TJIT Page 4

The timer flag (TF) is raised when the timer rolls over. In polling TF, we have to wait until the TF is raised. The
problem with this method is that the microcontroller is tied down while waiting for TF to be raised, and cannot
do anything else. Using interrupts solves this problem and, avoids tying down the controller. If the timer interrupt
in the IE register is enabled, whenever the timer rolls over, TF is raised, and the microcontroller is interrupted in
whatever it is doing, and jumps to the interrupt vector table to service the ISR. In this way, the microcontroller
can do other things until it is notified that the timer has rolled over.

Write a program that continuously get 8-bit data from P0 and sends it to P1 while simultaneously creating
a square wave of 200 μs period on pin P2.1. Use timer 0 to create the square wave. Assume that XTAL =
11.0592 MHz.

Solution:
We will use timer 0 in mode 2 (auto reload). TH0 = 100/1.085 us = 92
;--upon wake-up go to main, avoid using memory allocated to Interrupt Vector Table ORG
0000H
LJMP MAIN ; by-pass interrupt vector table
;--ISR for timer 0 to generate square
wave
ORG 000BH ; Timer 0 interrupt vector table
CPL P2.1 ; toggle P2.1 pin
RETI
;--The main program for initialization
ORG 0030H ; after vector table space
MAIN: MOV TMOD, #02H ; Timer 0, mode 2
MOV P0, #0FFH ; make P0 an input port
MOV TH0, #-92 ; TH0=A4H for -92
MOV IE, #82H ; IE=10000010 (bin) enable
Timer 0
SETB TR0 ; Start Timer 0
BACK: MOV A, P0 ; get data from P0
MOV P1, A ; issue it to P1
SJMP BACK ; keep doing it loop unless interrupted by
END TF0

Notice the following points in the above program:

1. Memory space allocated to the interrupt vector table should be avoided. Place all the initialization codes in
memory starting at 30H. The LJMP instruction is the first instruction that the 8051 executes when it is powered
up. LJMP redirects the controller away from the interrupt vector table.

Dept. of ECE, TJIT Page 5

2. The ISR for timer 0 is located starting at memory location 000BH since it is small enough to fit the address
space allocated to this interrupt.

3. Enable timer 0 interrupt.

4. While the P0 data is brought in and issued to P1 continuously, whenever timer 0 is rolled over, the TF0 flag is
raised and the microcontroller gets out of the BACK loop and goes to 000BH to execute the ISR associated
with timer 0.

5. In the ISR for timer 0, notice that there is no need for a CLR TF0 instruction before the RETI instruction. This
is because the 8051 clears the TF flag internally upon jumping to the interrupt vector table.

Write an assembly language program to create a square wave that has a high portion of 1085 us and a low
portion of 15 us. Assume XTAL=11.0592MHz. Use timer 1.

Solution:
Since 1085 μs is 1000 × 1.085 we need to use mode 1 of timer 1.
;--upon wake-up go to main, avoid using memory allocated to Interrupt Vector Table ORG
0000H
LJMP MAIN ; by-pass int. vector table
;--ISR for timer 1 to generate square wave
ORG 001BH ; Timer 1 int. vector table
LJMP ISR_T1 ; jump to ISR
;--The main program for initialization
ORG 0030H ; after vector table space
MAIN: MOV TMOD, #10H ; Timer 1, mode 1
MOV P0, #0FFH ; make P0 an input port
MOV TL1, #018H ; TL1=18 low byte of -1000
MOV TH1, #0FCH ; TH1=FC high byte of -1000
MOV IE, #88H ; 10001000 enable Timer 1 int
SETB TR1 ; Start Timer 1
BACK: MOV A, P0 ; get data from P0
MOV P1, A ; issue it to P1
SJMP BACK ; keep doing it
; Timer 1 ISR. Must be reloaded, not auto-reload
ISR_T1: CLR TR1 ; stop Timer 1
MOV R2, #4 ; 2MC
CLR P2.1 ; P2.1=0, start of low portion
HERE: DJNZ R2, HERE ; 4x2 machine cycle 8MC
MOV TL1, #18H ; load T1 low byte value 2MC
MOV TH1, #0FCH ; load T1 high byte value 2MC
SETB TR1 ; starts timer1 1MC
SETB P2.1 ; P2.1=1, back to high 1MC
RETI ; return to main
END

Dept. of ECE, TJIT Page 6

In the above program the low portion of the pulse is created by the 14 machine cycles (MC) where each MC =
1.085 μs and 14 x 1.085 μs = 15.19 μs.

Programming external hardware interrupts:

The 8051 has two external hardware interrupts. Pin 12 (P3.2) and pin 13 (P3.3) of the 8051, designated as INT0
and INT1, are used as external hardware interrupts. Upon activation of these pins, the 8051 gets interrupted in
whatever it is doing and jumps to the vector table to perform the interrupt service routine.

External interrupts INT0 and INT1:

There are two external hardware interrupts; INT0 and INT1. They are located on pins P3.2 and P3.3 of port 3
respectively. The IVT locations 0003H and 0013H are set aside for INTO0 and INT1 respectively. They are
enabled and disabled using IE register.

They are activated using two methods:

1. Level triggered
2. Edge triggered.

Level triggered interrupt:

Dept. of ECE, TJIT Page 7

In the level-triggered mode, INT0 and INT1 pins are normally high. If a low-level signal is applied to them, it
triggers the interrupt. Then the microcontroller stops whatever it is doing and jumps to the interrupt vector table
to service that interrupt. This is called as a level-triggered or level-activated interrupt and is the default mode
upon reset of the 8051. The low-level signal at the INT pin must be removed before the execution of the last
instruction of the ISR, RETI; otherwise, another interrupt will be generated. In other words, if the low level
interrupt signal is not removed before the ISR is finished it is interpreted as another interrupt and the 8051 jumps
to the vector table to execute the ISR again.

Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low, it should
turn on an LED. The LED is connected to P1.3 and is normally off. When it is turned on it should stay on
for a fraction of a second. As long as the switch is pressed low, the LED should stay on.

Solution:
ORG 0000H
LJMP MAIN ; by-pass interrupt vector table
;--ISR for INT1 to turn on LED
ORG 0013H ; INT1 ISR
SETB P1.3 ; turn on LED
MOV R3, #255
BACK: DJNZ R3, BACK ; keep LED on for a while
CLR P1.3 ; turn off the LED
RETI ; return from ISR
;--MAIN program for initialization
ORG 30H
MAIN: MOV IE, #10000100B ; enable external INT 1
HERE: SJMP HERE ; stay here until get interrupted END

In the above program, the microcontroller is looping continuously in the HERE loop. Whenever the switch on
INT1 is activated, the 8051 gets out of the loop and jumps to vector location 0013H. The ISR for INT1 turns on
the LED, keeps it on for a while, and turns it off before it returns. If by the time it executes the RETI instruction,
the INT1 pin is still low, the microcontroller initiates the interrupt again. Therefore, to end this problem, the INT1
pin must be brought back to high by the time RETI is executed.

Sampling the low level-triggered interrupt:

Pins P3.2 and P3.3 are used for normal I/O unless the INT0 and INT1 bits in the IE register are enabled. After
the hardware interrupts in the IE register are enabled, the controller keeps sampling the INT0 or INT1 pin for a
low-level signal once each machine cycle. According to one manufacturer‟s data sheet, the pin must be held in a
low state until the start of the execution of ISR. If the INT0 or INT1 pin is brought back to logic high before the
start of the execution of ISR there will be no interrupt.

However, upon activation of the interrupt due to the low level, it must be brought back to high before the execution
of RETI. According to one manufacturer‟s data sheet, if the INT0 or INT1 pin is left at a logic low after the RETI
instruction of the ISR, another interrupt will be activated after one instruction is executed. Therefore to ensure
the activation of the hardware interrupt at the INT0 or INT1 pin, make sure that the duration of the low-level
signal is around 4 machine cycles but no more. This is due to fact that the level-triggered interrupt is not latched.
Thus the pin must be held in a low state until the start of the ISR execution.

Dept. of ECE, TJIT Page 8

On reset, both IT0 (TCON.0) and IT1 (TCON.2) are low, making external interrupt level triggered.

Edge-triggered interrupts:
To make INT0 and INT1 edge triggered interrupts, we must program the bits of the TCON register. The TCON
register holds, among other bits, the IT0 and IT1 flag bits that determine level- or edge-triggered mode of the
hardware interrupts. IT0 and IT1 are bits D0 and D2 of the TCON register, respectively. They are also referred
to as TCON.0 and TCON.2 since the TCON register is bit addressable. On reset, both IT0 (TCON.0) and IT1
(TCON.2) are low, making external interrupt level triggered. By making the TCON.0 and TCON.2 bits high with
instructions such as SETB TCON.0 and SETB TCON.2, the external hardware interrupts of INT0 and INT1
become edge-triggered. For example, the instruction SETB TCON.2 makes INT1 edge-triggered. When a high-
to-low signal is applied to pin P3.3, 8051 is interrupted and forced to jump to location 0013H in the vector table
to service the ISR, assuming interrupt due to INT1 is enabled.

Generate from all pins of Port 0, a square wave which is half the frequency of the signal applied at INT0.

Solution:
ORG 0000H
LJMP MAIN

Dept. of ECE, TJIT Page 9

; ISR for hardware interrupt INT0
ORG 0003H
CPL P0
RETI
ORG 0030H
MAIN:
SETB TCON.0 ; make INT0 an edge-triggered interrupt
MOV IE, #81H ; enable hardware interrupt INT0
HERE: SJMP HERE
END

Assume that pin 3.3 (INT1) is connected to a pulse generator, write a program in which the falling edge of
the pulse will send a high to P1.3, which is connected to an LED (or buzzer). In other words, the LED is
turned on and off at the same rate as the pulses are applied to the INT1 pin.

Solution:
ORG 0000H
LJMP MAIN
;--ISR for hardware interrupt INT1 to turn on LED
ORG 0013H ; INT1 ISR
SETB P1.3 ; turn on LED
MOV R3, #255
BACK: DJNZ R3, BACK ; keep the buzzer on for a while
CLR P1.3 ; turn off the buzzer
RETI ; return from ISR
;------ MAIN program for initialization
ORG 30H
MAIN: SETB TCON.2 ; make INT1 edge-triggered int.
MOV IE, #10000100B ; enable External INT 1
HERE: SJMP HERE END ; stay here until get interrupted

In the above program when falling edge of the signal is applied to pin INT1, the LED will be turned on
momentarily. The LED‟s on-state duration depends on the time delay inside the ISR for INT1. To turn on the
LED again, another high-to-low pulse must be applied to pin P3.3.

Sampling the edge-triggered interrupt:

In edge-triggered interrupts, the external source must be held high for at least one machine cycle, and then held
low for at least one machine cycle to ensure that the transition is seen by the microcontroller.

Dept. of ECE, TJIT Page 10

The falling edge is latched by the 8051 and is held by the TCON register. The TCON.1 and TCON.3 bits hold
the latched falling edge of pins INT0 and INT1, respectively. TCON.1 and TCON.3 are also called IE0 and IE1,
respectively. They function as interrupt-in-service flags. When an interrupt-in-service flag is raised, it indicates
to the external world that the interrupt is being serviced and no new interrupt on this INT0 or INT1 pin will be
responded to until this service is finished. This is just like the busy signal you get if calling a telephone number
that is in use.

Regarding the IT0 and IT1 bits in the TCON register, the following two points must be emphasized.
1. When the ISRs are finished (that is, upon execution of RETI), these bits (TCON.1 and TCON.3) are
cleared, indicating that the interrupt is finished and the 8051 is ready to respond to another interrupt on that pin.
For another interrupt to be recognized, the pin must go back to a logic high state and be brought back low to be
considered an edge-triggered interrupt.

2. While the ISR is being executed, the INT0 or INT1 pin is ignored, no matter how many times it makes a
high-to-low transition. In reality one of the functions of the RETI instruction is to clear the corresponding bit in
the TCON register (TCON.1 or TCON.3). This informs us that the service routine is no longer in progress and
has finished being serviced. For this reason TCON.1 and TCON.3 in the TCON register are called interrupt-
inservice flags. The interrupt-in-service flag goes high whenever a falling edge is detected at the INT pin, and
stays high during the entire execution of the ISR. It is only cleared by RETI, the last instruction of the ISR.
Because of this, there is no need for an instruction such as CLR TCON.1 (INT0) or CLR TCON.3 (INT1) before
the RETI in the ISR associated with the hardware interrupt INT0 or INT1.

What is the difference between the RET and RETI instructions? Explain why we cannot use RET instead
of RETI as the last instruction of an ISR.

Both perform the same actions of popping off the top two bytes of the stack into the program counter, and marking
the 8051 return to where it left off. However, RETI also performs an additional task of clearing the interrupt-in-
service flag, indicating that the servicing of the interrupt is over and the 8051 now can accept a new interrupt on
that pin. If you use RET instead of RETI as the last instruction of the interrupt service routine, you simply block
any new interrupt on that pin after the first interrupt, since the pin status would indicate that the interrupt is still
being serviced. In the cases of TF0, TF1, TCON.1, and TCON.3, they are cleared due to the execution of RETI.

More about the TCON register:

IT0 and IT1:

These two bits set the low-level or edge-triggered modes of the external hardware interrupts of the INT0 and INT1
pins. They are both 0 upon reset, which makes them low-level triggered. The programmer can make either of
them high to make the external hardware interrupt edge-triggered. Once they are set to 0 or 1 they will not be
altered again since the designer has fixed the interrupt as wither edge or level triggered.

IE0 and IE1:

These bits are used to keep track of the edge-triggered interrupt only. In other words, if the IT0 and IT1 are 0,
meaning that the hardware interrupts are low level triggered, IE0 and IE1 are not used at all. The IE0 and IE1
bits are used to latch the high-to-low edge transition on the INT0 and INT1 pins. Upon the edge transition pulse
on the INT0 or INT1 pin, the 8051 sets the IE0 or IE1 bit in the TCON register, jumps to the vector in the interrupt

Dept. of ECE, TJIT Page 11

vector table and starts to execute the ISR. While it is executing the ISR, no high-to-low pulse transition on the
INT0 or INT1 is recognized, thereby preventing any interrupt inside the interrupt. Only the execution of the RETI
instruction at the end of the ISR will clear the IE0 or IE1 bit, indicating that the new high-to-low pulse will activate
the interrupt again. Hence IE0 and IE1 bits are used internally by the 8051 to indicate whether or not an interrupt
is in use and programmer is not concerned with these bits since they are solely for internal use.

TR0 and TR1:

These bits are used to start and stop the timer. These bits can be enabled and disabled using the instructions SETB
or CLR instruction and SETB TCON.4 and CLR TCON.4.

TF0 and TF1:

These bits are timer overflow flag bits. They are set when the corresponding timer overflows. They are monitored
using JNB TFx, TARGET instruction and cleared using CLR instruction. They can also be monitored using JNB
TCON.5, TARGET and cleared using CLR TCON.5 instructions.

Programming the serial communication interrupt:

In the earlier topic, when data is transmitted or received serially, TI or RI flag was set which was monitored using
JNB instruction. This method is known as polling method. Instead of this if interrupt is enabled due to serial
communication, TI or RI flag need not be monitored. Once these flags are set, microcontroller will automatically
generate interrupt.

RI and TI flags and interrupts:

TI is raised when the last bit of the framed data, the stop bit is transferred; indicating that the SBUF register is
ready to transfer the next byte. RI is raised when the entire frame of data, including the stop bit is received. That
is when the SBUF register has a byte RI is raised to indicate that the received byte needs to be picked up before
it is lost (overrun) by new incoming serial data. All the above concepts apply equally when using either polling
or an interrupt. The only difference is in how the serial communication needs are served.

In the 8051 only one interrupt is set aside for serial communication. This interrupt is used to both send and receive
data. If the interrupt bit in the IE register (IE.4) is enabled when RI or TI is raised, the 8051 gets interrupted and
jumps to memory address location 0023H to execute the ISR. In that ISR we must examine the TI and RI flags
to see which one caused the interrupt and respond accordingly.

Serial interrupt is invoked by TI or RI flags

Dept. of ECE, TJIT Page 12

Write a program in which the 8051 reads data from P1 and writes it to P2 continuously while giving a copy
of it to the serial COM port to be transferred serially. Assume that XTAL=11.0592. Set the baud rate at
9600.

Solution:
ORG 0000H
LJMP MAIN
ORG 23H
LJMP SERIAL ; jump to serial int ISR
ORG 30H
MAIN: MOV P1, #0FFH ; make P1 an input port
MOV TMOD, #20H ; timer 1, auto reload
MOV TH1, #0FDH ; 9600 baud rate
MOV SCON, #50H ; 8-bit,1 stop, ren enabled
MOV IE, #10010000B ; enable serial int.
SETB TR1 ; start timer 1
BACK: MOV A, P1 ; read data from port 1
MOV SBUF, A ; give a copy to SBUF
MOV P2, A ; send it to P2
SJMP BACK ; stay in loop indefinitely
;----------------- SERIAL PORT ISR
ORG 100H
SERIAL: JB TI, TRANS ; jump if TI is high
MOV A, SBUF ; otherwise due to receive
CLR RI ; clear RI since CPU doesn‟t
RETI ; return from ISR
TRANS: CLR TI ; clear TI since CPU doesn‟t RETI
; return from ISR
END

The moment a byte is written into SBUF it is framed and transferred serially. As a result, when the last bit (stop
bit) is transferred the TI is raised, and that causes the serial interrupt to be invoked since the corresponding bit in
the IE register is high. In the serial ISR, we check for both TI and RI since both could have invoked interrupt.

Use of serial COM in the 8051:

In majority applications, the serial interrupt is used mainly for receiving data and is never used for sending data
serially. This is like receiving a telephone call, where we need a ring to be notified. If we need to make a phone
call there are other ways to remind ourselves and so no need for ringing. In receiving call, we must respond
immediately. Similarly we use the serial interrupt to receive incoming data so that it is not lost.

Dept. of ECE, TJIT Page 13

Write a program in which the 8051 gets data from P1 and sends it toP2 continuously while incoming data
from the serial port is sent to P0. Assume that XTAL=11.0592. Set the baud rata at 9600.

Solution:
ORG 0000H
LJMP MAIN
ORG 23H
LJMP SERIAL ; jump to serial int ISR
ORG 30H
MAIN: MOV P1, #0FFH ; make P1 an input port
MOV TMOD, #20H ; timer 1, auto reload
MOV TH1, #0FDH ; 9600 baud rate
MOV SCON, #50H ; 8-bit,1 stop, ren enabled
MOV IE, #10010000B ; enable serial int.
SETB TR1 ; start timer 1
BACK: MOV A, P1 ; read data from port 1
MOV P2, A ; send it to P2
SJMP BACK ; stay in loop indefinitely
;----------------- SERIAL PORT ISR
ORG 100H
SERIAL: JB TI, TRANS ; jump if TI is high
MOV A, SBUF ; otherwise due to receive
MOV P0, A ; send incoming data to P0
CLR RI ; clear RI since CPU doesn‟t
RETI ; return from ISR
TRANS: CLR TI ; clear TI since CPU doesn‟t
RETI ; return from ISR
END

Write a program using interrupts to do the following:

(a) Receive data serially and sent it to P0,
(b) Have P1 port read and transmitted serially, and a copy given to P2, (c) Make timer 0
generate a square wave of 5kHz frequency on P0.1. Assume that XTAL-11,0592. Set
the baud rate at 4800.

Solution:
ORG 0
LJMP MAIN
ORG 000BH ; ISR for timer 0
CPL P0.1 ; toggle P0.1

Dept. of ECE, TJIT Page 14

 RETI ; return from ISR
ORG 23H
LJMP SERIAL ; jump to serial interrupt ISR
ORG 30H
MAIN: MOV P1, #0FFH ; make P1 an input port
MOV TMOD, #22H ; timer 1,mode 2(auto reload)
MOV TH1, #0F6H ; 4800 baud rate
MOV SCON, #50H ; 8-bit, 1 stop, ren enabled
MOV TH0, #-92 ; for 5kHZ wave
MOV IE, #10010010B ; enable serial int.
SETB TR1 ; start timer 1
SETB TR0 ; start timer 0
BACK: MOV A, P1 ; read data from port 1
MOV SBUF, A ; give a copy to SBUF
MOV P2, A ; send it to P2
SJMP BACK ; stay in loop indefinitely
;----------------- SERIAL PORT ISR
ORG 100H
SERIAL: JB TI, TRANS ; jump if TI is high
MOV A, SBUF ; otherwise due to receive
MOV P0, A ; send serial data to P0
CLR RI ; clear RI since CPU doesn‟t
RETI ; return from ISR
TRANS: CLR TI ; clear TI since CPU doesn‟t
RETI ; return from ISR
END

Clearing RI and TI before the RETI instruction:

In the above program RI and TI is cleared in the ISR before RETI instruction. This is necessary since there is
only one interrupt for both receive and transmit, and the 8051 does not know who generated it. Hence programmer
has to clear the flag in the ISR. Whereas if the interrupt is due to timers or external hardware interrupt, 8051 will
clear the flag. The TCON register holds the four of the interrupt flags and SCON register has the RI and TI flags.

Dept. of ECE, TJIT Page 15

Interrupt priority:
When the 8051 is powered up, the priorities are assigned according to the following table.

If INT0 and INT1 are activated at the same time, INT0 is responded first because it has higher priority over INT1.

Setting interrupt priority with the IP register:

We can alter the sequence of interrupt priority by assigning a higher priority to any one of the interrupts. This is
done by programming a register called IP (interrupt priority).

Dept. of ECE, TJIT Page 16

Discuss what happens if interrupts INT0, TF0, and INT1 are activated at the same time. Assume priority
levels were set by the power-up reset and the external hardware interrupts are edge triggered.

Solution:
If these three interrupts are activated at the same time, they are latched and kept internally. Then the 8051 checks
all five interrupts according to the sequence listed in Table 11-3. If any is activated, it services it in sequence.
Therefore, when the above three interrupts are activated, IE0 (external interrupt 0) is serviced first, then timer 0
(TF0), and finally IE1 (external interrupt 1).

When two or more interrupt bits in the IP register are set to high, while these interrupts have a higher priority than
others, they are serviced according to the normal priority sequence.

Interrupt inside an interrupt:

When 8051 is executing an ISR belonging to an interrupt and another interrupt is activated, then a high priority
interrupt can interrupt a low priority interrupt. This is an interrupt inside an interrupt. Low priority interrupt can
be interrupted by a higher priority interrupt, but not by another low priority interrupt. Although all the interrupts
are latched and kept internally, no low priority interrupt can get the immediate attention of the CPU until 8051
has finished servicing the high priority interrupts.

Triggering the interrupt by software:

To test an ISR by way of simulation, set the interrupts high and thereby cause the 8051 to jump to the interrupt
vector table. For example, if the IE bit for timer 1 is set, an instruction such as SETB TF1 will interrupt the 8051
in whatever it is doing and force it to jump to the interrupt vector table. That is we need not wait for timer 1 to
roll over to to have an interrupt. We can cause an interrupt with an instruction that raises the interrupt flag.

Dept. of ECE, TJIT Page 17