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Complex Computing Problem - COAL

The document outlines a project for designing a memory hierarchy for a new embedded system processor, focusing on optimizing performance, cost, and complexity. It includes specific system constraints and tasks such as memory hierarchy design, cache mapping scheme, write policy management, performance analysis, and comparison with real architectures. Deliverables include presentation slides, a comprehensive written report, pseudocode for cache simulation, and various tables and diagrams.

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Alisha Khan
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8 views3 pages

Complex Computing Problem - COAL

The document outlines a project for designing a memory hierarchy for a new embedded system processor, focusing on optimizing performance, cost, and complexity. It includes specific system constraints and tasks such as memory hierarchy design, cache mapping scheme, write policy management, performance analysis, and comparison with real architectures. Deliverables include presentation slides, a comprehensive written report, pseudocode for cache simulation, and various tables and diagrams.

Uploaded by

Alisha Khan
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Department: Software Engineering Program: BS

COMPUTER ORGANIZATION AND ASSEMBLY LANGUAGE

Announced date: 15th May, 2026 Due Date: 21st June, 2026 Total Marks = 10

Complex Computing Problem (CCP)

Mapped CLO SDG Complex Problem Solving Mapped

WP2 (Depth of Analysis required)


CLO3 4&9 WP3 (Depth of Knowledge required)

Problem Statement:

You are tasked with designing a memory hierarchy for a new embedded system processor. The goal
is to optimize the balance between performance, cost, and complexity. The processor will be used
in real-time applications where rapid data access is essential.

System Constraints:

 Main Memory: 1 MB
 Cache Levels: L1 (Required), L2 (Optional)
 L1 Cache Size: Max 8 KB
 Block Size: 16 bytes
 Associativity: Configurable
 Access Latency:
o L1 Cache: 1 clock cycle
o Main Memory: 50 clock cycles
 Write Policy Options: Write-through or Write-back
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Tasks

1. Memory Hierarchy Design

 Define the structure of your memory system (L1, L2 if used, and Main Memory).
 Choose cache parameters (size, block size, associativity).
 Justify your choices considering cost vs performance trade-offs.

2. Cache Mapping Scheme

 Select and explain one of the mapping schemes


 Describe your block placement and replacement strategy

3. Write Policy & Management

 Choose and justify write-through or write-back policy.


 Discuss how the policy affects memory consistency and performance.

4. Performance Analysis

 Calculate average memory access time for your configuration using example hit rates.
 Compare performance under varying hit/miss rates.
 Identify and discuss bottlenecks and how they’re mitigated.

5. Comparison with Real Architectures

 Compare your design with an existing processor’s memory hierarchy (e.g., ARM Cortex,
Intel Core).
 Highlight differences in cache sizes, associativity, access strategies, and write policies.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Deliverables

 Presentation slides for the project demonstration


 Create proper presentation

 Written Report (Include a comprehensive report summarizing the project, its challenges,
solutions, and lessons learned.)
 Complete memory hierarchy design and parameter selection.
 Cache mapping explanation with diagrams/tables.
 Description and justification of write policy.
 Performance analysis with calculation examples.
 Comparison with real-world architecture.

 Pseudocode or Algorithm:
 Simulation of cache behavior for a data access sequence.
 Include comments to explain hit/miss handling.

 Tables and Diagrams:


 Cache organization
 Mapping examples
 Address breakdown (tag, index, offset)

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