ANALOG

CIRCUITS

ECE-VLSI
III SEM

29-07-2025
SRESTA VALASA
 COURSE DESCRIPTION
Structure and operation of MOSFET, I-V Characteristics, Channel-Length Modulation,
MODULE 1: Transconductance, MOS Device Models: Large-Signal and Small-Signal Model, PMOS
MOSFET Basics Transistor [4]

MODULE 2: Biasing, Amplifier topologies, Analysis and Design of Common-Source Amplifier, Common-
Gate Amplifier, Source Follower, Current mirror and active load, Cascode amplifier [8]
MOS Amplifiers

General considerations, MOS Differential pair: Qualitative analysis, large signal analysis,
MODULE 3: Small signal analysis and CMRR, Analysis of two stage CMOS Operational Amplifier,
Operational Amplifier: Introduction, basic block diagram, transfer characteristics of op-amp,
Differential Amplifier measurement of op-amp parameters [10]

Feedback, Polarity of feedback, Feedback topologies, Barkhausen criteria, RC oscillators

MODULE 4: (phase shift, Wein bridge etc.), LC Oscillators (Hartley, Colpitts, Clapp etc.), non-sinusoidal
MOSFET Oscillators oscillators [6]

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 COURSE DESCRIPTION
Linear applications: Inverting Amplifier, Noninverting Amplifier, Summing amplifier,
MODULE 5: adder, voltage follower, Integrator, Differentiator, voltage to current converter, current to
Op-amp applications voltage comverter, difference amplifier, Design and Verification of first and higher order low
pass, high pass, band pass, band elimination and all pass active filters.
Non-linear applications: Precision half wave and full wave rectifiers, Log and Antilog
Amplifiers, Analog multipliers and dividers, comparators, Schmitt trigger, square wave,
triangular wave generators and pulse generator, 555 timer, principles of digital to analog
converters (DAC) and ADC. [20]

Self-directed DAC types-binary weighted, R-2R, ADC types-flash, successive approximation, dual slope,
specifications of ADC and DAC
learning

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 BOOKS

Behzad Razavi, A. S. Sedra, K. C. Smith, R. L. Boylestad, L. Nashelsky,

“Fundamentals of “Microelectronic circuits”, “Electronic Devices and
Microelectronics”, Wiley, Oxford University Press, Circuit Theory”, 2009.
2013. 2011.

J. Millman, C. C. Halkias, Chetan. D. Parekh, Sergio F, Design with op amps and Analog
“Integrated Electronics”, McGraw Hill. 2010. Integrated Circuits, McGraw Hill, Fourth
edition 2016.

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 MOSFET BIASING
➢ Biasing required to set up the MOSFET operates in the desired region (as switch, amplifier etc)

Active region

1 𝑊
𝐼𝐷 = 2 µ𝑛Cox 𝑉𝐺𝑆 − 𝑉𝑡 2 (saturation)
𝐿

ID= f(VGS)

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 MOSFET BIASING
➢ In active region, MOSFET acts as a voltage-controlled current source

➢ Voltage between gate and source, VGS, controls the drain current ID

➢ Biasing enables linear amplification of MOSFET – amplification without distortion

➢ VTC- Voltage transfer characteristics – plot between output voltage versus the input voltage.

Q point- Quiescent point or DC operating

point
Q Edge of
saturation

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 MOSFET BIASING

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 MOSFET BIASING
➢ Why is biasing required ?? A,C – SWITCH
➢ What Q point signifies A- open switch (off)
C-closed switch (on)
➢ How to determine the Q point

𝑽𝑫𝑫
𝑹𝑫

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷

𝑉𝐷𝐷 𝑉𝐷𝑆
𝐼𝐷 = −
𝑅𝐷 𝑅𝐷

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 MOSFET BIASING
❑ Biasing means setting up a stable DC operating point (Q-point) for the MOSFET so that it operates in the
desired region and amplify small signals linearly

Biasing Techniques
1. Fixed-Bias

RG

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷

1 𝑊 2
𝐼𝐷 = µ𝑛Cox 𝑉𝐺𝑆 − 𝑉𝑡
2 𝐿
➢ 𝑉𝐺𝑆 = 𝑉𝐺𝑆 𝑣𝑎𝑟𝑖𝑒𝑑 𝑢𝑛𝑡𝑖𝑙 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝐼𝐷 𝑖𝑠 𝑜𝑏𝑡𝑎𝑖𝑛𝑒𝑑
➢ Once required ID is achieved, VGS is kept constant

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 MOSFET BIASING

1. Fixed-Bias

➢ Simple approach to bias a MOSFET

➢ not a good approach to bias the MOSFET
➢ Susceptible to temperature change and device parameters
➢ µ𝑛 , VT changes with temperature so ID changes
➢ (W/L), VT, Cox changes from device 1 to device 2
➢ Q point is not stable
➢ Two MOSFETs will not have same electrical parameters
➢ This method is not commonly used.

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 MOSFET BIASING

Calculate the maximum allowable gate voltage in Fig

if M1 must remain saturated. µnCox = 100 µA/V2 and
VTH = 0.4 V

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 MOSFET BIASING
2. Voltage divider-Bias / Resistive divider Bias How is this better than fixed-bias?
1 𝑊 2
𝐼𝐷 = µ𝑛Cox 𝑉𝐺𝑆 − 𝑉𝑡
2 𝐿
𝐼𝐷 = 𝐼𝐺 + 𝐼𝑆
Here, 𝐼𝐺 = 0; ℎ𝑒𝑛𝑐𝑒 𝐼𝐷 = 𝐼𝑆

Applying Thevenin’s theorem across i/p ckt

𝑅2
𝑉𝑋 = 𝑅 𝑉𝐷𝐷 = Gate Voltage
1 +𝑅2

𝑅𝑋 = 𝑅1 ∥ 𝑅2 Applying KVL across o/p ckt

𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 − 𝐼𝐷 𝑅𝑆 = 0
Applying KVL across i/p ckt
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )
𝑉𝑋 − 𝑉𝐺𝑆 − 𝐼𝐷 𝑅𝑆 = 0
𝑉𝐷𝐷 − 𝑉𝐷𝑆
𝐼𝐷 =
𝑉𝐺𝑆 = 𝑉𝑋 − 𝐼𝐷 𝑅𝑆 𝑅𝐷 + 𝑅𝑆

𝑉𝐺𝑆 = 𝑉𝑋 − 𝑉𝑆

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 MOSFET BIASING
Improved stability:
➢ By using two resistors to create a voltage divider, the gate voltage is much less sensitive to changes
in the MOSFET's parameters.
Stable Q-point:
➢ The voltage divider creates a stable gate voltage, ensuring the operating point remains relatively
constant even with temperature variations or manufacturing differences between MOSFETs.
Reduced thermal runaway:
➢ Fixed bias circuits are prone to thermal runaway, where increased temperature leads to higher drain
current, which further increases temperature, and so on. Voltage divider bias helps mitigate this
issue.
Suitable for amplifiers:

➢ The stability provided by voltage divider bias makes it a good choice for amplifier circuits where
predictable and consistent performance is essential.

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 MOSFET BIASING

2. Voltage divider-Bias / Resistive divider Bias

Determine the bias current of M1 assuming VTH = 0.5 V, µnCox = 100 µA/V2 , W/L = 5/0.18, and λ = 0.
What is the maximum allowable value of RD for M1 to remain in saturation?

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 MOSFET BIASING

3. Self-Bias/ Drain-Feedback Bias

𝑉𝐺 = 𝑉𝐷

𝑉𝐺𝑆 = 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷

1 𝑊 2
𝐼𝐷 = µ𝑛Cox 𝑉𝐺𝑆 − 𝑉𝑡
2 𝐿

Feedback in both voltage divider and self bias tries to stabilize the operating point

➢ Offers higher stability against variations in transistor parameters and temperature compared to voltage divider
bias.
➢ The feedback resistor (RG) creates a loop that automatically adjusts the gate-source voltage (Vgs) to
compensate for changes in drain current (Id), helping to maintain a more stable operating point.

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 MOSFET BIASING

Calculate the drain current ofM1 if µnCox = 100 A=V2, VTH = 0.5 V, and λ
= 0. What value of RD is necessary to reduce ID by a factor of two?

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 Amplifier Topologies
1. Common-Source Amplifier Source common between input and output

2. Common – Gate Amplifier Gate common between input and output

3. Common- Drain Amplifier Drain common between input and output

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 Amplifier Topologies
Amplifier

Input Resistance, Ri Gain, 𝑨𝒗 Output Resistance, R0

➢ Resistance seen by the ➢ Ratio of the output voltage ➢ Resistance seen by the
input signal at the gate to input voltage input signal at the drain
terminal of the MOSFET terminal of the MOSFET

➢ High Ri means the ➢ Shows signal ➢ Low R0 is better for the

amplifier draws almost no amplification power delivery of the load
current from the signal
source

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 Amplifier Topologies

Design Parameter Voltage Amplifier Current Amplifier

High – to avoid loading the source

Low – to allow more current to be
Input Resistance and ensure maximum voltage is
drawn from the input source
sensed

High – to maintain a consistent

Low – so that most of the output
Output Resistance output current across varying
voltage reaches the load
load resistances

Voltage Gain – amplifies the Current Gain – increases the

Gain Type
voltage level of the input signal current delivered to the load

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 Amplifier Topologies

MOSFET in
saturation can act
as constant current
sources

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 Amplifier Topologies
Common-Source (CS) Amplifier IG=0
G D

S
Ri R0

𝑅𝑖 = ∞
𝑅0 = 𝑅𝐷

𝑉0 = −𝑔𝑚 𝑉1 𝑅𝐷 𝑉𝑖 = 𝑉1

Negative sign shows that the 𝑉0

output is 180° out of phase 𝐴𝑣 = = −𝑔𝑚 𝑅𝐷 Gain depends on gm and RD
𝑉𝑖
with the input

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 Amplifier Topologies
Calculate the small-signal voltage gain of the
CS stage if ID = 1mA, µnCox =100 µA/V2, VTH = 0.5
V, and λ = 0.

G D

= 1KΩ

𝐴𝑣 = −𝑔𝑚 𝑅𝐷 What happens when we increase RD?

𝑨𝒗 = 𝟑. 𝟑𝟑
𝜕𝐼𝐷
𝑔𝑚 = ቤ
𝜕𝑉𝐺𝑆 𝑉 𝑐𝑜𝑛𝑠𝑡.
𝐷𝑆

𝑊 1
𝑔𝑚 = 2 µ𝑛Cox 𝐼𝐷 = Ω-1
𝐿 300

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 Amplifier Topologies
G D

= 1KΩ

What happens when we increase RD?

VTH = 0.5 V

𝐼𝐷 L
𝑉𝐺𝑆 = 𝑉𝑇 + = 1.1𝑉
µ𝑛 𝐶𝑂𝑋 𝑊

𝐴𝑣 = −𝑔𝑚 𝑅𝐷 𝑨𝒗 = 𝟑. 𝟑𝟑 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 1𝑉

𝑊 1
𝑔𝑚 = 2 µ𝑛Cox 𝐼𝐷 = Ω-1 For RD= 1K, VDS ≥ 𝑉𝐺𝑆 − 𝑉𝑇
𝐿 300

If we increase RD= 1.2 K, VDS = 0.6 𝑉 < 𝑉𝐺𝑆 − 𝑉𝑇

MOSFET may not be in saturation so cannot act as amplifiers

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 Amplifier Topologies
With Channel Length Modulation

G D

Ri S R0

Resistance as a load :
𝑅𝑖 = ∞
𝑅0 = 𝑟𝑜 ‖𝑅𝐷 • Requires large area, making them unsuitable for
compact IC designs.
• Difficult to maintain accurate and consistent
𝑉0 = −𝑔𝑚 𝑉1 𝑟𝑜 ‖𝑅𝐷 𝑉𝑖 = 𝑉1 resistance values.

𝑉0
𝐴𝑣 = = −𝑔𝑚 𝑟𝑜 ‖𝑅𝐷
𝑉𝑖

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 Amplifier Topologies
CS Stage With Current-Source Load 𝑅𝑖 = ∞

𝑅0 = 𝑟𝑜 ‖𝑅𝐷 , 𝑅𝐷 = ∞

𝑅0 = 𝑟0

𝑉𝑖 = 𝑉1 𝑉0 = −𝑔𝑚 𝑉1 𝑟0

𝑽𝟎
𝑨𝒗 = = −𝒈𝒎 𝒓𝟎
𝑽𝒊

The trade-off between the voltage gain and the voltage headroom can be relaxed by replacing the load resistor
with a current source

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 Amplifier Topologies

r02

r01

𝐴𝑣 = −𝑔𝑚2 𝑟𝑜2 ‖𝑟01

𝐴𝑣 = −𝑔𝑚1 𝑟𝑜1 ‖𝑟02
𝑅𝑖 = ∞

𝑅0 = 𝑟𝑜1 ‖𝑟02

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 Amplifier Topologies
Diode-connected load
Diode-connection

D
G
S
𝑉𝐺𝑆 = 𝑉𝐷𝑆

𝑉𝐷𝑆
𝑖𝐷 = 𝑔𝑚 𝑉𝐺𝑆 +
𝑟0
1
𝑖𝐷 = (𝑔𝑚 + )𝑉𝐷𝑆
𝑟0
1
𝑉𝐷𝑆 1 𝑔𝑚 𝑟0
= =
𝑖𝐷 1 1
+ 𝑔
𝑟0 𝑚 𝑔𝑚 + 𝑟0
1
= ฮ𝑟
1 𝑔𝑚 0
𝐴𝑣 = −𝑔𝑚1 ฮ𝑟 ‖𝑟
𝑔𝑚2 02 01

𝒈
If CLM is not considered, then 𝑨𝒗 = − 𝒈𝒎𝟏
𝒎𝟐

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 Amplifier Topologies
CS stage with source resistance RS 𝑉1 = 𝑉𝐺𝑆
G D
+
Negative Feedback

Ri S R0
-

𝑉𝑖 = 𝑉1 +𝑔𝑚 𝑉1 𝑅𝑆 = 1 + 𝑔𝑚 𝑅𝑆 𝑉1
𝑅𝑖 = ∞ Rs can control the magnitude of
𝑅0 = 𝑅𝐷 𝑉𝑖 the signal VGS and thereby ensure
𝑉1 = that VGS does not become too
1 + 𝑔𝑚 𝑅𝑆 large and cause unacceptably
𝑉0 = −𝑔𝑚 𝑉1 𝑅𝐷 high nonlinear distortion.

𝑉0 −𝑔𝑚 𝑅𝐷
𝐴𝑣 = =
𝑉𝑖 1 + 𝑔𝑚 𝑅𝑆

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 Amplifier Topologies
CS With Biasing Small signal analysis

Input coupling capacitance 1. Short the capacitances.

2. Make VDD to ground.
3. Take the small signal equivalent model

R1 R2
𝑅𝑖 = 𝑅1 ‖𝑅2
𝑅0 = 𝑅𝐷
Ri R0
−𝑔𝑚 𝑅𝐷
𝐴𝑣 =
1 + 𝑔𝑚 𝑅𝑆

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 Amplifier Topologies
Gate resistance

R1 R2

R0
Ri

𝑅𝐺 +𝑅1 ‖𝑅2
𝑅𝑖 = 𝑅1 ‖𝑅2 𝑉𝑖 = 1 + 𝑔𝑚 𝑅𝑆
𝑅1 ‖𝑅2
𝑅0 = 𝑅𝐷

𝑉0 = −𝑔𝑚 𝑉1 𝑅𝐷
𝑅1 ‖𝑅2 −𝑔𝑚 𝑅𝐷
𝐴𝑣 =
𝑅𝐺 + 𝑅1 ‖𝑅2 1 + 𝑔𝑚 𝑅𝑆
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 Amplifier Topologies
Bypass capacitor

Find 𝑹𝒊 , 𝑹𝟎 and 𝑨𝒗

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 Amplifier Topologies
Common-Gate (CG) Amplifier
Output Impedance
𝑅𝑜 = 𝑅𝐷

Input Impedance 𝑉0 = − 𝑔𝑚 𝑉1 𝑅𝐷

𝑉𝑖𝑛
𝑅𝑖𝑛 = VDD − IDRD, must remain above Vb − VTH to ensure M1 is saturated.
𝐼𝑖𝑛

𝐼𝑖𝑛 + 𝑔𝑚 𝑉1 = 0 Gain
𝐼𝑖𝑛 = −𝑔𝑚 𝑉1 𝐴𝑣 = 𝑔𝑚 𝑅𝐷

𝑉𝑖𝑛 = − 𝑉1

Vin Iin
1
𝑅𝑖𝑛 =
𝑔𝑚 Gain depends on RD , suffers from
voltage headroom-gain trade-offs like
Current gain, 𝐴𝑣 =
𝐼𝑜
=1 that of the CS amplifier
𝐼𝑖

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 Amplifier Topologies
CG Amplifier with source resistance 𝑉𝑋 = − 𝑉1 𝑉0 = − 𝑔𝑚 𝑉1 𝑅𝐷
1
𝑅𝑖𝑛 = 𝑅𝑜 = 𝑅𝐷
𝑔𝑚

1
𝑔𝑚
𝑉𝑋 = 1 𝑉𝑖𝑛
𝑅𝑆 +
𝑔𝑚

1
𝑉𝑋 = 1+𝑔 𝑉𝑖𝑛
𝑚 𝑅𝑆

𝑉0 𝑔𝑚 𝑅𝐷 𝑅𝐷
𝐴𝑣 = = =
𝑉𝑖𝑛 1 + 𝑔𝑚 𝑅𝑆 𝑅 + 1
𝑆 𝑔 𝑚

Gain same as CS amplifier with source resistance

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 Amplifier Topologies
The voltage divider consisting of R1 and R2 neglected because Gate is grounded
𝑉𝑋 = − 𝑉1 𝑉0 = − 𝑔𝑚 𝑉1 𝑅𝐷
1
𝑅𝑖𝑛 = 𝑅𝑜 = 𝑅𝐷
𝑔𝑚

1
ฮ𝑅
𝑔𝑚 3
𝑉𝑋 = 1 𝑉𝑖𝑛
𝑅𝑆 +𝑔 ฮ𝑅3
𝑚

1
𝑔𝑚 ฮ𝑅3
𝐴𝑣 = (𝑔𝑚 𝑅𝐷 )
1
𝑅𝑆 + ฮ𝑅
𝑔𝑚 3

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 Amplifier Topologies
Common-Drain (CD) Amplifier

Output is sensed at source, hence, also known as Source Follower

𝑉𝑖𝑛 = 𝑉1 + 𝑉𝑜𝑢𝑡
𝑉𝑜𝑢𝑡 = 𝑔𝑚 𝑉1 𝑟0 ‖𝑅𝐿
𝑉𝑖𝑛 = 𝑉1 (1 + 𝑔𝑚 𝑟0 ‖𝑅𝐿 )

𝑔𝑚 𝑟0 ‖𝑅𝐿
𝐴𝑣 =
1 + 𝑔𝑚 𝑟0 ‖𝑅𝐿 )

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 Current mirror
➢ The biasing techniques studied for MOS amplifiers prove inadequate for high-performance microelectronic circuits.
➢ For example, the bias current of CS stages is a function of the supply voltage—a serious issue because in practice,
this voltage experiences some variation.
➢ The rechargeable battery in a cellphone or laptop computer, for example, gradually loses voltage as it is discharged,
thereby mandating that the circuits operate properly across a range of supply voltages.
➢ Another critical issue in biasing relates to ambient temperature variations.
➢ A cellphone must maintain its performance at −20°C in Finland and +50 °C in Saudi Arabia.

A MOS current source biased by means of a resistive divider suffers from

dependence on VDD and temperature.

Since both the mobility and the threshold voltage vary with temperature, I1 is not
constant even if VGS is.

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 Current mirror
➢ An elegant method of creating supply- and temperature-independent voltages and currents exists and appears in
almost all microelectronic systems.
➢ Called the “bandgap reference circuit” and employing several tens of devices.

➢ In order to avoid supply and temperature dependence, a bandgap reference

can provide a “golden current” while requiring a few tens of devices.
➢ We must therefore seek a method of “copying” the golden current without
duplicating the entire bandgap circuitry. Current mirrors serve this purpose.
➢ Icopy = IREF

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 Current mirror

The black box must generate VX such that

where channel-length modulation is neglected. Thus, the black box must satisfy the following input (current)/output
(voltage) characteristic:

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 Current mirror
➢ That is, it must operate as a “square-root” circuit.
➢ A diode-connected MOSFET provides such a characteristic [Fig. 9.35(b)], thus arriving at the NMOS current mirror
depicted in Fig. 9.35(c).
➢ The drain currents of the two transistors can be expressed as:

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 Cascode amplifier

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