UNIT 3 - Detailed Notes on Testing and Testability of

Sequential Circuits

Introduction to Sequential Circuit Testing

Sequential circuits contain memory elements such as flip-flops and latches.
Unlike combinational circuits, the output depends on both present inputs and previous states.
Testing sequential circuits is more difficult because of feedback paths and internal states.

Objectives of testing:
• Detect manufacturing defects
• Improve reliability
• Increase fault coverage
• Reduce testing cost
• Ensure proper state transitions

Sequential Circuits as Iterative Combinational Circuits

A sequential circuit can be represented as multiple copies of a combinational circuit across time frames.
This process is known as iterative logic array representation or time-frame expansion.

Advantages:
• Simplifies sequential ATPG
• Allows use of combinational ATPG algorithms
• Easier fault analysis

Disadvantages:
• High computational complexity
• Large memory requirements

State Table Verification

State table verification checks whether all state transitions and outputs are correct.

A state table contains:

• Present state
• Input
• Next state
• Output

Verification Process:
1. Apply input sequence
2. Observe next state
3. Compare with expected state
4. Verify output correctness

Applications:
• FSM verification
• Protocol controller testing
• Sequential logic validation
Test Generation Based on Circuit Structure
Structural test generation analyzes the circuit structure such as:
• Logic gates
• Flip-flops
• Feedback loops
• Signal paths

Common faults:
• Stuck-at faults
• Bridging faults
• Delay faults

Advantages:
• Suitable for ATPG automation
• Effective for VLSI testing

Design for Testability (DFT)

DFT techniques improve controllability and observability of internal nodes.

Goals of DFT:
• Simplify testing
• Improve fault detection
• Reduce ATPG complexity
• Increase test coverage

Major DFT techniques:

• Ad hoc methods
• Scan path design
• Partial scan
• Boundary scan

Ad Hoc Design Rules

Ad hoc methods are informal design guidelines to improve testability.

Important rules:
• Avoid asynchronous sequential logic
• Provide reset capability to all flip-flops
• Minimize feedback loops
• Separate clock and data signals
• Improve internal observability
• Use modular design

Advantages:
• Simple implementation
• Low area overhead

Disadvantages:
• Limited fault coverage
• Non-systematic approach
Scan Path Technique (Scan Design)
Scan design is the most widely used sequential testing technique.

Working Principle:
• Flip-flops are connected as a shift register during test mode.
• Internal states can be shifted in and shifted out.

Scan Testing Procedure:

1. Shift test vector into scan chain
2. Apply clock pulse
3. Capture circuit response
4. Shift response out for observation

Advantages:
• High fault coverage
• Simplifies sequential testing
• Converts sequential testing into combinational testing

Disadvantages:
• Additional hardware overhead
• Increased power consumption

Partial Scan Technique

In partial scan, only selected flip-flops are included in scan chains.

Need for partial scan:

• Reduce area overhead
• Improve speed
• Reduce routing complexity

Advantages:
• Lower hardware cost
• Better performance than full scan

Disadvantages:
• Lower fault coverage
• Complex ATPG

Boundary Scan (JTAG)

Boundary scan is defined by IEEE 1149.1 standard and is used for PCB and IC testing.

Important JTAG Signals:

• TDI – Test Data Input
• TDO – Test Data Output
• TCK – Test Clock
• TMS – Test Mode Select

Advantages:
• No physical probing required
• Easy board-level testing
• Supports debugging and programming

Applications:
• FPGA testing
• Processor debugging
• Embedded systems
• PCB testing

Comparison of Sequential Testing Techniques

Sequential testing methods differ in complexity, hardware overhead, and fault coverage.

• Ad hoc methods provide low-cost testing support.

• Scan path technique provides high fault coverage.
• Partial scan reduces overhead.
• Boundary scan enables board-level testing.

Conclusion
Testing and testability of sequential circuits are essential in modern VLSI systems.
Techniques such as scan path testing, partial scan, and boundary scan improve controllability and observability of
internal states.
Design-for-testability methods help achieve reliable operation, high fault coverage, and simplified testing in complex
digital systems.

Comparison Table
Technique Advantage Limitation

Ad Hoc Rules Simple and low cost Limited coverage

Scan Path High fault coverage Hardware overhead
Partial Scan Reduced area overhead Moderate fault coverage
Boundary Scan Board-level testing Extra circuitry