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Microcontroller and Embedded System

The document outlines the examination structure for the Sixth Semester B.E./B.Tech. Degree Examination in Microcontrollers and Embedded Systems, Embedded System Design, and VLSI Design and Testing for Dec. 2025/Jan. 2026. It includes various modules with questions covering topics such as RISC vs. CISC, ARM architecture, embedded system characteristics, CMOS logic, and design principles. Students are required to answer five full questions, selecting one from each module.
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© All Rights Reserved
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Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
6 views8 pages

Microcontroller and Embedded System

The document outlines the examination structure for the Sixth Semester B.E./B.Tech. Degree Examination in Microcontrollers and Embedded Systems, Embedded System Design, and VLSI Design and Testing for Dec. 2025/Jan. 2026. It includes various modules with questions covering topics such as RISC vs. CISC, ARM architecture, embedded system characteristics, CMOS logic, and design principles. Students are required to answer five full questions, selecting one from each module.
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

BCO601

pm
USN

Sixth Semester B.E./[Link]. Degree Examination, Dec.2025/Jan.2026

4
Microcontrollers and Embedded Systems

:2
Time: 3 hrs. Max. Marks: 100

6
:0
Note: 1. Answer any FIVE full questions, choosing ONE full question from each module.
2. M : Marks , L: Bloom’s level , C: Course outcomes.

01

L
-B
Module – 1 M L C
Q.1 a. Differentiate between: 10 L2 CO1

5
i) RISC and CISC

02

L
ii) Microprocessor and micro controller

-B
-2
b. With a neat diagram, explain embedded system hardware. 10 L2 CO1

L
12
OR

-B
Q.2 a. Explain in detail about Current Program Status Register (CPSR). 10 L2 CO1
7-

b. Define Pipelining. Explain how it helps the program execution.


L 10 L2 CO1
-1

-B
U

Module – 2
Q.3 a. Explain about load store instructions in ARM with an example. 10 L2 CO2
VT

m
-B

b. Write a program to find the sum of 10 integer numbers. 10 L3 CO2


0p
OR

L
L

:4

Q.4 a. Explain how instruction is scheduled in ARM. -B 10 L2 CO2


-B

41

b. Write a note on profiling and cycle counting. 10 L1 CO2


L
L

-B

Module – 3
-B

01

Q.5 a. Explain the classification of embedded system. 10 L2 CO3


L
L

25

b. Write a note on core of an embedded system in detail. 10 L1 CO3


-B
-B

OR
20

Q.6 a. Explain the purpose of embedded system used in various domains. 10 L2 CO3
L
BL

-B
2-

b. Explain the following: 10 L2 CO3


i) I2C BUS
-1

ii) Watch dog timer


17

-B

Module – 4
Q.7 a. Explain the characteristics of embedded system. 10 L2 CO4
L
-B

b. Explain the fundamental issues in hardware software design. 10 L2 CO4


L

1 of 2
-B
L
-B
BL
BCO601

pm
OR
Q.8 a. What are the operational and non operational quality attributes of an 10 L1 CO4
embedded system.

4
:2
b. With a neat diagram, explain how source file to object file translation takes 10 L2 CO4
place in high level language based firmware development.

6
:0
Module – 5

01
Q.9 a. With a neat diagram, explain operating system architecture. 10 L2 CO5

L
-B
b. Explain the steps involved in selecting RTOs. 10 L2 CO5

5
02

L
OR

-B
Q.10 a. Write a note on multiprocessing and multitasking. 10 L1 CO5
-2
b. Explain the following: 10 L2 CO5

L
12
i) Simulator, Emulator

-B
ii) Boundary scan
7-

*****
L
-1

-B
U
VT

m
-B

0p

L
L

:4

-B
-B

41

L
L

-B
-B

01

L
L

25

-B
-B

20

L
BL

-B
2-
-1

L
17

-B
L
-B
L
-B

2 of 2
L
-B
BL
BEC601/BTE601/BVL601

pm
USN

Sixth Semester B.E./[Link]. Degree Examination, Dec.2025/Jan.2026

5
Embedded System Design

6 :2
Time: 3 hrs. Max. Marks: 100

:0
Note: 1. Answer any FIVE full questions, choosing ONE full question from each module.
2. M : Marks , L: Bloom’s level , C: Course outcomes.

01

L
-B
Module – 1 M L C
Q.1 a. Define Embedded System. Explain the six purpose of Embedded system 8 L2 CO3

5
with an example for each.

02

L
-B
b. Bring out the differences between RISC and CISC. 4 L2 CO3
c.
-2
Mention all the cores around which an embedded system is built. Discuss 8 L2 CO3

L
12
any two in detail.

-B
OR
7-

Q.2 a. What are the different types of memories need in Embedded System 8 L2 CO3
Design? Explain the role of each. L
-1

-B
b. With a neat interfacing diagram, explain Inter Integrated Circuit (I2C) Bus. 6 L2 CO3
U
VT

c. Explain the following circuits in an Embedded System. 6 L2 CO3


L

i) Brown out Protection Unit m


-B

ii) Watch Dog Timer (WDT)


1p

L
Module – 2
L

:0

Q.3 -B
a. Explain the different characteristics of Embedded System in detail. 8 L2 CO4
-B

42

b. Explain the different types of serial interface bus used in Automotive 6 L2 CO4
L

Communication.
L

-B
-B

01

c. Compare CDFG and DFG with an example. 6 L4 CO4


OR
L
L

25

Q.4 a. Explain the different fundamental design approaches used in Hardware 8 L2 CO4
-B
-B

Software Co-design.
20

b. With FSM model, explain the design and operation of Automatic 6 L2 CO4
L
BL

Tea/Coffee Vending Machine.


-B
2-

c. Explain with a neat diagram, the process of converting assembly language 6 L2 CO4
-1

to machine language.
L
17

-B

Module – 3
Q.5 a. With a neat diagram, explain the different functions of operating system. 8 L2 CO5
L

b. Explain in detail the structure, memory organization and state transitions of 8 L2 CO5
-B

the process.
c. Differentiate between Hard Real Time System and Soft Real Time System 4 L4 CO5
with an example for each.
L
-B

1 of 2
L
-B
BL
BEC601/BTE601/BVL601

pm
OR
Q.6 a. Three process with process IDS P1, P2 and P3 are having estimated 7 L3 CO5
completion time of 10, 5, 7 milliseconds respectively. A new process

5
P4 with estimated completion time of 2 ms enter the READY queue after

:2
2 ms. Calculate the waiting time and turnaround time for each process and

6
the average waiting time and turnaround time (assuming no I/O waiting for
the processes) in SJF scheduling algorithm.

:0
01
b. Explain the concept of Dead lock with an example. Also explain the 5 L2 CO5

L
methods of handling Dead lock.

-B
5
c. Discuss the different techniques for embedding the firmware into the target 8 L2 CO5

02
processor.

L
-B
-2 Module – 4
Q.7 a. With a neat diagram, explain the four main hardware components of ARM- 8 L2 CO1

L
12
based embedded device.

-B
b. Discuss about RISC design philosophy. 6 L2 CO1
7-

c. Explain the factors that make the ARM instruction set suitable for
L 6 L2 CO1
-1

embedded applications.
-B
U

OR
VT

Q.8 a. Explain ARM core data flow model with neat diagram. 8 L2 CO1
m
-B

b. Explain the different processor modes of ARM processor with the help of
1p
6 L2 CO1
ARM register set.

L
L

:0

-B
With suitable diagrams, explain the following hardware extensions of ARM
-B

c. 6 L2 CO1
code.
42

i) Cache and tightly coupled memory


L
L

ii) Memory Management


:

-B
-B

01

Module – 5
Q.9 a. Explain with diagram, barrel shifter operation in ARM processor. Give an 8 L2 CO2
L
L

25

example.
-B
-B

20

b. Explain the following instructions with example 6 L2 CO2


i) UMLAL ii) RSC iii) SWI iv) SWPB.
L
BL

-B
2-

c. Develop an assembly language program to count the number of ones and 6 L3 CO2
-1

zeros in two consecutive memory locations.


L
17

OR
-B

Q.10 a. Explain single register load-store instructions with example. 8 L2 CO2


L

b. Explain both forward and backward branch instructions with an example. 6 L2 CO2
-B

c. Develop an assembly language program to find the largest/smallest number 6 L3 CO2


in an array of 32 bit numbers.
L
-B

*****

2 of 2
L
-B
BL
pm
USN BEC602

Sixth Semester B.E./[Link]. Degree Examination, Dec.2025/Jan.2026

2
:2
VLSI Design and Testing

3
Time: 3 hrs. Max. Marks: 100

:2
Note: 1. Answer any FIVE full questions, choosing ONE full question from each module.

01

L
2. M : Marks , L: Bloom’s level , C: Course outcomes.

-B
Module – 1 M L C

5
Q.1 a. Implement CMOS logic for the following compound gates. 10 L3 CO1

02

L
i) F = A (B  C)  DE

-B
ii) F = (A  B  C) D-2
b. Implement and explain 2 i/p multiplexes using TG and also mention 10 L3 CO2

L
12
advantages of TG.

-B
2-

OR
L
a. Design flip-flop using multiplexes and inverter.
-2

Q.2 08 L3 CO2
-B
b. Illustrate structural representation for 2 i/p NAND gates by adding 04 L3 CO2
U

performance parameter.
VT

c. Develop physical symbolic layout for the following. 08 L3 CO2


L

i) Inverter ii) Transmission Gate m


-B

5p
Module – 2

L
L

Q.3 a. Explain the working principle of nMOS enhancement nmos transistor. 10 L2 CO1
:0

-B
-B

b. Define Body Effect. Illustrate how body effect alters the Vt and give 05 L3 CO1
39

mathematical expressions.
L

c. Discuss n / p ratio effect on transfer characteristics. 05 L3 CO1


L

-B
-B

01

OR
Q.4 a. Draw schematic diagram of CMOS inverter and explain its D C Transfer 12 L3 CO1
L
L

25

characteristics.
-B
-B

b. Illustrate the mechanism of Latch-up in CMOS and preventive measures. 08 L3 CO1


20

Module – 3
L

Q.5 a. Explain czochoalki method for wafer processing. 06 L2 CO1


BL

-B
2-

b. Discuss Lamda-based p-well design rules. 06 L2 CO1


c. Explain the Twin-tub process. 08 L3 CO1
-1

L
22

OR
-B

Q.6 a. Describe switching characteristics of CMOS inverter with equivalent 10 L3 CO3


circuits to determine fall and rise time.
L

b. Explain in brief scaling principles of MOS transistor dimensions. 10 L2 CO1


-B

Module – 4
Q.7 a. What are the advantages of Dynamic CMOS logic and explain the working 08 L3 CO4
L

of dynamic CMOS inverter with timing diagrams.


-B

b. Realize 2 inputs XOR / XNOR gate using cascode voltage switch logic. 04 L3 CO4
c. Implement 4 – way switch logic using Transmission gate and write layout 08 L3 CO4
L

version of CMOS logic.


-B

1 of 2
BL
BEC602
OR

pm
Q.8 a. Draw star connection for CMOS inverter layout optimization and mention 06 L3 CO4
its advantages.

2
b. Find Euler’s path for the function Z  (A  B)  CD and draw 06 L3 CO4

:2
corresponding layout.
c. Write short notes on : 08 L2 CO4

3
i) ESD Protection

:2
ii) Tristate and Bidirectional Pads.

01

L
-B
Module – 5
Q.9 a. Implement AOI based clocked NOR SR Latch circuit with waveforms. 10 L3 CO5

5
b. Illustrate typical design flow of a contemporary and an ideal approach for 10 L3 CO5

02

L
designing system.

-B
-2 OR

L
12
Q.10 a. Illustrate J – K flip – flop with Nand gate JK latches with waveforms. 10 L3 CO5

-B
b. Write short notes on : 10 L2 CO1
2-

i) Adhoc Testing
ii) Self Test and Build in Test.
L
-2

-B

U
VT

m
-B

5p

L
L

:0

-B
-B

39

L
L

-B

2 of 2
-B

01

L
L

25

-B
-B

20

L
BL

-B
2-
-1

L
22

-B
L
-B
L
-B
L
-B
BL
pm
USN BEC654C/BTE654C

Sixth Semester B.E./[Link]. Degree Examination, Dec.2025/Jan.2026

1
:1
Electronic Communication System

0
Time: 3 hrs. Max. Marks: 100

:2
Note: 1. Answer any FIVE full questions, choosing ONE full question from each module.

01

L
2. M : Marks , L: Bloom’s level , C: Course outcomes.

-B
Module – 1 M L C

6
Q.1 a. Briefly, explain what are the different modes of communications. 6 L2 CO1

02

L
b. Explain with a neat block diagram the element of electronic and 10 L2 CO1

-B
communication system. -2

L
An RF amplifier has an input signal power of 1W and delivers the output 4
01
c. L3 CO1

-B
signal with 10W power. Determine its power gain in decibels (dB).
5-

OR
L
a. With a neat block diagram, explain the element of digital communication
-0

Q.2 8 L2 CO1
-B
system.
U

b. Define and explain frequency division multiplexing. 8 L2 CO1


VT

m
-B

c. Determine the antenna gain of a reflector dish antenna having an effective 4 L3 CO1
1p
area of 0.56, operating at 12 GHZ.

L
L

Module – 2
:1

-B
-B

Q.3 a. Define and explain amplitude modulation with necessary expression and 10 L2 CO2
34

waveforms.
L
L

b. Derive the expression for the total power in a single tone AM signal. 10 L3 CO2
:

-B
-B

01

OR
Q.4 a. Show how the modulation index can be computed by displaying the AM 10 L3 CO2
L
L

26

envelope on an oscilloscope.
-B
-B

20

b. Define transmission efficiency of AM signal and derive its expression. 6 L3 CO2


L
BL

c. Describe the limitations of amplitude modulation. 4 L2 CO2


-B
1-

Module – 3
-0

Q.5 a. Define Pulse Amplitude Modulation (PAM) with necessary diagrams. 10 L2 CO3
L
05

Explain the different types of sampling in PAM.


-B

b. Explain the generation and demodulation of Pulse Position Modulation 10 L2 CO3


L

(PPM)
-B

OR
Q.6 a. State and prove sampling theorem. 10 L3 CO3
L

b. Explain the generation and detection of Pulse Width Modulation (PWM)


-B

10 L2 CO3
L
-B

1 of 2
BL
BEC654C/BTE654C

pm
Module – 4

1
Q.7 a. Define and state and properties of entropy. 5 L2 CO4

:1
b. Describe the four basic types of redundancy checks. 12 L2 CO4

0
:2
c. A communication system consists of 6 messages with probabilities 1/8, 1/8, 3 L3 CO4

01

L
1/8, 1/8, 1/4 and 1/4 respectively. Determine the entropy of the system.

-B
OR

6
Q.8 a. With a neat block diagram, explain BPSK modulator and demodulator. 8 L2 CO4

02

L
-B
b. With necessary expressions and waveforms, explain Amplitude Shift
-2 6 L2 CO4
Keying (ASK).

L
01

-B
c. Explain QPSK with necessary expression and the constellation diagram. 6 L2 CO4
5-

Module – 5
L
-0

Q.9 a. Describe the frequency reuse concept in cellular communications. 8 L2 CO5


-B
U

b. Draw the cell structure in cellular communication and explain. 8 L2 CO5


VT

m
-B

c. A cellular communication service area is covered with 12 clusters having 4 L2 CO5


1p
7 cells in each cluster and 16 channels assigned in each cell. Determine :
i) Number of channels cluster ii) System capacity.

L
L

:1

-B
-B

OR
34

Q.10 a. Discuss the advantages and disadvantages of wireless communications. 10 L2 CO5


L
L

-B
-B

01

b. List and briefly explain the main areas of wireless applications. 10 L2 CO5

*****
L
L

26

-B
-B

20

L
BL

-B
1-
-0

L
05

-B
L
-B
L
-B
L
-B

2 of 2
BL

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