Advanced Computer
Architecture
Comprehensive Study Notes
Unit 6 — Topics 6.1 – 6.6
Harvard Architecture • Accumulator & Register-Based • Control Units
RISC & CISC • Multiprocessing / Multitasking • DSP
Section Topic
6.1 Harvard Architecture
6.2 Accumulator-Based and Register-Based Architecture
6.3 Hardwired and Microprogrammed Control Unit
6.4 RISC and CISC
6.5 Introduction to Multiprocessing / Multitasking
6.6 Digital Signal Processor (DSP)
6.1 Harvard Architecture
Most early computers used a single memory space for both program
instructions and data. Harvard architecture breaks this rule by using two
separate memory systems — one for instructions and one for data — with
two independent buses connecting them to the CPU.
What is Von Neumann Architecture? (The Old Way)
Before Harvard, all computers were Von Neumann machines. In this design,
instructions and data share the same memory and the same bus (path to the
CPU). This causes a problem called the Von Neumann Bottleneck: the CPU
can't fetch the next instruction while it's reading/writing data — they have to wait
in line.
Figure 6.1 — Von Neumann (left) vs Harvard Architecture (right)
Key Difference — Two Buses, Two Memories
Feature Von Neumann Harvard
Memory Single shared Separate (Instr. + Data)
Buses One bus Two independent buses
Speed Slower (bottleneck) Faster (parallel access)
Complexity Simple More complex hardware
Used In General PCs (modified) Microcontrollers, DSPs
Modified Harvard Architecture
Modern CPUs use a Modified Harvard Architecture. They have separate L1
instruction cache and L1 data cache (Harvard-style), but a unified main memory
(Von Neumann-style). This gives the best of both worlds — speed from cache
separation, simplicity from unified main memory.
• CPU fetches instruction from Instruction Cache
• Simultaneously reads/writes data from Data Cache
• Both caches are backed by the same unified RAM
Real-World Examples
• Pure Harvard: PIC microcontrollers, AVR (Arduino), DSP chips
• Modified Harvard: Intel Core i7/i9, ARM Cortex-A (your smartphone CPU)
6.2 Accumulator-Based and
Register-Based Architecture
This topic is about where the CPU temporarily stores operands (the numbers
it is currently working on) during arithmetic and logic operations. Two main
strategies exist.
Figure 6.2 — Accumulator-Based (left) vs Register-Based Architecture (right)
6.2.1 Accumulator-Based Architecture
The CPU has one special register called the Accumulator (ACC). Every
arithmetic operation automatically uses the ACC as one of the operands, and
the result is always stored back in the ACC.
How it works — Example: A + B
Step Assembly Instruction Action
1 LOAD A Load value A into ACC
2 ADD B ACC = ACC + B (result in ACC)
3 STORE C Store ACC into memory location C
• Advantage: Very simple hardware — fewer transistors, cheaper to build
• Disadvantage: More memory accesses needed — slow, many
LOAD/STORE instructions
• Used in: Early Intel 8080, Zilog Z80, 6502 (old Nintendo)
6.2.2 Register-Based Architecture (General
Purpose Registers)
The CPU has multiple general-purpose registers (R0–R15 or more). Any
register can hold either an operand or a result. Instructions explicitly name
which registers to use.
How it works — Example: A + B
Step Assembly Instruction Action
1 MOV R1, A Load A into register R1
2 MOV R2, B Load B into register R2
3 ADD R3, R1, R2 R3 = R1 + R2
4 MOV C, R3 Store R3 into memory C
• Advantage: Faster — fewer memory accesses, more parallelism possible
• Disadvantage: Longer instructions (need to specify register numbers), more
complex hardware
• Used in: All modern CPUs — x86-64, ARM, MIPS, RISC-V
6.3 Hardwired and
Microprogrammed Control Unit
The Control Unit (CU) is the brain of the CPU. It reads instructions and
generates the control signals that tell every other part of the CPU what to do
(when to read memory, when to write, when to activate the ALU, etc.). There
are two ways to design a control unit.
Figure 6.3 — Hardwired (left) vs Microprogrammed Control Unit (right)
6.3.1 Hardwired Control Unit
Control signals are generated by a fixed combinational logic circuit — actual
physical gates wired together. The instruction opcode directly triggers specific
gates, which output the correct control signals. There is NO memory involved.
Speed ■ Very fast — direct logic, no lookup needed
Flexibility ■ Rigid — cannot change without redesigning hardware
Complexity Complex to design and debug
Cost More expensive for complex ISA
Used For RISC processors (simple instruction sets)
6.3.2 Microprogrammed Control Unit
Instead of gates, control signals are stored as microinstructions inside a
special ROM called the Control Memory. When the CPU receives an
instruction, it looks up the corresponding microprogram and executes its
micro-operations one by one.
Key Terms:
Microinstruction: One row in Control Memory — specifies which control
signals to activate
Microprogram: A sequence of microinstructions that implements one machine
instruction
Control Memory: A ROM inside the CPU that stores all microprograms
Speed ■ Slower — extra ROM access per cycle
Flexibility ✔ Easy to update — change ROM contents
Complexity Easier to design for complex ISA
Cost Cheaper for complex instruction sets
Used For CISC processors (x86, VAX)
Criterion Hardwired Microprogrammed
Speed Fastest Slower
Flexibility Low High
Design Effort High Lower
ISA Support Simple (RISC) Complex (CISC)
Error Correction Redesign needed Update ROM
6.4 RISC and CISC
RISC and CISC define two opposing philosophies in Instruction Set Architecture
(ISA) design — the set of instructions a CPU can execute. The debate is: Is it
better to have many simple instructions or fewer complex ones?
Figure 6.4 — RISC uniform pipeline vs CISC variable instruction cycles
6.4.1 RISC — Reduced Instruction Set
Computer
The RISC philosophy: do less with each instruction, but do it incredibly
fast. All instructions are the same size (32-bit typically) and execute in exactly 1
clock cycle. This regularity makes pipelining highly effective.
• Fixed instruction length (e.g., 32 bits always)
• Load/Store architecture — only LOAD and STORE touch memory; all other
operations work on registers
• Large register file — typically 32 general-purpose registers
• Hardwired control unit — no microcode
• Pipelining is very efficient — simple instructions = easy to overlap
• Compiler does more work — complex tasks need many simple instructions
Example RISC instruction (MIPS):
ADD R3, R1, R2 ; R3 = R1 + R2 (all in registers, 1 cycle)
• Real Examples: ARM (iPhone/Android), MIPS, RISC-V, SPARC, PowerPC
6.4.2 CISC — Complex Instruction Set
Computer
The CISC philosophy: one instruction does as much as possible. A single
instruction might fetch two operands from memory, multiply them, and store the
result — all in one go. This reduces the number of instructions in a program but
makes the hardware complex.
• Variable instruction length (1 to 15 bytes in x86)
• Instructions can access memory directly — no need to load into register
first
• Many specialized instructions — string operations, block moves, etc.
• Microprogrammed control unit — ROM stores complex instruction
implementations
• Hardware does more work — compiler is simpler
Example CISC instruction (x86):
IMUL EAX, [EBX+4], 10 ; EAX = memory[EBX+4] × 10 (3+ cycles)
• Real Examples: Intel x86/x64 (your laptop CPU), AMD64, VAX
Feature RISC CISC
Instruction Count More (simpler each) Fewer (complex each)
Instruction Size Fixed (32-bit) Variable (1–15 bytes)
Execution Time 1 cycle per instruction Multiple cycles
Pipelining Highly efficient Difficult
Memory Access Only via LOAD/STORE Direct in any instruction
Registers Many (32+) Fewer (8 in old x86)
Control Unit Hardwired Microprogrammed
Power Use Low (mobile-friendly) Higher
Examples ARM, MIPS, RISC-V x86, x64, VAX
Modern Reality: The Lines Have Blurred
Modern x86 processors (Intel/AMD) are internally RISC! They translate
complex x86 CISC instructions into simpler micro-operations (µops) internally
and execute them like RISC. So you get the code compatibility of CISC with the
speed of RISC.
6.5 Introduction to
Multiprocessing / Multitasking
As software grew more demanding, a single CPU running one task at a time
became a bottleneck. Two major solutions emerged: multiprocessing (add
more CPUs) and multitasking (split time on one CPU).
Figure 6.5 — Multiprocessing vs Multitasking
6.5.1 Multiprocessing
Multiprocessing means using two or more physical processors (CPUs)
working together. Tasks are truly running at the same time — in parallel. This is
real, genuine parallelism.
Types of Multiprocessing
Type Description Example
SMP
All CPUs share same memory; treated equally by OS
Dual-core, Quad-core PC
(Symmetric)
ASMP
One master CPU controls; others are slaves
Old mainframes, some embedded
(Asymmetric)
MPP
Thousands of processors, each with own memory Supercomputers
(Massively Parallel)
Cluster Multiple computers connected by network Google server farms
• Advantage: True parallelism, huge throughput, fault tolerance
• Challenge: Memory coherence — all CPUs must see consistent data
Figure 6.5b — Amdahl's Law: Adding more processors has diminishing returns
Amdahl's Law says the speedup from N processors is limited by the serial
part of the program. If 10% of code is serial, maximum speedup is 10× — no
matter how many CPUs you add.
6.5.2 Multitasking
Multitasking allows a single CPU to appear to run multiple programs
simultaneously. In reality, the CPU rapidly switches between tasks. Each task
gets a short time slice (typically 10–100 ms). The switching is so fast that it feels
simultaneous to the user.
Types of Multitasking
Type Who Controls Switching? Example
Preemptive OS forcibly switches at timer interrupts Windows, Linux, macOS
Cooperative Task voluntarily yields CPU Old Windows 3.x, classic Mac OS
Process vs Thread
Aspect Process Thread
Definition Running program with own memoryLightweight unit inside a process
Memory Separate address space Shared address space
Switching Slow (context switch overhead) Fast
Crash impact Isolated — won't kill others Can crash entire process
Example Chrome browser Each Chrome tab
Modern systems use BOTH: multiprocessing (multiple cores) combined with
multitasking (multiple threads per core). Your 8-core CPU with 16 threads can
run hundreds of tasks — some truly parallel, some time-shared.
6.6 Digital Signal Processor (DSP)
A Digital Signal Processor (DSP) is a specialized microprocessor optimized
for processing real-world signals — audio, video, radar, sonar, speech — in
real time. A general CPU can do this too, but a DSP does it much faster and
with much less power.
Figure 6.6 — DSP Internal Architecture with MAC Unit
6.6.1 Why DSPs Exist — The Core Problem
Signal processing involves computing sums of products (called convolution or
FIR filtering) billions of times per second. The key operation is:
y[n] = a[0]×x[0] + a[1]×x[1] + a[2]×x[2] + ... + a[N]×x[N]
On a general CPU, each multiply and add is a separate instruction. A DSP has
a dedicated Multiply-Accumulate (MAC) unit that performs one multiply-add in
a single clock cycle. This is the DSP's superpower.
6.6.2 Key Architectural Features of DSPs
MAC Unit Multiply and accumulate in 1 cycle — the core of DSP speed
Harvard Architecture Separate program and data memories — fetch instruction + data simulta
Circular Buffers Hardware support for ring buffers used in FIR filters
Zero-Overhead Loop Hardware loop counter — no time wasted on loop control instructions
Fixed/Floating Point Fixed-point DSPs: cheaper, lower power. Floating-point: more precise
DMA Controller Data moved between memory and peripherals without CPU involvement
Pipelining Deep pipeline optimized for repeated MAC operations
ADC/DAC Interface Direct connection to analog-to-digital and digital-to-analog converters
6.6.3 DSP Applications — Where DSPs Are
Used
Application Area Specific Uses
Audio MP3/AAC compression, noise cancellation, equalizers, echo removal
Telecommunications 4G/5G modems, echo cancellation, DTMF detection
Image & Video JPEG/H.264 encoding, video filters, real-time processing
Medical ECG/EEG analysis, MRI signal processing, hearing aids
Radar & Sonar Target detection, Doppler processing, beamforming
Speech Speech recognition, text-to-speech, voice codecs
Motor Control Precise motor speed/position control in robots
Consumer Smartphone audio chips, smart speakers (Amazon Echo), ANC headphones
6.6.4 DSP vs General CPU vs GPU
Criterion General CPU DSP GPU
Optimized For General tasks Signal math (MAC) Graphics / ML
MAC Performance Moderate Extremely high Very high
Power Use High Very low Very high
Programmability Very high Moderate High (CUDA)
Real-Time Guarantee No Yes No
Cost High Low High
Example Chips Intel i9 TI TMS320 Nvidia RTX
Popular DSP Chips
• Texas Instruments TMS320 Series — Industry standard, used in industrial
and audio
• Qualcomm Hexagon DSP — Inside Snapdragon chips (your Android phone)
• ADSP-21xx (Analog Devices) — Audio and communications
• ARM Cortex-M4/M7 with DSP extensions — Low-power IoT DSP
Quick Revision Summary
# Topic Core Idea Key Fact
6.1 Harvard ArchitectureSeparate memories & buses for instructions
Eliminates
and data
Von Neumann bottleneck; used in DSPs
6.2 Accumulator vs Register
Accumulator: one fixed result reg; Register:
Modern many
CPUs
GPRs
use register-based (32+ regs); ACC u
6.3 Control Unit Design Hardwired: logic gates; Microprogrammed:
Hardwired
ROM lookup
= fast (RISC); Microprogrammed = flexibl
6.4 RISC vs CISC RISC: simple, fixed instructions; CISC:Modern
complex,
x86
variable
converts CISC to RISC internally (micro
6.5 Multiprocessing / Multitasking
Multi: multiple CPUs in parallel; Multi-task:
Amdahl's
time-share
Law limits
one CPU
parallel speedup; preemptive O
6.6 DSP Specialized CPU with MAC unit for real-time
1-cyclesignal
multiply-accumulate;
processing Harvard arch; used in p
Key Formulas to Remember
Formula Name Expression Notes
Amdahl's Law (Speedup) P = parallel fraction, N = # processors
Speedup = 1 / [(1 - P) + P/N]
DSP MAC Operation y[n] = Σ a[k] · x[n-k] FIR filter convolution — 1 cycle per term o
Clock Cycles Per Instruction RISC aims
CPI = Total Cycles / Instruction for CPI ≈ 1; CISC CPI >> 1
Count
Throughput (Pipelining) Pipelining improves throughput, not latenc
Throughput = 1 / Clock Period