8086 MICROPROCESSOR

Architecture & Fundamentals

Study Guide • High Priority

CONTENTS KEY FACTS

1.1 Architecture of 8086 ▸ 16-bit microprocessor
1.2 Memory Segmentation ▸ 20-bit address bus (1 MB RAM)
1.3 Pin Description ▸ 16-bit data bus
1.4 Interrupts & Processing ▸ Introduced by Intel, 1978

1.1 Architecture of 8086

The 8086 is a 16-bit microprocessor that uses a pipelined architecture split into two independent
functional units: the Bus Interface Unit (BIU) and the Execution Unit (EU). These two units operate in
parallel, enabling instruction prefetching while the EU is executing the current instruction.

Bus Interface Unit (BIU)

The BIU is responsible for all external bus operations — it forms the interface between the CPU and the
outside world. Its key jobs are fetching instructions, reading operands, and writing results.

BIU Components
• Instruction Queue (6-byte FIFO): prefetches up to 6 bytes of instructions from memory ahead of
execution, enabling pipelining.
• Segment Registers (CS, DS, SS, ES): hold the base addresses of the four memory segments.
• Instruction Pointer (IP): holds the offset of the next instruction within the code segment.
• Address Generation Logic: computes the 20-bit physical address from segment + offset.
• Bus Control Logic: generates all bus control signals (RD, WR, ALE, DEN, DT/R, M/IO).

Execution Unit (EU)

The EU fetches instructions from the BIU's instruction queue and executes them. It never interacts with
the bus directly — all memory and I/O accesses are requested through the BIU.
 EU Components
• ALU (Arithmetic & Logic Unit): performs all arithmetic (+, −, ×, ÷) and logical (AND, OR, XOR,
NOT) operations.
• General-purpose Registers (AX, BX, CX, DX): 16-bit registers, each split into high (H) and low (L)
8-bit halves.
• Pointer Registers (SP, BP): Stack Pointer and Base Pointer.
• Index Registers (SI, DI): Source Index and Destination Index for string operations.
• Flag Register (PSW): 16-bit status register with Carry, Zero, Sign, Overflow, Parity, Auxiliary,
Direction, Interrupt, and Trap flags.
• Control Circuitry: decodes instructions and directs the ALU and registers.

Register Set

Register Name & Primary Use

AX Accumulator – default for arithmetic, I/O, and multiply/divide
BX Base Register – used as memory base address in data segment
CX Count Register – loop counter and shift/rotate count
DX Data Register – I/O port address; extends AX in 32-bit ops
SP Stack Pointer – always points to top of stack (SS:SP)
BP Base Pointer – accesses stack frame parameters
SI Source Index – source address for string operations
DI Destination Index – destination address for string operations
CS Code Segment – base of code (instructions)
DS Data Segment – base of default data area
SS Stack Segment – base of stack
ES Extra Segment – secondary data segment (string destination)
IP Instruction Pointer – offset of next instruction in CS
FLAGS Status/Control flags (Carry, Zero, Sign, Overflow, etc.)

1.2 Memory Segmentation

The 8086 has a 20-bit address bus, giving it access to 2²⁰ = 1,048,576 bytes = 1 MB of physical
memory. However, its registers are only 16-bit (max 64 KB). Memory segmentation solves this by
dividing the 1 MB address space into overlapping segments, each up to 64 KB.
The Four Memory Segments

Segment Register Pair Purpose

Code Segment (CS) CS : IP Holds the program instructions being
executed
Data Segment (DS) DS : BX/SI/DI Default segment for program data
(variables, arrays)
Stack Segment (SS) SS : SP / SS : BP Holds the runtime stack (return
addresses, local vars)
Extra Segment (ES) ES : DI Auxiliary data segment; destination in
string operations

Physical Address Calculation

The BIU calculates a 20-bit physical address from a 16-bit segment register and a 16-bit offset
(effective address). The segment register is shifted left by 4 bits (multiplied by 16) and then added to
the offset:

Physical Address = (Segment Register × 16) + Offset

Equivalently: shift segment left by 4 bits, then add the 16-bit offset

Worked Example
• CS = 2000h, IP = 0300h
• Physical Address = (2000h × 10h) + 0300h
• = 20000h + 0300h = 20300h
• The instruction is fetched from memory location 0x20300.

Key Points on Segmentation

• Segments start at paragraph boundaries (every 16 bytes — any address divisible by 16).
• Segments can overlap: multiple logical segments can map to the same physical memory.
• Each segment can be up to 64 KB (65,536 bytes).
• The effective address (offset) is computed by the EU; the BIU then appends the segment base.
• Overlapping segments are used to save memory when code and data are small.
 1.3 8086 Pin Description

The 8086 comes in a 40-pin DIP (Dual In-line Package). It operates in two modes selectable via pin 33
(MN/MX̄ ). Minimum mode is for simple, single-processor systems; maximum mode supports
multiprocessor systems with a bus controller (8288).

Minimum Mode vs Maximum Mode

Feature Minimum Mode (MN/MX̄ = HIGH) Maximum Mode (MN/MX̄ = LOW)

Bus Control 8086 directly drives all bus control 8288 Bus Controller generates bus
signals signals
System Size Simple, single-processor systems Multiprocessor / coprocessor
systems
Pins 24–31 Dedicated control signals (RD, WR, Status signals (S0, S1, S2) sent to
M/IO, etc.) 8288
Cost Lower (fewer chips) Higher (requires 8288 IC)

Key Control Signals

Signal Direction Description

ALE Output Address Latch Enable — high pulse indicates valid address on bus;
used to latch address in 8212/74LS373
RD̄ Output Read — active LOW; signals memory or I/O to put data on bus
WR̄ Output Write — active LOW; signals memory or I/O to accept data
M/IŌ Output Memory/IO Select — HIGH = memory access; LOW = I/O access
DEN̄ Output Data Enable — enables data bus transceivers (active LOW during data
transfer)
DT/R̄ Output Data Transmit/Receive — HIGH = transmit (CPU writing); LOW =
receive (CPU reading)
READY Input Used by slow memory/IO to insert wait states; LOW = insert wait
RESET Input Resets the CPU; CS=FFFFh, IP=0000h after reset (jumps to FFFF0h)
HOLD / HLDA In/Out Bus request/grant for DMA: HOLD input requests bus; HLDA output
grants it
BHĒ Output Bus High Enable — enables upper byte (D8–D15) of data bus
Interrupt Pins

NMI — Non-Maskable Interrupt

• Rising-edge triggered (positive edge sensitive).
• Cannot be disabled by software (cannot be masked by CLI instruction).
• Always calls interrupt type 2 (fixed vector).
• Used for critical hardware faults: memory parity errors, power failure, etc.
• Priority: NMI has higher priority than INTR.

INTR — Maskable Interrupt

• Level-triggered (active HIGH).
• Can be enabled/disabled by software: STI (Set Interrupt Flag) / CLI (Clear Interrupt Flag).
• When accepted, the CPU performs two INTĀ (interrupt acknowledge) bus cycles to read the
interrupt type number from the interrupting device.
• Supports up to 256 different interrupt vectors (types 0–255).

1.4 Interrupts & Interrupt Processing

An interrupt is a signal that causes the CPU to suspend its current task, save its state, and execute a
special routine called an Interrupt Service Routine (ISR). After the ISR completes, the CPU resumes
the interrupted program.

Types of Interrupts

Hardware Interrupts (External)

• NMI (Type 2): Non-maskable; triggered by external hardware on NMI pin; cannot be disabled.
• INTR: Maskable; triggered by peripherals via 8259A PIC; disabled by CLI, enabled by STI.
• INTĀ: CPU's response — two acknowledgment pulses are sent back to the interrupting device to
receive the interrupt vector number.

Software Interrupts (Internal)

• INT n: Software interrupt instruction; directly specifies the vector type number n (0–255). Example:
INT 21h (DOS services), INT 10h (BIOS video).
• INTO: Interrupt on Overflow — type 4; triggers only if the Overflow flag (OF) is set.
• INT 3: Breakpoint interrupt (1-byte opcode 0xCC); used by debuggers to set breakpoints.
• Single-Step (Type 1): When Trap Flag (TF) is set, an interrupt occurs after every instruction.
 • Divide Error (Type 0): Triggered automatically on division by zero or quotient overflow.

Interrupt Vector Table (IVT)

The IVT occupies the first 1 KB of memory (addresses 00000h to 003FFh). It holds 256 entries, one for
each interrupt type (0–255). Each entry is 4 bytes: 2 bytes for the IP (offset) and 2 bytes for the CS
(segment) of the corresponding ISR.

IVT Entry Address = Interrupt Type × 4

4 bytes per entry × 256 entries = 1024 bytes (00000h – 003FFh)

Type # Interrupt Name Trigger Condition

0 Divide Error Division by zero or quotient too large
1 Single Step Trap Flag (TF) = 1; after every instruction
2 NMI Rising edge on NMI pin
3 Breakpoint INT 3 instruction (0xCC); debugger breakpoints
4 Overflow INTO instruction when Overflow Flag (OF) = 1
5–31 Reserved Reserved by Intel for future use
32–255 User-Defined Available for hardware (IRQ0–IRQ15 via 8259A) and
software INT n

Interrupt Processing Sequence

When the CPU accepts an interrupt, it follows this sequence:

1 Complete current instruction execution (if in progress).

2 Push FLAGS register onto the stack (saves CPU status).

3 Clear Interrupt Flag (IF) and Trap Flag (TF) to disable further maskable interrupts.

4 Push CS (Code Segment) register onto the stack.

5 Push IP (Instruction Pointer) register onto the stack.

6 Load new CS and IP from the Interrupt Vector Table (IVT entry = type × 4).

7 Execute the Interrupt Service Routine (ISR).

8 Execute IRET — pops IP, CS, and FLAGS to restore original program state.
Interrupt Priority Order
When multiple interrupts occur simultaneously, the 8086 services them in the following priority order
(highest to lowest):

Priority Interrupt Notes

1 (Highest) Divide Error / INTO / Internal software interrupts (fixed, immediate)
INT n / INT 3
2 NMI Non-maskable; cannot be disabled
3 INTR Maskable; enabled when IF = 1
4 (Lowest) Single-Step (TF) Debug mode; after each instruction

8086 Microprocessor Study Guide — Architecture & Basics