DEBRE TABOR UNIVERSITY

FACULTY OF ELECTRICAL AND COMPUTER ENGINEERING

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

(COMMUNICATION STREAM)
TITLE: DESIGN AND ANALYSIS OF A T-S-T CIRCUIT SWITCH

COURSE TITLE: SWITCHING AND INTELLIGENT NETWORK

Prepared by: Student ID:

[Link] Misgenu Benti DTU13R0551

[Link] Tesfaye Daba DTU13R0509

[Link] Kindalem Erkie DTU13R0236

[Link] Shibabaw Mekonnen DTU13R3156

[Link] Eshetu Rega DTU13R0531

Advisor:

1. Mr. Joseph B. (MSc)

Thursday, December 25, 2025 G.C

DEBRE TABOR, ETHIOPIA

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 Abstract
This project presents the design and analysis of a Time–Space–Time (TST) circuit switching
architecture for a modern digital local exchange capable of supporting 2048 simultaneous voice
channels. The design task is motivated by the need for efficient, scalable, and non-blocking
switching systems in contemporary telecommunication networks. The study begins with an
examination of the fundamental principles of Time Division Switching (TDS) and Space
Division Switching (SDS), followed by an exploration of how these techniques are integrated into
the three-stage TST architecture to minimize blocking while optimizing switching speed and
hardware complexity. The system design considers E1 carrier structure, assuming 32 time slots
per frame with 30 time slots dedicated to voice channels, to determine the required number of
incoming and outgoing links. A detailed architecture is developed, including the sizing and
performance requirements of the Time Slot Interchangers (TSIs) and the dimensional analysis
of the central Space Switch. The design is evaluated against Clos’s non-blocking criteria, and
all switching stages are optimized to ensure full connectivity without call blockage. A
comprehensive analysis compares switching performance, complexity, and scalability with
traditional single-stage Time (T) or Space (S) switches. The results demonstrate that the TST
architecture offers superior efficiency, reduced hardware cost, and improved throughput for large-
capacity digital exchanges. The project concludes that a correctly dimensioned TST switch
provides an effective and future-ready solution for modern circuit-switched networks, particularly
where high channel capacity and guaranteed non-blocking performance are critical.

Keywords

Time Space Time (TST) Switching, Time Slot Interchanger (TSI), Space Switch, E1 Carrier, PCM
Voice Channels, Digital Switching, Circuit Switching, Clos Network, Non-Blocking Architecture,
Telecommunication Exchange.

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 Acknowledgment
We would like to express our sincere gratitude to our instructor, Mr. Joseph B. (MSc), for his
valuable guidance, insightful lectures, and continuous academic support throughout the course.
His expertise in telecommunication switching systems greatly enhanced our understanding of the
subject and played a significant role in the successful completion of this work.

We also extend our appreciation to the Department of Electrical and Computer Engineering for
providing the necessary academic resources and a conducive learning environment. Finally, we
acknowledge our classmates for their collaboration, discussions, and constructive feedback during
the project writing process.

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Table of Contents
Abstract ........................................................................................................................ I
Acknowledgment .......................................................................................................... II
1 CHAPTER 1: INTRODUCTION ............................................................................ 1
1.1 Background of the Study ................................................................................. 1
1.2 Problem Statement .......................................................................................... 1
1.3 Objectives of the Project .................................................................................. 1
1.4 Scope of the Project ......................................................................................... 2
1.5 Significance of the Project................................................................................ 2
1.6 Organization of the Report .............................................................................. 2
CHAPTER 2: LITERATURE REVIEW ......................................................................... 4
CHAPTER 3: SYSTEM DESIGN AND METHODOLOGY............................................. 7
CHAPTER 4: ANALYSIS AND RESULTS ................................................................... 14
CHAPTER 5: CONCLUSION AND RECOMMENDATIONS ....................................... 18
Conclusion ................................................................................................................. 18
Recommendations ....................................................................................................... 18
Future Work............................................................................................................... 20
References .................................................................................................................. 21

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1 CHAPTER 1: INTRODUCTION
1.1 Background of the Study
Telecommunication networks rely on switching systems to establish, maintain, and release
communication paths between users. With the rapid demand for voice services and real-time
communication, digital circuit switching has become a foundational technology in public switched
telephone networks (PSTNs). Among various switching architectures, the Time–Space–Time
(TST) switch has emerged as an optimal structure for achieving high-capacity, non-blocking, and
efficient channel switching.

Traditional switching systems used either Space Division Switching (SDS) or Time Division
Switching (TDS) independently. However, as networks expanded and the need for handling
thousands of simultaneous voice calls increased, it became necessary to combine both techniques
to achieve higher scalability and cost efficiency. The TST architecture, first introduced in advanced
digital exchanges, integrates the benefits of both SDS and TDS by using Time Slot Interchangers
(TSIs) at the input and output stages and a centralized space switch in between. This architecture
significantly reduces hardware complexity while ensuring non-blocking performance as guided by
Clos’s switching theory.

1.2 Problem Statement

Modern telecommunications require switching systems that can support large numbers of users
with minimal delay, high reliability, and guaranteed connection availability. A pure Time or pure
Space switch is insufficient for systems with thousands of channels due to limitations in
scalability, blocking probability, and hardware complexity.
Therefore, the challenge addressed in this project is:
How can a non-blocking digital switching system be designed to efficiently handle 2048 voice
channels using a combination of time and space switching techniques?

1.3 Objectives of the Project

General Objective

To design and analyze a non-blocking Time–Space–Time (TST) circuit switch capable of

supporting 2048 simultaneous voice channels in a digital local exchange.

Specific Objectives

• To explain the principles of Time Division Switching and Space Division Switching.

• To determine the required number of E1 links for handling 2048 voice channels.
• To design the architecture of the TST switch, including TSIs and the central space switch.

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 • To apply Clos’s criteria to ensure non-blocking conditions.

• To develop a clear block diagram of the proposed TST switching system.

• To analyze the efficiency, scalability, and performance of the TST architecture compared
to pure T or S switches.

1.4 Scope of the Project

This project focuses on the theoretical and architectural design of a TST digital switch for circuit-
switched voice communication. The scope includes:

• Analysis of switching principles (TDS, SDS, TST)

• Determination of system capacity and link requirements

• Structural design of TSIs and space switch matrix
• Verification of non-blocking criteria

• Performance comparison with alternative switch architectures

The project does not include hardware implementation or real-time simulation; however, design
parameters and analyses follow standard telecommunication engineering practices.

1.5 Significance of the Project

The TST switch is widely used in digital switching centers due to its optimal balance between
switching speed, non-blocking behavior, and hardware efficiency. Understanding its design is
essential for engineers working in telecommunication switching networks, PSTNs, and exchange
design.
This project provides:

• Practical insight into digital switching architecture

• Application of theoretical switching concepts in a real design scenario

• Foundational knowledge relevant for advanced network engineering, NGN systems, and
digital exchange configuration

1.6 Organization of the Report

This report is organized into five chapters:

• Chapter 1 introduces the background, problem statement, objectives, scope, significance,

and structure of the project.
• Chapter 2 presents a detailed literature review on switching systems, including time,
space, and hybrid switching techniques, as well as non-blocking conditions.

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• Chapter 3 explains the methodology and develops the TST switch design, including TSIs,
the space switch, and dimensioning.

• Chapter 4 provides analysis and discussion of results, covering blocking, efficiency,

complexity, and performance evaluation.

• Chapter 5 summarizes the findings, draws conclusions, and presents recommendations

and future research directions.

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 CHAPTER 2: LITERATURE REVIEW
2.1 Overview of Circuit Switching

Circuit switching is a communication technique in which a dedicated path is established between

two end-users for the entire duration of the call. It guarantees constant bandwidth, fixed delay, and
predictable performance making it ideal for voice services. Modern circuit-switched networks
employ digital switching systems that utilize pulse code modulation (PCM) with a sampling rate
of 8 kHz and 8-bit quantization, resulting in a 64-kbps channel per voice user [1]. The fundamental
goal of a switching system is to interconnect multiple users efficiently while minimizing blocking
probability and maximizing throughput.

2.2 Space Division Switching (SDS)

Space Division Switching uses physical crosspoints (switching elements) arranged in matrices to
create spatial connections between input and output lines. Traditional electromechanical systems
such as crossbar switches used metallic contacts to form a circuit path. In a digital environment,
crosspoint matrices are implemented electronically. SDS offers fast switching and straightforward
connection mapping; however, its major drawback is hardware complexity. A large crosspoint
matrix requires N × N switching elements for N inputs and N outputs, making it impractical for
systems supporting thousands of channels [2].

2.3 Time Division Switching (TDS)

Time Division Switching operates by rearranging PCM time slots within frames. Instead of
establishing a physical path, the switch changes the order of time slots, effectively connecting users
through Time Slot Interchangers (TSIs). A TSI stores incoming time slots in a buffer and
retransmits them in a different order based on a control map [3].
TDS drastically reduces hardware requirements because it reuses the same physical medium for
multiple connections at different time intervals. However, switching large numbers of time slots
requires high memory speed and imposes timing constraints on the system.

2.4 Hybrid Switching: Time–Space–Time Architecture

To overcome the limitations of pure SDS and TDS, hybrid switching techniques such as Space–
Time–Space (STS) or Time–Space–Time (TST) were introduced. Among these, TST is the most
widely used in digital exchanges due to its optimal balance between complexity and performance.

A TST switch consists of:

• Time Slot Interchangers (TSI) at the input stage

• A Space Switch Matrix at the central stage

• TSIs at the output stage

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This structure reduces the size of the space switch and distributes switching tasks across multiple
stages, resulting in a non-blocking and highly scalable system [4].

2.5 Time Slot Interchanger (TSI) Principles

The TSI performs two key operations:

1. Write Operation: Incoming time slots are stored sequentially in memory.

2. Read Operation: Stored slots are read out in a rearranged order based on a control map.

The memory access rate must be at least 2 × (number of time slots per frame) to allow both read
and write operations within the same frame. This makes TSIs highly dependent on memory speed
and clock frequency [5].

2.6 Space Switch Fundamentals

A digital space switch typically uses electronic crosspoints arranged in a multistage topology. For
large systems, a single-stage N × N matrix is inefficient because it demands N² switching elements.
Multi-stage structures such as Clos networks drastically reduce the number of crosspoints needed
while supporting non-blocking connectivity [6].

The central space stage in a TST switch facilitates interconnection between TSIs and ensures that
time-slotted data is routed to the correct output module.

2.7 Clos Network and Non-Blocking Condition

Charles Clos introduced a three-stage network to minimize blocking while reducing hardware
complexity. The Clos non-blocking condition is expressed as:

𝑚 ≥ 2𝑛 − 1

Where:
• n = number of inputs/outputs per inlet or outlet module

• m = number of central switching modules

This condition ensures that a path can always be established between any input and output without
rearranging existing connections [7]. TST architecture is typically designed according to Clos
criteria to guarantee non-blocking performance.
2.8 Digital Switching in Modern Telecommunication Networks

Digital switching systems such as the Alcatel E10, Ericsson AXE, and Nortel DMS series widely
adopt hybrid switching architectures (including TST) to support large-capacity voice networks [8].
These systems demonstrate that combining time and space switching stages minimizes hardware
cost, supports modular expansion, and ensures reliable real-time communication.

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2.9 Existing Research on TST Switching Efficiency

Recent studies highlight the efficiency of TST architectures in reducing crosspoint count,
optimizing switching delay, and supporting high channel density. Researchers have shown that
distributing switching operations across time and space stages minimizes blocking, improves
throughput, and enhances fault tolerance compared to single-stage switches [9], [10].

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 CHAPTER 3: SYSTEM DESIGN AND
METHODOLOGY
3.1 System Requirements

The design objective is to develop a non-blocking T-S-T (Time–Space–Time) digital switch

capable of handling 2048 simultaneous voice channels. The system must meet the following
requirements:
• Support 64 kbps PCM digital voice channels (ITU-T G.711 standard).

• Utilize E1 carrier links, each consisting of 32 time slots (TS0 used for framing; 30 used
for voice).
• Achieve non-blocking operation according to Clos’s criteria.

• Optimize switching hardware by combining Time and Space switching stages.

• Maintain compatibility with digital switching standards used in local exchanges.

The TST configuration must include:

1. Input TSIs for time slot rearrangement

2. Central Space Switch Matrix for interconnection

3. Output TSIs for final time slot alignment

3.2 Determination of Number of E1 Links

Each E1 link provides:

32 time slots/frame (30 voice channels)

To determine the number of E1 links required for 2048 voice channels:

2048
Number of E1s = = 68.266
30
Since the number of E1 links must be an integer:

69 E1 links (minimum)

Thus:

• 69 incoming E1 links
• 69 outgoing E1 links

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Each E1 carries:

2.048 Mbps

Therefore, the total system throughput:

69×2.048=141.31 Mbps (each direction)

3.3 Time Slot Interchanger (TSI) Design

Each TSI receives 30 time slots per frame and must be capable of:

• Storing incoming time slots sequentially

• Reading them out in any order based on connection requests

3.3.1 Memory Requirement

For 30 time slots per frame, 8 bits per time slot:

Memory size=30×8=240 bits≈30 bytes

3.3.2 Memory Access Speed

A TSI must perform two memory accesses per time slot:

• 1 write

• 1 read

If the frame rate is 8 kHz:

Memory access per second=30×2×8000=480,000 accesses/s

This is easily achievable with standard digital memory.

3.3.3 Number of TSIs

There are 69 incoming and 69 outgoing E1 links:

69 Input TSIs+69 Output TSIs

3.4 Space Switch Design

The central space switch interconnects all input TSIs to all output TSIs.

3.4.1 Space Switch Size

The simplest approach is a single-stage crosspoint matrix:

8
69×69=4761 crosspoints69

However, to reduce hardware complexity, a Clos 3-stage design is preferred.

3.4.2 Clos Architecture Specification

Let:
• n = number of inlets per input stage switch

• r = number of input stage switches

• m = number of central switches

For 69 inputs:

n=8 (choose a practical value)

r=698=8.625→9 switches

According to Clos non-blocking condition:

𝑚 ≥ 2𝑛 − 1

𝑚 ≥ 2(8) − 1 = 15

Thus:

• 9 input stage switches (each 8×m)

• 15 middle stage switches

• 9 output stage switches

This configuration guarantees strictly non-blocking operation.

3.4.3 Actual Space Switch Dimensions

• Input stage: 9× (8×15)

• Middle stage: 15× (9×9)

• Output stage: 9× (15×8)

• This reduces the number of crosspoints significantly compared to a single-stage matrix.

3.5 T-S-T Architecture Design

A T-S-T design uses:

𝑇𝑆𝐼input → 𝑆𝑝𝑎𝑐𝑒 𝑤𝑖𝑡𝑐ℎ → 𝑇𝑆𝐼output

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3.5.1 Call Routing Process

1. Input TSI arranges incoming time slots.

2. Space switch connects time slot paths across E1 links.

3. Output TSI forwards the call in the desired time slot.

3.5.2 Advantages of T-S-T Configuration

• Reduces space switch complexity

• Achieves non-blocking switching

• Distributes delay across TSIs

• Enables modular expansion

3.6 Non-Blocking Criteria Verification (Clos Criterion)

The Clos non-blocking rule is:

𝑚 ≥ 2𝑛 − 1𝑚

With chosen parameters:

• n=8

• m=15
Verification:

15 ≥ 2(8) − 1 = 15

Thus, the switch meets the non-blocking condition.

All connections can be set up without rearranging existing connections (strict-sense non-blocking).

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3.7 Block Diagram of Proposed TST Switch Architecture

Figure A: General Architecture of a Time–Space–Time (TST) Digital Switch

Figure B: Block Diagram of Proposed TST Switch Configuration for 69 Input and 69 Output E1
Links

The diagram illustrates the complete structure of a Time–Space–Time (TST) switching system,
which is one of the most widely implemented architectures in digital telecommunication
exchanges. The TST switch is composed of three sequential switching stages: a Time-switch
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(Input TSI) stage, a Space-switch (Central Matrix) stage, and finally another Time-switch
(Output TSI) stage. This structure corresponds directly to the classical model of TST switching
found in standard telecommunication engineering texts and digital switching literature.

1. Input Time-Switch (Input TSI Bank)

Incoming signals arrive at the switch in the form of Time-Division Multiplexed (TDM) links,
typically structured as PCM frames (e.g., E1, 32 time slots per frame). These TDM links first enter
the Input Time Slot Interchanger (TSI) Bank, where the initial stage of switching occurs.
Function of the Input TSI

• Stores each incoming PCM time slot in a memory buffer.

• Rearranges or “interchanges” the order of stored time slots based on connection

requirements.

• Allows any incoming time slot to be mapped to any intermediate time slot before entering
the next stage.

This operation is crucial because it reduces the burden on the central space switch and enables
flexible connection setup.

2. Central Space-Switch (Clos-Based Switching Matrix)

After the time slot rearrangement at the input stage, the data is forwarded into the Central Space
Switch, which performs switching in the spatial domain. This stage is often implemented as a
multistage Clos switching network, which significantly reduces the number of required
crosspoints while still maintaining strict-sense non-blocking performance.

Function of the Space Switch

• Provides the physical path or “cross-connect” between an input module and an output
module.
• Ensures that any input time slot can reach any output TSI through an available space switch
module.

• Uses an optimized number of crosspoints to reduce hardware cost and complexity.

This architectural model is widely documented in academic sources, including UTS Surabaya’s
OPAC digital switching references and university switching system lecture notes.

3. Output Time-Switch (Output TSI Bank)

Once the signal passes through the space switch, it enters the Output TSI Bank, which performs
the final stage of time slot manipulation.
Function of the Output TSI
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• Reassigns the received time slots into the correct time positions required by the outgoing
TDM link.

• Ensures alignment so that the channel appears in the proper time slot for the receiving
subscriber or exchange.

• Completes the connection by outputting a properly framed PCM stream onto the outgoing
E1/TDM link.

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 CHAPTER 4: ANALYSIS AND RESULTS
4.1 Switching Speed Analysis

4.1.1 Time Slot Duration

In a PCM system operating at 8 kHz:

1
𝑇frame = = 125 𝜇𝑠
8000
Each frame has 32 time slots, so the time per slot is:
125 𝜇𝑠
𝑇slot = ≈ 3.906
32
4.1.2 TSI Switching Requirement
A Time Slot Interchanger must perform:

• 1 write + 1 read operation per time slot

Total memory accesses per second:

30 × 2 × 8000 = 480,000 accesses/s

This requirement is well within the performance of modern digital memory devices, confirming
the feasibility of the TSI design.

4.2 Blocking Probability Analysis

4.2.1 Single-Stage Switch Blocking Characteristics

A single-stage 69 × 69 space switch is theoretically blocking, because simultaneous connection
requests may attempt to use the same output line.

Thus, such a design is not acceptable for PSTN-grade switching.

4.2.2 Applying Clos’s Non-Blocking Criterion

The chosen Clos parameters:

• n=8n = 8n=8 ports per input switch

• m=15m = 15m=15 middle-stage switches

• r=9r = 9r=9 input-stage switches

Clos criterion:

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 𝑚 ≥ 2𝑛 − 1

15 ≥ 15

This configuration is strict-sense non-blocking.

Conclusion:
The designed T-S-T switch guarantees zero blocking probability, ensuring that any of the 2048
channels can establish a connection at any time.

4.3 Hardware Complexity Analysis

4.3.1 Single-Stage Space Matrix Complexity

A direct crosspoint matrix:

69 × 69 = 4761 crosspoints

4.3.2 Clos-Based Multi-Stage Complexity

a) Input stage:

9 × (8 × 15) = 1080 crosspoints

b) Middle stage:

15 × (9 × 9) = 1215 crosspoints

c) Output stage:

9 × (15 × 8) = 1080 crosspoints

Total crosspoints in 3-stage system:

1080 + 1215 + 1080 = 3375 crosspoints

Hardware Savings:
4761 − 3375
Savings = × 100 ≈ 29.1%
4761
→ The T-S-T architecture reduces hardware by approximately 30%, increasing efficiency and
lowering costs.

4.4 Delay and Latency Analysis

4.4.1 TSI Delay

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TSI introduces a frame-based delay, typically:

0.125 ms ≤ 𝑇TSI ≤ 0.25 ms

4.4.2 Space Switch Delay

Electronic crosspoints operate at nanosecond speeds:

𝑇space ≈ 10−9 s

Thus, the dominant delay arises from TSI, not the space switch.
4.4.3 Total Switching Delay

𝑇total ≈ 𝑇TSI-input + 𝑇space + 𝑇TSI-output

𝑇total ≈ 0.125 + 0.000001 + 0.125 = 0.25 ms

This delay is within acceptable limits for real-time voice communication (<150 ms one-way delay
recommended by ITU-T G.114).

4.5 Scalability Evaluation

The designed architecture is scalable because:

• Additional TSIs can be added as more E1 links are introduced.

• The space switch matrix can be expanded by increasing the number of input switches (r)
or central switches (m).

• The Clos architecture inherently supports incremental expansion.

Practical Scalability Example

To support 4096 channels, E1 links become:

4096
≈ 137 E1s
30
Doubling r from 9 to ~18 input switches would support the increase without redesigning the entire
structure.

4.6 Efficiency Comparison: T-S-T vs. Pure T and Pure S Switches

4.6.1 Pure Time Switch

• Requires extremely large and fast memory

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 • Becomes impractical for >2000 channels

• High delay accumulation

4.6.2 Pure Space Switch

• Requires N² crosspoints
• Hardware cost increases exponentially

• Poor scalability

4.6.3 T-S-T Switch Advantages

Feature Pure T Pure S T-S-T (Proposed)

Hardware Complexity High Very High Medium

Blocking Probability Medium High Zero (non-blocking)

Delay Moderate Low Low

Scalability Low Medium High

Cost Effectiveness Low Medium High

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 CHAPTER 5: CONCLUSION AND
RECOMMENDATIONS

Conclusion
This project has presented the design and analysis of a non-blocking Time–Space–Time (TST)
digital circuit switch tailored to support 2048 simultaneous voice channels using E1 carrier
systems. The study successfully integrated the theoretical concepts of Time Division Switching
(TDS), Space Division Switching (SDS), and Clos’s non-blocking network principles to
engineer an efficient and scalable switching architecture suitable for modern digital exchanges.

The system analysis showed that:

• A minimum of 69 E1 links is required to support the intended 2048 PCM voice channels.

• A TST architecture comprising 69 input TSIs, a Clos-based multi-stage space switch,

and 69 output TSIs effectively supports the required switching operations.

• The chosen Clos configuration—using n=8n = 8n=8, r=9r = 9r=9, and m=15m = 15m=15
meets the strict-sense non-blocking criterion, ensuring that no connection request is
blocked under any traffic condition.

• The TST design reduced hardware complexity by approximately 30% compared to a

single-stage 69×69 space switch, proving its cost-effectiveness.

• The total switching delay (~0.25 ms) is well within ITU-T limits for voice services,
confirming suitability for real-time communications.

• Comparative evaluation demonstrated that the TST architecture outperforms pure Time and
pure Space switching systems in terms of scalability, efficiency, delay, and blocking
performance.

Therefore, the proposed TST switch architecture is both technically feasible and operationally
efficient for implementation in medium- to large-scale telecommunication exchanges. It maintains
the balance between performance and complexity, making it a long-standing solution in circuit-
switched networks.

Recommendations
Based on the findings of this project, the following recommendations are made for optimizing and
enhancing TST switching systems:
5.2.1 Adopt TST for Medium and High-Capacity Networks

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Telecommunication operators should utilize TST architecture where channel capacity exceeds
1000 users, as pure T or S switches become inefficient at these scales.

5.2.2 Implement Clos-Based Multi-Stage Space Switching

To achieve strict non-blocking capability with reduced hardware complexity, multi-stage Clos
architectures should be preferred over single-stage crosspoint matrices.

5.2.3 Employ High-Speed Memory for TSI Implementation

Because TSI performance directly affects total switching delay, high-speed RAM or FIFO memory
should be used to ensure reliable read/write operations at 8 kHz frame rates.

5.2.4 Use Modular and Expandable Switch Design

Scalability should be emphasized. The TST switch should be designed so that:

• Additional TSIs can be added when new E1 links are introduced

• More central switches can be added to upgrade capacity

• The control system can dynamically adjust to new routing demands

5.2.5 Integrate Intelligent Control Functions

Future switching systems may integrate:

• Automatic load balancing across space switch modules

• Fault-tolerant path selection algorithms

• Dynamic time-slot allocation strategies

These improvements will contribute to higher reliability and adaptive performance in

contemporary networks.

5.2.6 Consider Future Evolution to Packet-Switched Architectures

Although TST switches remain foundational to PSTNs, operators should plan for gradual
migration toward:

• Softswitch architectures
• VoIP-based NGN systems

• IMS-enabled networks

These systems will eventually supersede legacy circuit switches.

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 Future Work
Further improvements may include:

• Real-time simulation of the proposed TST switch using MATLAB, Python, or NS-3

• Hardware-based implementation using FPGA or DSP boards

• Evaluation of hybrid switching combining TST with packet-switching fabrics

• Power consumption and reliability analysis

• Integration with signaling protocols such as SS7 or SIP

Such enhancements would extend the practical relevance of this design and support more advanced
telecommunication services.

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References
[1] R. L. Freeman, Telecommunication System Engineering, 4th ed. New York, NY, USA:
Wiley-Interscience, 2004.
[2] J. E. Flood, Telecommunication Switching, Traffic and Networks. London, U.K.: Pearson
Education, 1995.
[3] A. Mukherjee, Introduction to Digital Switching. New York, NY, USA: McGraw-Hill,
1989.
[4] T. H. Chen and S. S. Rappaport, “Digital time-division switching systems,” IEEE
Communications Magazine, vol. 16, no. 6, pp. 20–32, 1978.
[5] A. J. Viterbi and J. K. Omura, Principles of Digital Communication and Coding. New York,
NY, USA: McGraw-Hill, 1979.
[6] C. Clos, “A study of non-blocking switching networks,” Bell System Technical Journal,
vol. 32, no. 2, pp. 406–424, Mar. 1953.
[7] B. S. Manoj and G. R. Gupta, Digital Switching Systems: System Reliability and Analysis.
New Delhi, India: Prentice-Hall of India, 2010.
[8] T. H. Lee, Electronic Switching in the Telephone Network. Dordrecht, Netherlands:
Springer-Science+Business Media, 2013.
[9] R. Black, “Time-slot interchange and TST switch design in digital telephony,” IEEE
Transactions on Communications, vol. 30, no. 12, pp. 2533–2543, Dec. 1982.
[10] ITU-T Recommendation G.711, “Pulse Code Modulation (PCM) of Voice Frequencies,”
International Telecommunication Union, Geneva, Switzerland, 1988.

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