End Semester Examination, April – May, 2025
Degree: [Link] , Semester : Fourth
Stream: CSE/CSE(AI)/CSE(AI & ML)/CSE(AIML)/CSE(IOT) /CSE(IOT,
CS,BT)/ CSE(IOTCSBT)/CSIT/CST/IT/CSBS
Paper Code: PCCCS402
Paper Name: - Computer Organization & Architecture
Full Marks: 100 Duration: 3 Hours
Part - A
Attempt any 10 questions out of 15 questions
Each question carries 2 Marks (2 × 10)
1. What do you mean by MIPS and CPI? How do they relate with each other? 2
2. What is the Von Neumann model of computation? 2
3. Represent -43.625 in binary representation using the given manner. Assume the 2
number is using 32-bit format which reserves 1 bit for the sign, 15 bits for the
integer part and 16 bits for the fractional part.
4. What is the length of the product register for unsigned multiplication if the 2
length of the multiplicand is m-bit and the length of the multiplier is q-bit?
5. A two-word relative mode brunch instruction is stored in memory location 2
1000. The branch is made to the location 87. What is the effective address?
6. Explain indirect addressing mode using an example. 2
7. Explain micro instruction format using example. 2
8. Explain the process of mapping from instruction code to microinstruction 2
address.
9. How many total bits are required for a direct-mapped cache with 16 KiB of data 2
and 4-word blocks, assuming a 32-bit address?
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10. Find the Average Memory Access Time (AMAT) for a processor with a 1 ns 2
clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses
per instruction, and a cache access time (including hit detection) of 1 clock
cycle. Assume that the read and write miss penalties are the same and ignore
other write stalls.
11. If given a choice between increasing the number of memory banks or 2
implementing memory interleaving, which approach would be more effective
in improving memory access speed?
12. Is there any drawback of strobe method in data transfer? If yes, what is the 2
method of solving this problem?
13. Find the difference between polling and daisy chaining. 2
14. How many Data Hazards are possible? Name them. Which Data Hazard is not 2
possible?
15. Explain Speedup ration and efficiency in instruction pipeline. 2
Part - B
Attempt any 6 questions out of 9 questions
Each question carries 5 Marks (5 × 6)
16. Do the following changes to a computer system increase throughput, decrease 5
response time, or both?
a) Replacing the processor in a computer with a faster version.
b) Adding additional processors to a system that uses multiple processors for
separate tasks – for example, searching the web.
17. Show the step-by-step multiplication process using Booth algorithm when the 5
following binary numbers are multiplied. Assume 5-bit registers that hold
signed numbers. The multiplicand in both cases is +15.
a) (+15) x (+13)
b) (+15) x (-13)
18. Prove that the multiplication of two n-digit numbers in base r gives a product 5
no more than 2n digits in length. Show that this statement implies that no
overflow can occur in the multiplication operation.
19. An instruction is stored at location 30 with its address field at location 301. The 5
address field has the value 400. A processor register 𝑅𝑅 1 contains the Number
200. Evaluate the effective address if the addressing mode of the instruction is
(a) direct, (b) immediate, (c) relative, (d) register indirect and (e) index with 𝑅𝑅 1
as the index register.
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20. Write down a program in Stack-based architecture (zero-address instruction) 5
that performs the following operation.
Z=A/B+(C-A*B); here, Z, A, B and C are the memory locations.
For each step of the above-mentioned operation using zero-address instruction,
give proper explanation and draw the positions of TOS (top of the stack) with
diagrams, accordingly.
21. Write down the microinstructions for the fetch phase of the instruction cycle. 5
22. Consider a direct-mapped cache of size 32 KB with block size 32 bytes. The 5
CPU generates 32-bit address. Find the no of bits required for cache indexing
and tag bits.
23. Indicate whether the following constitute a control, status, or data transfer 5
commands.
a) Skip next instruction if flag is set.
b) Seek a given record on a magnetic disk.
c) Check if I/O device is ready.
d) Move printer paper to beginning of next page.
e) Read interface status register.
24. Consider a shared bus parallel computer built using 32-bit RISC processor 5
running at 15MHz with CPI of 1. Assume that 15% of the instructions are loads
and 10% are stores. Assume 0.95 hit ratio to cache for read and write through
caches. The bandwidth of the bus is 2GB/sec.
a) How many processors can the bus support without getting saturated?
b) If caches are not there, how many processors can the bus support
assuming the main memory is as fast as the cache?
Part - C
Attempt any 5 questions out of 8 questions
Each question carries 10 Marks (10 × 5)
25. Draw the block diagram of Von-Neumann architecture computer and explain 10
roles of individual units. What are the functions of different registers available
in CPU?
26. Derive an algorithm in flowchart form for the comparism of two signed binary 10
numbers when negetive numbers are in signed-2’s complement representation:
a) By means of subtraction operation with the signed-2’s complement
numbers.
b) By scanning and comparing pairs of bits from left to right.
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27. Design an array multiplier that multiplies two 4-bit numbers. Use AND gates 10
and binary adders.
28. i) Write down a program in Stack-based architecture that performs the 10
operation, Z=A*B+(D-A/B). For each step, indent and comment the
instructions and draw the positions of top of the stack (TOS) with diagrams,
accordingly.
ii) Write down a program in Accumulator-based architecture that performs the
operation, Z=(A-B) + (C-A*B). For each step, indent and comment the
instructions and draw the architecture, accordingly.
29. Write down the sequences of control signals for the following instructions. 10
a) MOV (R1), R2 [ Reading a word from a memory ]
b) MOV R2, (R1) [ Storing a word in memory ]
30. Suppose we have a processor with a base CPI of 1.0, assuming all references 10
hit in the primary cache, and a clock rate of 4 GHz. Assume a main memory
access time of 100ns, including all the miss handling. Suppose the miss rate per
instruction at the primary cache is 2%. How much faster will the processor be
if we add a secondary cache that has a 5 ns access time for either a hit or a miss
and is large enough to reduce the miss rate to main memory to 0.5%?
31. Consider the execution of a program of 20,000 instructions by a linear pipeline 10
processor with a clock rate 40 MHz. Assume that the instruction pipeline has
five stages and that one instruction is issued per clock cycle. The penalties due
to branch instructions and out-of-order executions are ignored. Calculate the
speed up of the pipeline over its equivalent non pipeline processor, the
efficiency and throughput.
32. Evaluate the impact of pipelining on CPU performance. Identify potential 10
hazards and discuss strategies to overcome them.
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