PULP PLATFORM

Open Source Hardware, the way it should be!

Working with RISC-V

from open ISA to open Architecture to open Hardware
Part 1 of 5 : Introduction to RISC-V ISA
Luca Benini <[Link]@[Link]>
Davide Rossi <[Link]@[Link]>

[Link] @pulp_platform [Link]

 Working with RISC-V

Summary
▪ Part 1 – Introduction to RISC-V ISA
▪ What RISC-V is about
▪ Description of ISA, and basic principles
▪ Simple 32b implementation (Ibex by LowRISC)
▪ How to extend the ISA (CV32E40P by OpenHW group)

▪ Part 2 – Advanced RISC-V Architectures

▪ Part 3 – PULP concepts
▪ Part 4 – PULP Extensions and Accelerators
▪ Part 5 – PULP based chips
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RISC-V Instruction Set Architecture

▪ Started by UC-Berkeley in 2010 SW
▪ Contract between SW and HW Applications
▪ Partitioned into user and privileged spec
▪ External Debug OS
▪ Standard governed by RISC-V foundation
▪ ETHZ is a founding member of the foundation

Debug
ISA
▪ Necessary for the continuity
User Privileged
▪ Defines 32, 64 and 128 bit ISA
▪ No implementation, just the ISA
▪ Different implementations (both open and close source) HW
▪ At ETHZ+UNIBO we specialize in
efficient implementations of RISC-V cores
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RISC-V maintains basically a PDF document

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ISA defines the instructions that processor uses

C++ program
translated to
RISC-V
instructions
defined by ISA.
This will run on
ANY RISC-V
implementation
Screen shot from the excellent Compiler Explorer by Matt Godbolt
[Link] |
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RISC-V Ecosystem
▪ Binutils – upstream ▪ OS
▪ Linux, sel4, freeRTOS, zephyr
▪ GCC – upstream
▪ LLVM – upstream ▪ Runtimes
▪ Jikes, Ocaml, Go
▪ Simulator:
▪ SW maintained by different parties
▪ ”Spike” - reference
▪ Binutils and GCC by Sifive a Berkeley start-up
▪ QEMU, Gem5

▪ OpenOCD

See [Link] for an updated list

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RISC-V ISA is divided into extensions

I Integer instructions (frozen) ▪ Kept very simple and extendable
▪ Wide range of applications from IoT to HPC
E Reduced number of registers

Multiplication and Division ▪ RV + word-width + extensions

M (frozen)
▪ RV32IMC: 32bit, integer, multiplication, compressed
A Atomic instructions (frozen)

Single-Precision Floating-
▪ User specification:
F Point (frozen) ▪ Separated into extensions, only I is mandatory
Double-Precision Floating-
D Point (frozen) ▪ Privileged Specification (WIP):
C
Compressed Instructions ▪ Governs OS functionality: Exceptions, Interrupts
(frozen)
▪ Virtual Addressing
X Non Standard Extensions
▪ Privilege Levels |
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Work continues on new RISC-V extensions

▪ Foundation members work in Q Quad-precision Floating-Point
task-groups L Decimal Floating Point

▪ Dedicated task-groups B Bit Manipulation

▪ Formal specification
T Transactional Memory
▪ Memory Model
▪ Marketing P Packed SIMD

▪ External Debug Specification Dynamically Translated

J Languages
▪ ETH Zurich also contributes V Vector Operations
▪ Bit manipulation
▪ Packed SIMD, DSP N User-Level Interrupts
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What is so special about RISC-V

▪ It is FREE
▪ Everybody can build, sell, and make RISC-V cores available

▪ It is a modern design, no historical baggage

▪ Some of the more common ISAs (ARM, Intel..) have been around for 20+ years
Newer implementations, still need to be compatible to older designs.
▪ RISC-V benefited form the mistakes made by others, cleaner design
▪ Major design decisions have been properly motivated and explained

▪ Reserved space for extensions, modular

▪ Open standard, you can help decide how it is developed
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The FREEDOM in RISC-V is implementation

▪ You can access all ISAs without (many) restrictions
▪ SW tools need to be developed so that they can generate code for that ISA

▪ Most ISAs are closed. Only specific vendors can implement it

▪ To use a core that implements an ISA, you have to license/buy it from vendor
▪ Open source SW (for the ISA) is possible but building HW is not allowed

RISC-V ARM

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Are RISC-V processors better than XYZ?

▪ Actual performance depends on the implementation
▪ RISC-V does not specify implementation details (on purpose)

▪ Modern design, should deliver comparable performance

▪ If implemented well, it should perform as well as other modern ISA implementations
▪ In our experiments, we see no major weaknesses when compared to other ISAs
▪ It also is not magically 2x better

▪ High-end processor performance is not so much about ISA

▪ Implementation “details” like microarchitecture, memory hierarchy, target technology,
power management are more important.

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What is not so good about RISC-V?

▪ Still in development
▪ Some standards (privilege, vector, debug etc.) still being refined, adjusted.
▪ Tools and development environment needs to catch up.

▪ No canonical implementation (“the” RISC-V core)

▪ It is free to implement, so many people did so, resulting in many cores

▪ Higher end (out of order, superscalar) cores not yet mature

▪ In theory there is nothing to prevent a RISC-V based Linux laptop.
▪ It will take some more time until RISC-V implementations can compete with other
commercial processors (which needed hundreds of man months of work)
▪ Getting there (Alibaba XT910, SiFive P550, Esperanto ET-Maxion, Semidynamics
Avispado, Rivos ??? and more coming every day!) |
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Reduced Instruction Set: all in one page

Privilege Multiply/Divide (M)
Basic Instructions (I) Mode

Atomic Extensions (A)

Floating Point Extensions

Compressed
Instructions (C)

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RISC-V Architectural State

▪ There are 32 registers, each 32 / 64 / 128 bits long
▪ Named x0 to x31
▪ x0 is hard wired to zero
▪ There is a standard ‘E’ extension that uses only 16 registers (RV32E)

▪ In addition one program counter (PC)

▪ Byte based addressing, program counter increments by 4/8/16

▪ For floating point operation 32 additional FP registers

▪ Additional Control Status Registers (CSRs)
▪ Encoding for up to 4’096 registers are reserved. Not all are used.
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RISC-V Instructions four basic types

▪R register to register operations
▪I operations with immediate/constant values
▪ S / SB operations with two source registers
▪ U / UJ operations with large immediate/constant value

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Encoding of the instructions, main groups

▪ Reserved opcodes for standard extensions
▪ Rest of opcodes free for custom implementations
▪ Standard extensions will be frozen/not change in the future

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RISC-V is a load/store architecture

▪ All operations are on internal registers

▪ Can not manipulate data in memory directly

▪ Load instructions to copy from memory to registers

▪ R-type or I-type instructions to operate on them
▪ Store instructions to copy from registers back to memory
▪ Branch and Jump instructions

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Constants (Immediates) in Instructions

▪ In 32bit instructions, not possible to have 32b constants
▪ Constants are distributed in instructions, and then sign extended
▪ The Load Upper Immediate (lui) instruction to assemble/push constants

▪ Instruction types according to immediate encoding

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Load from memory (ld), how immediates work

ld x9, 64(x22)

Sign extend

32b memory address Memory

▪ Not possible to fit a 32b address in 32b encoding directly

▪ Take the content in source (rs1), add the immediate (imm) to it. This is the address
▪ Read from this address in the memory and load into the destination (rd) register

▪ RISC-V tries to minimize number of instructions

▪ The ld instruction seems overly complicated, but you can use this for everything
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Branching, how addresses come together

bne x10, x11, 2000 // if x10 != x11, jump 2000 ahead

▪ Similar problem, how to encode jump address in branches

▪ Branch on Equal (beq) and Branch on Not Equal (bne)
▪ They use B type operations, need two source registers

▪ Jumps are relative to Program Counter (PC)

▪ The immediate (constant) shows how far we have to jump (PC-relative addressing)
▪ Works addresses within ± 4096. To branch further, we need several instructions.

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RISC-V Instruction Length is Encoded

▪ LSB of the instruction tells how long the instruction is
▪ Supports instructions of 16, 32, 48, 64, 80, 96, … , 320 bit
▪ Allows RISC-V to have Compressed instructions

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Compressed Instruction extension ‘C’

▪ Use 16-bit instructions for common operations
▪ Code size reduction by 34%
▪ Compressed instructions increase fetch-bandwidth
▪ Allow for macro-op fusion of common patterns

x86-64: 3.71 bytes / instruction RV64IC: 3.00 bytes / instruction |

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So, how to build RISC-V cores?

▪ RISC-V ISA tells you the function
▪ You know which instructions are supported
▪ How they are encoded
▪ What they are supposed to do

▪ It does not tell you any implementation details

▪ Pipeline stages, memory hierarchy, computation units, in-order or out–of order
▪ Everyone is free to figure out how to best implement these

▪ Need to come up with a micro-architecture to implement it

▪ Determine which standard extensions are supported, how
▪ Choose a micro-architecture that fits performance requirements
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What are the Performance Metrics

▪ Area ▪ CPU Design:
▪ in kGE equivalent (# of simple logic ▪ IPC (Instructions per cycle)
gates) or mm2 (technology dependent) ▪ IPC implicitly measured in commonly used
benchmarks (Coremark, Dhrystone, SpecInt)
▪ Frequency: ▪ Energy Efficiency: OPs/Joule
▪ Depends on # of gates on longest path
▪ Hardware Designer
▪ Power: ▪ Tries to find a good balance
▪ Strongly depends on the above metrics ▪ Application dependent
▪ Leakage: dissipated even when not ▪ IoT and HPC have different requirements
working (Area) ▪ One size does not fit all
▪ Dynamic Power: dissipated on logic
transitions (frequency and area) |
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RISC-V cores developed at ETH Zurich

32 bit 64 bit
Low Cost DSP Streaming Linux
Core Enhanced Compute capable Core
Core Core
▪ Zero-riscy ▪ RI5CY ▪ Snitch ▪ Ariane
▪ RV32-ICM ▪ RV32-ICMFX ▪ RV32- ▪ RV64-IC(MA)
▪ Micro-riscy ▪ SIMD ICMDFX ▪ Full
▪ HW loops privileged
▪ RV32-CE ▪ Bit specification
manipulation
▪ Fixed point

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Zero-riscy / Ibex, small core for control applications

▪ 2-stage pipeline
▪ Optimized for area
▪ Area:
19 kGE (Zero-riscy)
12 kGE (Micro-riscy)
▪ Critical path:
~ 30 logic levels
▪ Two Configurations:
▪ New name: Ibex ▪ Zero-riscy: RV32IMC (2,44 Coremark/MHz)
▪ LowRISC has taken over ▪ 32 registers, hardware multiplier
Zero/Micro-Riscy in 2019
▪ Micro-riscy : RV32EC (0,91 Coremark/MHz)
▪ 16 registers (E), software emulated multiplier
P. Davide Schiavone et al., "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things
applications," 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017, pp. 1-8. |
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Ibex continues to grow with LowRISC

40+ Contributors
680 Pull Requests
314 GitHub Issues

Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage (or optionally 3-
stage) pipeline that implements the RV32IMCB instruction set architecture.

Since being contributed to lowRISC by ETH Zürich, it has seen substantial investment of
development effort
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Roadmap of Ibex

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Growth of Ibex measured with Coremark/MHz

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RI5CY / CV32E40P our main 32bit RISC-V core

▪ Zero-riscy / Ibex is suitable for simple applications
▪ Control applications, book-keeping

▪ For number crunching, we need more capable cores

▪ Mainly used in clusters for signal processing / machine learning applications

▪ Tuned for energy efficiency

▪ Not necessarily lowest power

▪ Make use of custom extensions

▪ The Xpulp extensions enhance the capabilities
▪ Several Xpulp extensions in discussions for ratification
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Simplified pipeline for RI5CY / CV32E40P

Instruction Memory Data Memory
Instruction Instruction
Data Write Data Address Data Read
Address Read

Execute / Write Back

Register Address Register

Decode / Execute
Program Counter
File Generation File

Fetch / Decode
Read Unit Write

PC Align
Generation Decompress

Decode
Execute
Operands
Units
Forward

Jumps / Branches

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RI5CY: Our 32-bit workhorse

▪ 4-stage pipeline
▪ 41 kGE
▪ Coremark/MHz 3.19

▪ Includes Xpulp
extensions
▪ SIMD ▪ Different Options:
▪ Fixed point ▪ FPU: IEEE 754 single precision
▪ Bit manipulations ▪ Including hardware support for FDIV, FSQRT, FMAC, FMUL

▪ HW loops ▪ Privilege support:

▪ Supports privilege mode M and U
M. Gautschi et al., "Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices," in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp. 2700-2713, Oct. 2017. |
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RISC-V has space for custom instructions (X)

▪ There is a reserved decoding space for custom instructions
▪ Allows everyone to add new instructions to the core
▪ The address decoding space is reserved, it will not be used by future extensions
▪ Implementations supporting custom instructions will be compatible with standard ISA
▪ Code compiled for standard RISC-V will run without issues
▪ The user has to provide support to take advantage of the additional instructions
▪ Compiler that generates code for the custom instructions

▪ We use a lot this degree of freedom

▪ Great tool for exploring
▪ The goal is to help ratify these extensions as standards through working groups
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Our extensions to RI5CY & support in GCC, LLVM

▪ Post–incrementing load/store instructions
▪ Hardware Loops ([Link], [Link], [Link])
▪ ALU instructions
▪ Bit manipulation (count, set, clear, leading bit detection)
▪ Fused operations: (add/sub-shift)
▪ Immediate branch instructions

▪ Multiply Accumulate (32x32 bit and 16x16 bit)

▪ SIMD instructions (2x16 bit or 4x8 bit) with scalar replication option
▪ add, min/max, dotproduct, shuffle, pack (copy), vector comparison

For 8-bit values the following can be executed in a single cycle

([Link].b)
Z = D 1 × K1 + D 2 × K2 + D 3 × K3 + D 4 × K4 |
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RI5CY ISA extensions improve performance

for (i = 0; i < 100; i++)
d[i] = a[i] + b[i];
Baseline Auto-incr load/store HW Loop Packed-SIMD
mv x5, 0 mv x5, 0 [Link] 100, Lend [Link] 25, Lend
mv x4, 100 mv x4, 100 lb x2, 0(x10!) lw x2, 0(x10!)
Lstart: Lstart: lb x3, 0(x11!) lw x3, 0(x11!)
lb x2, 0(x10) lb x2, 0(x10!) add x2, x3, x2 [Link].b x2, x3, x2
lb x3, 0(x11) lb x3, 0(x11!) Lend: sb x2, 0(x12!) Lend: sw x2, 0(x12!)
addi x10,x10, 1 addi x4, x4, -1
addi x11,x11, 1 add x2, x3, x2
add x2, x3, x2 sb x2, 0(x12!)
sb x2, 0(x12) bne x4, x5, Lstart
addi x4, x4, -1
addi x12,x12, 1
bne x4, x5, Lstart

11 cycles/output 8 cycles/output 5 cycles/output 1,25 cycles/output

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Runtime for three different applications

RV32IMCXpulp
Extensions have more effect RV32IMC
RV32EC
x53.4 x3.5
x1 x1

x1.3
Better

x6.1

2D Convolution EEMBC Coremark Scheduler Application |

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Different cores for different area budgets

x2.2

x3.5
Better

RV32IMCXpulp RV32IMC RV32EC |

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Different cores for different power budgets

x2.4
x2.7
Better

RV32IMCXpulp RV32IMC RV32EC

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Energy Efficiency: 2D-Convolution @55MHz, 0.8V

More frequent events/ processing
RV32IMCXpulp
RV32IMC
RV32EC

41.6 ms

Better
4.78 ms

784 μs 649 ms 31 s

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This was a short overview of basics of RISC-V

▪ Tomorrow, more advanced cores
▪ 64bit RISC-V core
▪ Discussion on performance
▪ Vector processing

▪ On Wednesday-Friday, we learn about PULP systems

▪ Cores alone can not do much, they need a system around
▪ Many core systems
▪ Managing Data
▪ Acceleration
▪ Actual Integrated Circuits from the PULP group
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Luca Benini, Davide Rossi, Andrea Borghesi, Michele Magno, Simone
Benatti, Francesco Conti, Francesco Beneventi, Daniele Palossi, Giuseppe
Tagliavini, Antonio Pullini, Germain Haugou, Manuele Rusci, Florian Glaser,
Fabio Montagna, Bjoern Forsberg, Pasquale Davide Schiavone, Alfio Di
Mauro, Victor Javier Kartsch Morinigo, Tommaso Polonelli, Fabian Schuiki,
Stefan Mach, Andreas Kurth, Florian Zaruba, Manuel Eggimann, Philipp
Mayer, Marco Guermandi, Xiaying Wang, Michael Hersche, Robert Balas,
Antonio Mastrandrea, Matheus Cavalcante, Angelo Garofalo, Alessio
Burrello, Gianna Paulin, Georg Rutishauser, Andrea Cossettini, Luca
Bertaccini, Maxim Mattheeuws, Samuel Riedel, Sergei Vostrikov, Vlad
Niculescu, Hanna Mueller, Matteo Perotti, Nils Wistoff, Luca Bertaccini, Thorir
Ingulfsson, Thomas Benz, Paul Scheffler, Alessio Burello, Moritz Scherer,
Matteo Spallanzani, Andrea Bartolini, Frank K. Gurkaynak,
and many more that we forgot to mention
[Link] @pulp_platform