Static Random-Access Memory
(SRAM)
Architecture, Operation, and Advanced Topologies
Table of Contents
1. Introduction to SRAM
2. The Standard 6T Cell Architecture
3. Operational Mechanisms (Read/Write)
4. Stability and Noise Margins
5. Advanced Cell Topologies (8T & 10T)
1. Introduction to SRAM
Static Random-Access Memory (SRAM) is a highly volatile memory technology that retains its data
state as long as power is supplied, without the need for periodic refresh cycles. Because of its
extremely fast access times, SRAM is the undisputed standard for on-chip cache memory (L1, L2,
and L3 caches) in modern microprocessors. However, this speed comes at the cost of a larger
physical footprint compared to DRAM.
2. The Standard 6T Cell Architecture
The fundamental building block of SRAM is the 6-Transistor (6T) cell. Its robust design relies on a
bistable latch mechanism to hold a binary state.
• Cross-Coupled Inverters: Two CMOS inverters are connected back-to-back. The output of
the first inverter drives the input of the second, and vice versa. This positive feedback loop
locks the node voltages to opposite logic levels (0 and 1).
• Access Transistors: Two NMOS pass-transistors connect the internal nodes of the latch to the
external Bit-Lines (BL and BL_bar).
• Word-Line (WL): The gates of the access transistors are tied to the Word-Line, which controls
when the cell is accessed for reading or writing.
3. Operational Mechanisms
3.1 The Read Operation
Reading data from a 6T SRAM cell is a delicate operation that requires careful transistor sizing to
prevent accidental data flipping (Read Upset).
1. Precharge: Both bit-lines (BL and BL_bar) are precharged to V .
DD
2. Access: The Word-Line (WL) is asserted (driven high).
3. Discharge: The internal node of the cell that holds a logic '0' will pull down its corresponding
bit-line through the access transistor and the pull-down NMOS. The other bit-line remains near
VDD.
4. Sensing: A highly sensitive Sense Amplifier detects the small voltage differential between the
two bit-lines and amplifies it to full logic levels.
3.2 The Write Operation
Writing requires external drivers to overpower the cell's internal feedback loop.
1. Drive: The Write Driver forces the bit-lines to the desired state (e.g., BL = 0, BL_bar = V ).
DD
2. Access: The Word-Line is asserted.
3. Flip: The forced bit-line voltages overpower the weaker cross-coupled inverters, forcing the
internal nodes to flip to the new data state.
4. Stability and Noise Margins
The reliability of an SRAM cell is measured by its Static Noise Margin (SNM). SNM is defined as
the maximum DC noise voltage that can be superimposed on the cross-coupled nodes without
flipping the cell's state.
The Butterfly Curve: SNM is typically analyzed graphically by plotting the Voltage Transfer
Characteristics (VTC) of the two inverters against each other. The resulting shape is a "butterfly
curve." The SNM is the side length of the largest square that can be inscribed within the lobes of
this curve.
SRAM design involves an inherent trade-off: Read Stability requires weak access transistors
relative to the pull-down transistors to prevent the internal '0' node from rising too high during a
read. Conversely, Write-ability requires strong access transistors relative to the pull-up transistors
to successfully pull down a high node during a write.
5. Advanced Cell Topologies
As transistor sizes shrink into the single-digit nanometer regimes, maintaining adequate read
stability and write margins in a standard 6T cell becomes increasingly difficult due to process
variations and lower supply voltages.
• 8T SRAM: Adds an isolated read port (two additional transistors) to the standard 6T cell. This
completely decouples the read operation from the internal storage nodes, eliminating read
upsets and allowing for aggressive voltage scaling.
• 10T SRAM: Employs further sophisticated read/write decoupling and leakage-reduction
techniques, often used in ultra-low-power applications where sub-threshold operation is
required.