• Microprocessors are multipurpose devices that can be designed for

generic or specialized functions.

• It is an integrated circuit contained on a single silicon chip, a
microprocessor consists of the arithmetic logic unit, control unit,
internal memory registers, and other vital circuitry of a computer's
central processing unit (CPU).
• A central processing unit (CPU) contained within a single chip
(integrated circuit). The term originated in the 1970s when processors
were first miniaturized. Today, all CPUs are microprocessors, and server,
desktop, laptop, smartphone and tablet microprocessors have more
than one processing unit (dual core and multicore)
8085 Microprocessor
• 8 bit Microprocessor
• 40 pin DIP (Dual Inline package)

• Based on Von-Neumann architecture in which the data and instructions

are in the same memory space without any distinction between them.
That means it uses the same bus for data and address, so speed of
operation is less compared to harvard architecture where separate
address and data buses are there to access address and data from from
the respective memory space.
• 5V, 3 MHz (internal) processor, 8 bit data and upto 16 bit address by
multiplexing.
Pin Diagram of 8085
Arithmetic & Logic unit:
Performs 8 bit arithmetic and logic operations.
Accumulator:
8 bit register, Also known as register A.
Most important general purpose register in 8085.
During arithmetic and logical operations, one of the operands will be in the accumulator, also
the results will be stored in accumulator.
Temperory register:
8 bit register to hold the second operand and intermediate results during arithmetic and logical
operations.
Not accessible to the programmer.
W and Z registers:
8 bit temperory registers, can be used as WZ register pair to hold the 16bit address while
executing certain instructions such as LDA C234H
B,C,D,E, H and L Registers:
All are 8 bit general purpose registers. But if needed we can use
register pairs as BC, DE, and HL to store the 16 bit information where
left side register in each pair contain the most significant byte and the
right side register contains the least significant byte.
HL register pair is more important as it has more functions such as it
can be used as a memory pointer while accessing memory location
with 16 bit address , also one operand during a 16bit addition etc
should be in the HL register pair.
Also there are more ways to address the HL register pair compared to
other register pairs.
FLAG Register in 8085:
Program Counter:
Program counter (PC) is a 16 bit register.
It contains the address of the next instruction to be executed.
After fetching the address from PC, it increaments by one.
Instruction Register:
Instruction register is a special purpose register used to receive the 8 bit opcode portion of an
instruction.
not accessible to the programmer.
Instruction Decoder:
Instruction decoder decodes the information present in the Instruction register. Based on that
the timing and control unit generates the timing sequences for executing that instruction.
Stack Pointer:
Stack pointer is a special purpose 16-bit register.
holds the address of the top of the stack.
Timing and Control Unit:
Responsible for generating timing and control signals to coordinate all the activities inside and
outside the 8085 microprocessor to obtain its
desired output.
The extrnal oscillator frequency is divided by 2 internally and the approximate maximum
internal frequency of operation of 8085 microprocessor is 3 MHz.
For an internal frequency of 3 MHz, the clock cycle or T state of 8085 is 333nS.
Also the minimum internal frequency of operation of 8085 is 500KHz.
Multiplexer / Demultiplexer
The registers B,C, D,E, H and L are connected to the internal data bus. So to choose a particular
register during a register write or read operation,we need to select the specific register as given
in the instruction.
MUX for register read and DeMUX for register write.
The Register select unit provides appropriate code to MUX or DeMUX to select the specific
register in the instruction.
Address/Data Buffers:
The purpose of the buffer is to provide a
means for electrically disconnecting the
output pin from the external bus when not
actually outputting data and the bus is
being driven from a different device.
The buffers are bidirectional when used for
data and unidirectional when used for
address.

Fig. Example for a Tristate buffer

Interrupts :
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 hardware interrupt signals, i.e. TRAP,
RST 7.5, RST 6.5, RST 5.5, and INTR.
An interrupt controller is an integrated circuit that helps microprocessor to handle
interrupt requests coming from multiple different sources (like external I/O devices)
which may come simultaneously.
The TRAP has the highest priority followed by RST 7.5, RST 6.5, RST 5.5.
Serial I/O Controller:
8085 Microprocessor has two Serial Input/Output pins that are used to read/write
one bit data to and from peripheral devices.
SOD and SID pins.
Introduction to Microprocessor languages:
ü Microprocessors can recognise and operate with binary numbers alone.
ü Each microprocessor have its own binary words, meanings and languages for its operation.
ü The Word or Word length is the number of bits the microprocessor can recognise and
process at a time. It can range from 4 bits (low speed) to 64 bits (high speed) or even more.
ü A byte is a group of 8 bits, or it consists of two nibbles (lower and upper 4 bits in a group of 8
bits)

ü To communicate with a microprocessor, one must give instructions in Binary language

(Machine language) which the specific processor can understand.
ü To overcome the difficulty in writing instructions with 0’s and 1’s, microprocessor
manufacturers have formulated English like words to represent the binary instructions
specific for a processor, called Assembly language.
ü The programs written in assembly language is not transferrable from one processor to
another ( because processor specific).
ü To overcome this , general purpose languages such as FORTRAN, ‘C’, Python etc are formed,
which are processor independent, called High level languages
Contd…
üAn Instruction is a binary pattern used to command the microprocessor to perform
a specific function.
üThe microprocessor developer selects combinations of bit patterns and gives
specific meaning to each combination by using electronic logic circuits, and is called
an Instruction. For example an 8 bit processor can have 28 = 256 combinations of
eight bits, or 256 words. Instructions are made up of one or several words.
üThe set of instructions made for a processor makes up its specific Binary or
Machine Language.
ü8085 is an 8 bit processor, with 74 different instructions.
üFor convenience, we can use hexadecimal code corresponding to a binary code, ie,
00110010 is a binary number can be written as 3216 or 32 H. But it is still difficult to
write and understand programs using hex values.
üTo overcome this, manufacturers developed a symbolic code for each instruction
called mnemonic, which are processor specific. As an example binary code
00111100 or 3C H is represented by INR A, instruction to increment accumulator
register by one.
üThe complete set of 8085 mnemonics is called 8085 assembly language.
üMachine Language and Assembly language are processor specific and are called
Low Level Languages.
Contd…
üSince the microprocessor can understand only binary values, the programs
written in assembly language has to be translated to binary equivalent either
manually (Hand assembly) or with the help of Assembler.
üAssembler is a program which translates the mnemonics into its corresponding
binary machine codes.
üSimilarly processor or machine independent high level languages are translated
to binary equivalent ( object code) with the help of Compiler or Interpreter.
üCompiler is a program which translates high level languages in to machine
language . A compiler reads a given program ( source code) entirely and
translates to machine code (object code).
üInterpreter is a program which translates high level to machine language ,one
statement at a time.
Instruction Format of 8085:
• An instruction is a command to the microprocessor to perform a given task on a
specified data.
• Each instruction has two parts: one is task to be performed, called the operation
code (opcode), and the second is the data to be operated on, called the operand.
The operand (or data) can be specified in various ways. It may include 8-bit (or
16-bit) data, an internal register, a memory location, or 8-bit (or 16-bit) address.
In some instructions, the operand is implicit.
• The 8085 has 74 basic instructions and 246 total instructions. The instruction set
of 8085 is defined by the manufacturer INTEL Corporation.
• The size of 8085 instruction can be one-byte, two bytes or three bytes.
• A 1-byte instruction includes the opcode and operand in the same byte. These
instructions are stored in 8- bit binary format in memory; each requires one
memory location.
Example:
Contd….
• In a two-byte instruction, the first byte specifies the operation code and the
second byte specifies the operand. Source operand is a data byte immediately
following the opcode.
Example:

• In a three-byte instruction, the first byte specifies the opcode, and the
following two bytes specify the 16-bit address. Note that the second byte is
the low-order address and the third byte is the high-order address.
Example:
Addressing Modes in 8085:
Addressing modes refers to the way in which the operand of an instruction
is specified. In 8085 there are five addressing modes.
• Immediate Addressing
• Direct Addressing
• Register Addressing
• Register Indirect Addressing
• Implied Addressing
1. Immediate Addressing:
The data is specified in the instruction itself.
Example: MVI B, 3EH
Moves the data 3EH given in the instruction to B-register.
Contd…
2. Direct Addressing:
The address of the data is specified in the instruction. The data will be in the
memory.
Example: LDA 1050H
Load the data available in memory location 1050H in accumulator
3. Register Addressing :
The instruction specifies the name of the register in which the data is available.
Example: MOV A, B
Moves the content of B-register to A-register.
4. Register Indirect Addressing:
The instruction specifies the name of the register in which the address of the
data is available. Here the data will be in memory and the address will be in a
register pair.
Example: MOV A, M
The memory data addressed by HL pair is moved to A-register.
Contd….
5. Implied Addressing:
In implied addressing mode, the instruction itself specifies the data to be
operated.
Example: CMA
Complements the content of accumulator.
Instruction Cycle in 8085:
• The Program and data which are stored in the memory, external to the microprocessor
are used for executing the complete instruction.
• The sequence of operations that a processor has to carry out while executing an
instruction is called instruction cycle.
• Each instruction cycle of a processor in turn consists of a number of machine cycles.
Thus to execute a complete instruction of the program, the following steps should be
performed by the 8085 microprocessor.
Ø Fetching the opcode from the memory;
Ø Decoding the opcode to identify the specific set of instructions;
Ø Fetching the remaining Bytes left for the instruction, if the instruction
length is of 2 Bytes or 3 Bytes;
Ø Executing the complete instruction procedure.
The given steps altogether constitute the complete instruction cycle.
Machine Cycle in 8085:
• The time required to access the memory or input/output devices is called Machine cycle.
• To execute an instruction, the processor will run one or more machine cycles in a particular
order.
• The seven Machine Cycle in 8085 Microprocessor are :
• Opcode Fetch Cycle
• Memory Read
• Memory Write
• I/O Read
• I/O Write
• Interrupt Acknowledge
• Bus Idle
T-State:
• The machine cycle and instruction cycle takes multiple clock periods.
• The T-state is the time period of the internal clock signal of the processor.
• A portion of an operation carried out in one system clock period is called as T- state.
• The time taken by the processor to execute a machine cycle is expressed in T-state
Instruction Set in 8085:
Classified as,
1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Branching Instructions
5. Machine Control Instructions
Data Transfer Instructions:
• The instructions that moves (copies) data between registers or between
memory location and register.
• In all data transfer operations, the content of source register or memory is
not altered. Hence the data transfer is copying operation.
Data transfer instructions contd…:
• MOV Rd, Rs (Rd) ← (Rs)
• The content of source register (Rs) is copied to the destination register (Rd). The registers Rd
and Rs can be any one of the general purpose registers A, B, C, D, E, H or L.
• No flags are affected.

• One byte instruction

• One machine cycle : Opcode fetch - 4T
• Register addressing
• Total number of instructions = 49
Contd…
• MOV Rd, M (Rd) ← (M) or (Rd) ← ((HL))
• The content of memory (M) addressed by the HL pair is moved to the destination register (Rd).
The register Rd can be any one of the general purpose registers A, B, C, D, E, H or L.
• No flags are affected.
• One byte instruction
• Two machine cycles:
Opcode fetch - 4T
Memory read - 3T
Total - 7T
• Register indirect addressing
• Total number of instructions = 7
MOV A, M MOV B, M MOV C, M MOV D, M MOV E, M MOV H, M MOV L, M
Contd…

• MOV M, Rs (M) ← (Rs) or ((HL)) ← (Rs)

• The content of source register (Rs) is moved to the memory location addressed by HL pair. The
register Rs can be any one of the general purpose registers A, B, C, D, E, H or L.
• No flags are affected.
• One byte instruction
• Two machine cycles :
Opcode fetch - 4T
Memory write - 3T
• Register indirect addressing
• Total number of instructions = 7
MOV M,A MOV M,B MOV M, C MOV M, D MOV M, E MOV M, H MOV M, L
Data transfer Instructions Contd….
• MVI Rd, d8 (Rd) ← d8
• The 8-bit data (d8) given in the instruction is moved to the destination register
(Rd). The register Rd can be any one of the general purpose registers A, B, C, D,
E, H or L.
• No flags are affected.
• Two byte instruction
• Two machine cycles:
Opcode fetch - 4T
Memory read - 3T
• Immediate addressing mode
• Total number of instructions = 7
MVI A, d8 MVI B, d8 MVI C, d8 MVI D, d8 MVI E, d8 MVI H, d8 MVI L, d8
Contd…
• MVI M, d8 (M) ← d8 or ((HL)) ← d8
• The 8-bit data (d8) given in the instruction is moved to the memory location
addressed by the HL pair.
• No flags are affected.
• Two byte instruction
• Three machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Memory write - 3T
• Register indirect addressing
• Or Immediate addressing
• Total number of instructions = 1
Contd…
• LDA addr16 (A) ← (M) or (A) ← (addr16)
• The content of the memory location whose address is given in the instruction, is
moved to accumulator.
• No flags are affected.
• Three byte instruction
• Four machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Memory read - 3T
• Memory read - 3T

• Direct addressing
• Total number of instructions = 1
Contd …
• LHLD addr16 (L) ← (M) or (L) ← (addr16)
(H) ← (M) or (H) ← (addr16 + 01)
• The content of the memory location whose address is given in the instruction, is
moved to the L-register. The content of the next memory location is moved to the H-
register.
• No flags are affected.
• Three byte instruction
• Five machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• Memory read - 3T
• Memory read - 3T
• Memory read - 3T

• Direct addressing
• Total number of instructions = 1
Data Transfer Instructions Contd….
• LXI rp, d16 (rp) ← d16
• The 16-bit data given in the instruction is moved to the register pair (rp). The
register pair can be BC, DE, HL or SP.

• Three byte instruction

• Three machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 4
LXI B, d16 LXI D, d16 LXI H, d16 LXI SP, d16
Contd….
• LDAX rp (A) ← (M) or (A) ← ((rp))
• The content of the memory addressed by the register pair (rp) is moved to the
accumulator. (The content of the register pair is the memory address). The
register pair can be either BC or DE.
• One byte instruction
• Two machine cycles:
• Opcode fetch - 4T
• Memory read - 3T

• Register indirect addressing

• Total number of instructions = 2
LDAX B LDAX D
Contd….
• STA addr16 (M) ← (A) or (addr16) ← (A)
• The content of the accumulator is moved to the memory . The address of the
memory location is given in the instruction.
• No flags are affected.
• Three byte instruction
• Four machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• Memory read - 3T
• Memory write- 3T
• Direct addressing Mode
• Total number of instructions = 1
Contd….
• SHLD addr16 (M) ← (L) or (addr16) ← (L)
(M) ← (H) or (addr16+1) ← (H)
• The content of the L-register is stored in the memory location, whose address is given
in the instruction. The content of the H-register is stored in the next memory location.
• No flags are affected.
• Three byte instruction
• Five machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• Memory read - 3T
• Memory write - 3T
• Memory write - 3T

• Direct addressing
• Total number of instructions = 1
Data transfer instructions Contd….
• SPHL (SP) ← (HL)
• The content of the HL pair is moved to the Stack Pointer (SP).
• No flags are affected.
• One byte instruction
• One machine cycle:
• Opcode fetch - 6T

• Implied addressing
• Total number of instructions = 1
Data transfer instructions contd….
XCHG (E) ↔ (L)
(D) ↔ (H)
• The content of the HL pair is exchanged with the DE pair.
• No flags are affected.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T

• Implied addressing
• Total number of instructions = 1
Contd…
PUSH rp (SP) ← (SP) – 1 ; ((SP)) ← (rp)H
(SP) ← (SP) – 1 ; ((SP)) ← (rp)L
• The content of the register pair (rp) is pushed to the stack. After execution of this
instruction, the content of the Stack Pointer (SP) will be 02 less than the earlier value.
• The register pairs can be BC, DE , HL and PSW.
• No flags are affected.
• PSW (Program Status Word) : Accumulator and Flag register together called PSW.
Accumulator is high order register and Flag register is low order register.
• The instruction is executed as follows:
(i) The content of the SP is decremented by one.
(ii) The content of the high order register is moved to memory addressed by SP.
(iii) The content of the SP is decremented by one.
(iv) The content of the low order register is moved to memory addressed by SP
Contd….
• One byte instruction
• Three machine cycles:
• Opcode fetch - 6T
• Memory write - 3T
• Memory write - 3T
• Register indirect addressing

• Total number of instructions = 4

PUSH PSW PUSH B PUSH D PUSH H
Contd…
POP rp (rp)L ← ((SP)) ; (SP) ← (SP) + 1
(rp)H ← ((SP)) ; (SP) ← (SP) + 1
• The content of top of stack memory is moved to the register pair. After execution of
this instruction the content of the Stack Pointer (SP) will be 02 greater than the earlier
value.
• The register pairs can be BC, DE , HL and PSW.
• No flags are affected.
• PSW (Program Status Word) : Accumulator and Flag register are together called PSW.
The accumulator is a high order register and the flag register is a low order register.
• The pop instruction is executed as follows:
(i) The content of the memory addressed by the SP is moved to the low order register.
(ii) The content of the SP is incremented by one.
(iii) The content of the memory addressed by the SP is moved to the high order register.
(iv) The content of the SP is incremented by one.
Contd….

• One byte instruction

• Three machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• Memory read - 3T

• Register indirect
addressing
• Total number of
Contd….
IN addr8 (A)← (addr8)
• The content of the port is moved to the A-register.
• The 8-bit port address will be given in the instruction.
• No flags are affected.
• Two byte instruction
• Three machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• IO read - 3T

• Direct addressing
• Total number of instructions = 1
Data transfer instructions Contd….
OUT addr8 (addr8) ← (A)
• The content of the A-register is moved to the port.
• The 8-bit port address will be given in the instruction.
• No flags are affected.
• Two byte instruction
• Three machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• IO write - 3T

• Direct addressing
• Total number of instructions = 1
[In an 8085 processor-based system when the IO devices are mapped by IO mapping then the processor can communicate
with these IO devices only by using IN and OUT instructions. The processor uses an 8-bit address to select IO-mapped IO
devices.]
Stack in 8085:
• The stack is a portion of RAM memory defined by the user for temporary storage and retrieval of data while
executing a program.
• The microprocessor will have a dedicated internal register called Stack Pointer (SP) to hold the address of the stack.
• Also, the processor will have a facility to automatically decrement/increment the content of SP after every
write/read operation into stack.
• The user can initialize or create a stack by loading a RAM address in the Stack Pointer (SP).
• Once an address is loaded in SP, the RAM memory locations below the address pointed by SP are reserved for
stack. Typically 25 to 100 RAM memory locations are sufficient for stack.
• The user should take care that the reserved RAM memory locations for stack are not used for any other purpose.
• The user has to create/implement a stack whenever the program consists of PUSH, POP, RST n, CALL and RET
instructions. Also, the stack is needed whenever the system uses interrupt facility.
• In a program, when the number of the available registers are not sufficient for storing intermediate result and data,
then some of intermediate result and data can be stored in a stack using PUSH instruction and retrieved whenever
required using POP instruction.
• The CALL instruction and the interrupts store the return address (content of program counter) in the stack before
executing the subroutine. Usually the subroutines are terminated with RET instruction. When RET instruction is
executed, the top of stack is poped to program counter and the program control returns to the main program after
the execution of subroutine.
Stack in 8085 contd…

• In an 8085 processor, for every write operation into

stack, the SP is automatically decremented by two and
for every read operation from stack, the SP is
automatically incremented by two.
• Hence, data can be stored only in lower addresses
from the address pointed by SP. Therefore, we can say
that the SP holds the address of the top of stack.
• The storage and retrieval in stack are in reverse order,
because the SP is decremented for every write
operation into stack and SP is incremented for every
read operation from stack. Therefore, the stack in
8085 is called Last-In-First-Out (LIFO) stack, i.e., the
last stored information can be read first.
Fig. Example for Stack in 8085
Arithmetic Instructions in 8085:
ADD reg (A) ← (A) + (reg)
• The content of the register is added to the content of the accumulator (A-register). After
addition the result is stored in the accumulator.
• All flags are affected.
• The register can be any one of the general purpose register A, B, C, D, E, H or L.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Register addressing

• Total number of instructions = 7

ADD A ADD B ADD C ADD D ADD E ADD H ADD L
Arithmetic Instructions Contd….
ADI d8 (A) ← (A) + d8
• The 8-bit data given in the instruction is added to the content of the A-register
(Accumulator). After addition, the result is stored in the accumulator.
• All flags are affected.
• Two byte instruction
• Two machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 1
Arithmetic Instructions Contd….
ADD M (A) ← (A) + (M) or (A) ← (A) + ((HL))
• The content of memory addressed by HL pair is added to the content of the A-
register. After addition, the result is stored in the A-register.
• All flags are affected.
• One byte instruction
• Two machine cycles:
• Opcode fetch - 4T
• Memory read - 3T

• Register indirect addressing

• Total number of instructions = 1
Arithmetic Instructions Contd….
ACI d8 (A) ← (A) + d8 + CF
• The 8-bit data given in the instruction and the carry flag (the value of carry flag
before executing this instruction) are added to the content of the A-register
(Accumulator). After addition, the result is stored in the accumulator.
• All flags are affected.
• Two byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 1
Arithmetic Instructions Contd….
ADC reg (A) ← (A) + (reg) + CF
• The content of the register and the carry flag are added to the content of the A-register.
After addition, the result is stored in the A-register.
• All flags are affected.
• The register can be any one of the general purpose register A, B, C, D, E, H or L.
• One byte instruction
• One machine cycle :
• Opcode fetch - 4T
• Register addressing

• Total number of instructions = 7

ADC A ADC B ADC C ADC D ADC E ADC H ADC L
Arithmetic Instructions Contd….
ADC M (A) ← (A) + (M) + CF or (A) ← (A) + ((HL)) + CF
• The content of the memory addressed by the HL pair and the value of the
carry flag (before executing this instruction) are added to the content of A-
register. After addition, the result is stored in the A-register.
• All flags are affected.
• One byte instruction
• Two machine cycles:
• Opcode fetch - 4T
• Memory read - 3 T
• Register indirect addressing
• Total number of instructions = 1
Arithmetic Instructions Contd….
INR reg (reg) ← (reg) + 01
• The content of the register is incremented by one. Except carry flag, all other
flags are affected.
• The register can be any one of the general purpose register A, B, C, D, E, H or L.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Register addressing

• Total number of instructions = 7

INR A INR B INR C INR D INR E INR H INR L
Arithmetic Instructions Contd….
INR M (M) ← (M) + 01 or ((HL)) ← ((HL)) + 01
• The content of the memory addressed by the HL pair is incremented by one.
• Except carry, all other flags are affected.
• One byte instruction
• Three machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Memory write - 3T

• Register indirect addressing

• Total number of instructions = 1
Arithmetic Instructions Contd….
INX rp (rp) ← (rp) + 01
• The content of the register pair is incremented by one.
• The register pair can be BC, DE, HL or SP.
• No flags are affected.
• One byte instruction
• One machine cycle :
• Opcode fetch - 6T
• Register addressing
• Total number of instructions = 4
INX B INX D INX H INX SP
Arithmetic Instructions Contd….
DAD rp (HL) ← (HL) + (rp)
• (DAD - Double Addition)
• The content of the register pair is added to the content of the HL pair.
After addition, the result is stored in the HL pair.
• Only the carry flag is affected.
• The register pair can be BC, DE, HL or SP.
• One byte instruction
• Three machine cycles:
• Opcode fetch - 4T
• Bus idle - 3T
• Bus idle - 3T
• Register addressing
• Total number of instructions = 4
DAD B DAD D DAD H DAD SP
MPES
Module 1_8
Arithmetic Instructions Contd….
SUB reg (A) ← (A) – (reg)
• The content of the register is subtracted from the content of the accumulator
(A-register). After subtraction the result is stored in the A-register.
• All flags are affected.
• The register can be any one of the
general purpose register A, B, C, D,
E,H or L.
Contd….

• One byte instruction

• One machine cycle:
Opcode fetch - 4T
• Register addressing
• Total number of instructions = 7
SUB A SUB B SUB C SUB D SUB E
SUB H SUB L
Contd….
SUI d8 ( A ) ← (A) – d8
• The 8-bit data given in the instruction is subtracted from the A-register (accumulator). After subtraction, the
result is stored in the A-register.
• All flags are affected.
• Two byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 1
SUB M (A) ← (A) – (M) or (A) ← (A) – ((HL))
• The content of the memory addressed by the HL pair is subtracted from the A-register. After subtraction, the
result is stored in the A-register.
• All flags are affected.
• One byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Register indirect addressing
• Total number of instructions = 1
Contd….
SBB reg (A) ← (A) – (reg) – CF
• The content of the register and the value of carry (before executing this
instruction) are subtracted from the accumulator (A-register). After subtraction,
the result is stored in the accumulator.
• All flags are affected.
• The register can be any one of the general purpose register A, B, C, D, E, H or L.
• One byte instruction
• One machine cycle :
• Opcode fetch - 4T
• Register addressing
• Total number of instructions = 7
SBB A SBB B SBB C SBB D SBB E SBB H SBB L
Arithmetic Instructions in 8085 Contd…
SBI d8 (A) ← (A) – d8 – CF
• The 8-bit data given in the instruction and the value of carry (before executing this instruction) are subtracted
from accumulator. After subtraction, the result is stored in the accumulator.
• All flags are affected.
• Two byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 1
SBB M (A) ← (A) – (M) – CF or (A) ← (A) – ((HL)) – CF
• The content of the memory addressed by HL and the value of carry (before executing this instruction) are
subtracted from accumulator (A-register). After subtraction, the result is stored in the A-register.
• All flags are affected .
• One byte instruction
• Two machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• Register indirect addressing
• Total number of instructions = 1
Contd….
DCR reg (reg) ← (reg) – 01
• The content of the register is decremented by one.
• Except carry, all other flags are affected.
• The register can be A, B, C, D, E, H or L.
• One byte instruction
• One machine cycle :
• Opcode fetch - 4T
• Register addressing

• Total number of instructions = 7

DCR A DCR B DCR C DCR D DCR E DCR H DCR L
Contd…
DCR M (M) ← (M) – 01 or ((HL)) ← ((HL)) – 01
• The content of memory addressed by the HL pair is decremented by one.
• Except carry, all other flags are affected.
• One byte instruction
• Three machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Memory write - 3T

• Register indirect addressing

• Total number of
instructions = 1
Contd….
DCX rp (rp) ← (rp) – 01
• The content of the register pair is decremented by one.
• The register pair can be BC, DE, HL or SP.
• No flags are affected.
• One byte instruction
• One machine cycle :
• Opcode fetch - 6T
• Register addressing
• Total number of instructions = 4
DCX B DCX D DCX H DCX SP
MPES
Module 1_9
BCD Numbers:
• Binary coded decimal
• Binary representation of decimal numbers 0 to 9 are called BCD.
• Unpacked and Packed BCD’s are there.
• In Unpacked BCD, lower 4 bits ( lower nibble ) of one byte represents BCD
number and rest of the bits are zero.
• In Packed BCD, a single byte has two BCD numbers in it. Lower 4 bits and
upper 4 bits. Eg. 0101 1001 is packed BCD for 59 decimal.
10 D = 1010 B = A H is not a valid BCD number as BCD is from 0 to 9 only.
To convert it to valid BCD, add 06H to that.
1010 +
0110
1 0000 = 10
DAA
• (DAA - Decimal Adjust Accumulator)
• After BCD addition, the DAA instruction is executed to get the result in BCD. When DAA instruction is
executed, the content of the accumulator is altered or adjusted as explained below :
i) If the sum of the lower nibbles exceeds 09H or auxiliary carry is set, then a correction
06H (0110) is added to sum of lower nibbles.
ii) If the sum of the upper nibbles exceeds 09H or carry is set, then a correction 06H (0110) is
added to sum of upper nibble.
• After executing this instruction all flags are modified to indicate the status of the result.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Implied addressing
• Total number of instructions = 1
Eg. For BCD addition:
85 + 25 = 110 in actual BCD format.
But in binary, 1000 0101 +
0010 0101
1010 1010 is AA H , which is not a valid BCD number.
To make the result in BCD, add 06 H to both upper and lower nibbles as they exceeds 09 decimal value.
Then,
1010 1010 +
0110 0110
1 0001 0000 = 110 which is the correct answer.
DAA instruction is used after the addition instruction.
Eg:
ORG 4000 H
MOV A, 85 H
MOV B, 25 H
ADD B
DAA
HLT
Thank You
Logical Instructions in 8085
ANA reg (A) ← (A) & (reg )
(& is the symbol used for logical AND operation)
• The content of the register is logically ANDed bit by bit with the content of the accumulator. In
bit by bit AND operation, the bit D0 of register is ANDed with the bit D0 of A-register, the bit D1
of register is ANDed with bit D1 of A-register, and so on.
• The register can be any one of the general purpose register A, B, C, D, E, H or L. After execution
of the instruction, carry flag is always reset and auxiliary carry flag is always set. Other flags are
altered (according to the results).
• After AND operation, result is stored in accumulator.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Register addressing
• Total number of instructions = 7
ANA A ANA B ANA C ANA D
ANA E ANA H ANA L
ANI d8 (A) ← (A) & d8
• The 8-bit data given in the instruction is logically ANDed bit by bit with the
content of the accumulator.
• The result is stored in the accumulator.
• After execution of this instruction, CF = 0 and AF = 1. Other flags are affected.
• Two byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 1
Logical Instructions Contd….
ANA M (A) ← (A) & (M) or (A) ← (A) & ((HL))
• The content of the memory addressed by the HL pair is logically ANDed bit by bit
with the content of the accumulator.
• The result is stored in the accumulator.
• After execution, CF = 0 and AF = 1. Other flags are affected .
• One byte instruction
• Two machine cycles:
• Opcode fetch - 4T
• Memory read - 3T

• Register indirect addressing

• Total number of instructions = 1
ORA reg (A) ← (A) | (reg)
( | is the symbol used for logical OR operation)
• The content of the register is logically ORed bit by bit with the content of the accumulator. In
bit by bit OR operation, the bit D0 of the register is ORed with bit D0 of the A-register, the bit
D1 of the register is ORed with bit D1 of the A register, and so on.
• The register can be any one of the general purpose register A, B, C, D, E, H or L.
• After execution of the instruction, both the carry and auxiliary flags are always reset (AF = 0,
CF = 0). Other flags are modified (according to the result).
• After OR operation, the result is stored in the accumulator.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Register addressing
• Total number of instructions = 7
ORA A ORA B ORA C ORA D
ORA E ORA H ORA L
ORA M (A) ← (A) | (M) or (A) ← (A) | ((HL))
• The content of the memory addressed by the HL pair is logically ORed bit by bit
with the content of the accumulator.
• The result is stored in the accumulator.
• After execution, CF = AF = 0. Other flags are affected .
• One byte instruction
• Two machine cycles:
• Opcode fetch - 4T
• Memory read - 3T

• Register indirect addressing

• Total number of instructions = 1
Logical Instructions Contd….

ORI d8 (A) ← (A) | d8

• The 8-bit data given in the instruction is logically ORed bit by bit with the content
of the accumulator.
• The result is stored in the accumulator.
• After execution of this instruction, CF = AF = 0. Other flags are affected.
• Two byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 1
XRA reg (A) ← (A) ^ (reg)
( ^ is the symbol used for logical EXCLUSIVE-OR operation).
• The content of the register is logically EXCLUSIVE-ORed bit by bit with the content of the
accumulator . In bit by bit EXCLUSIVE-OR operation, the bit D0 of register is EXCLUSIVE-
ORed with bit D0 of A-register, the bit D1 of register is EXCLUSIVORed with bit D1 of A-
register, and so on.
• The register can be any one of the general purpose register A, B, C, D, E, H or L.
• After execution AF = CF = 0. Other flags are modified (according to the result).
• The result is stored in the accumulator.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Register addressing
• Total number of instructions = 7

XRA A XRA B XRA C XRA D XRA E XRA H XRA L

XRI d8 (A) ← (A) ^ d8 or (A) ← (A) ^ d8
• The 8-bit data given in the instruction is logically EXCLUSIVE-ORed bit by bit
with the content of the accumulator.
• The result is stored in the accumulator.
• After execution of this instruction, CF = AF = 0. Other flags are affected.
• Two byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 1
XRA M (A) ← (A) ^ (M) or (A) ← (A) ^ ((HL))
• The content of the memory addressed by the HL pair is logically EXCLUSIVE-ORed
bit by bit with the content of accumulator.
• The result is stored in accumulator.
• After execution, CF = AF = 0. Other flags are affected.
• One byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T

• Register indirect addressing

• Total number of instructions = 1
Logical instructions in 8085 contd….
CMP reg (A) – (reg) ⇒ Modify flags
• The content of the register is compared with the accumulator. The comparison is performed by
subtracting the content of register from the A-register. The subtraction is performed in the ALU,
and the result is used to modify flags and then the result is discarded (i.e., it is not stored in any
register). After execution of this instruction, the content of accumulator and the register are
not altered.
• All flags are affected by this instruction.
• The register can be any one of the general purpose register A, B, C, D, E, H or L.
• The status of carry and zero flag after comparison are given below :
i) If (A) < (reg) then the carry flag is set (i.e., CF = 1)
ii) If (A) > (reg) then the carry flag is reset or cleared (i.e., CF = 0)
iii) If (A) = (reg) then the zero flag is set (i.e., ZF = 1)
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Register addressing
• Total number of instructions = 7
CMP A CMP B CMP C CMP D CMP E CMP H CMP L
Contd….
CPI d8 (A) – d8 ⇒ Modify flags.
• The 8-bit data given in the instruction is compared with the accumulator. The
comparison is performed by subtracting the 8-bit data from the A-register. The
subtraction is performed in ALU and the result is used to modify flags and then
discarded. After execution of the instruction, the content of the accumulator is not
altered.
• All flags are affected.
• The status of carry and zero flag after comparision are given below :
i) If (A) < d8 then the carry flag is set (i.e., CF = 1)
ii) If (A) > d8 then the carry flag is reset or cleared (i.e., CF = 0)
iii) If (A) = d8 then the zero flag is set (i.e., ZF = 1).
• Two byte instruction
• Two machine cycles :
• Opcode fetch - 4T
• Memory read - 3T
• Immediate addressing
• Total number of instructions = 1
CMP M (A) – (M) ⇒ Modify flags or (A) – ((HL)) ⇒ Modify flags.
• The content of the memory addressed by HL pair is compared with the accumulator.
The comparison is performed by subtracting the content of memory from the A-register.
The subtraction is performed in the ALU and the result is used to modify flags and then
discarded. After execution of the instruction, the content of the accumulator and the
memory are not altered.
• All flags are affected by this instruction.
• The status of carry and zero flag after comparison are given below:
i) If (A) < (M) then the carry flag is set (i.e., CF = 1).
ii) If (A) > (M) then the carry flag is reset or cleared (i.e., CF = 0).
iii) If (A) = (M) then the zero flag is set (i.e., ZF = 1).
• One byte instruction
• Two machine cycles:
• Opcode fetch - 4T
• Memory read - 3T
• Register indirect addressing
• Total number of instructions = 1
Contd….
Logical instructions contd….
RRC Dn ← Dn+1 ; D7 ← D0 and (CF) ← D0
• (RRC - Rotate Accumulator Right to Carry)
• The content of A-register is rotated right by one bit and the right most bit of A-
register is rotated to carry. [The right most bit is least significant bit.]
• Only carry flag is affected.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Implied addressing
RAR Dn ← Dn+1 ; D7 ← (CF) and (CF ) ← D0
• (RAR - Rotate Accumulator Right through carry)
• The content of the A-register along with the carry is rotated right by one bit. Here
the carry is moved to the most significant bit position (D7 ) and the least
significant bit (D0 ) is moved to the carry.
• Only the carry flag is affected.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Implied addressing
RAL Dn +1 ← Dn ; D0 ← (CF) and (CF) ← D7
• (RAL - Rotate Accumulator Left through carry)
• The content of the A-register along with the carry is rotated left by one bit. Here
the carry is moved to the least significant bit position (D0 ) and the most
significant bit (D7 ) is moved to the carry.
• Only the carry flag is affected.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
• Implied addressing
Branching Instructions in 8085:
• The control transfer instructions include Unconditional Branch, Jump and Jump-to-
subroutine. The Branch instruction uses relative addressing while the Jump instruction
uses direct or indirect addressing.
• Sub routine is a program other than the main program which executes a specific task ,
which can be used in main programs wherever that particular task should be
performed by the help of Branching instructions or interrupts.
JMP addr16 (PC) ← addr16
• It is unconditional jump instruction. When this instruction is executed, the address
given in the instruction is moved to the program counter. Now, the processor starts
executing the instructions stored from this address.
• Three byte instruction
• Three machine cycles:
• Opcode fetch - 4 T
• Memory read - 3 T
• Memory read - 3 T
• Immediate addressing
J <condition> addr16
• If <condition> is TRUE then, (PC) ← addr16
• It is conditional jump instruction. The conditional jump instruction will check a flag condition. If the flag
condition is true, then the address given in the instruction is moved to the program counter. Thus the
program control is branched to the jump address. If the flag condition is false, then the next instruction
is executed.
• There are eight conditional jump instructions.
• JZ addr16 ; Jump on Zero - Jump if zero flag = 1.
• JNZ addr16 ; Jump on Not Zero - Jump if zero flag = 0.
• JC addr16 ; Jump on Carry - Jump if carry flag = 1.
• JNC addr16 ; Jump on No Carry - Jump if carry flag = 0.
• JM addr16 ; Jump on Minus - Jump if sign flag = 1.
• JP addr16 ; Jump on Positive - Jump if sign flag = 0.
• JPE addr16 ; Jump on Parity Even - Jump if parity flag = 1.
• JPO addr16 ; Jump on Parity Odd - Jump if parity flag = 0.
• Three byte instruction
• Two or three machine cycles:
CALL addr16 (SP) ← (SP) – 1 ; ((SP)) ← (PC)H
(SP) ← (SP) – 1 ; ((SP)) ← (PC)L
(PC) ← addr16
• It is unconditional CALL used to call a subroutine program. When this instruction is
executed, the address of the next instruction in the program counter is pushed to the
stack. The 16-bit address (which is the address of the subroutine program) given in the
instruction is loaded in the program counter. Now, the processor will start executing the
instructions stored in this call address .
• Three byte instruction
• Five machine cycles:
• Opcode fetch - 6T
• Memory read - 3T
• Memory read - 3T
• Memory write - 3T
• Memory write - 3T
• Immediate addressing
C<condition> addr16
• If <condition> is TRUE then,
(SP) ← (SP) – 1 ; ((SP)) ← (PC)H
(SP) ← (SP) – 1 ; ((SP)) ← (PC)L
(PC) ← addr16
• It is conditional subroutine call instruction. The conditional CALL instruction will check for a flag
condition. If the flag condition is true, then the address of the next instruction is pushed to the stack
and the call address (address given in the instruction) is loaded in the program counter. Now, the
processor will start executing the instructions stored in this address. If the flag condition is false, then
the next instruction is executed.
• There are eight conditional CALL instructions. These are:
• CZ addr16 ; Call on Zero - Call if zero flag = 1.
• CNZ addr16 ; Call on Not Zero - Call if zero flag = 0.
• CC addr16 ; Call on Carry - Call if carry flag = 1.
• CNC addr16 ; Call on No Carry - Call if carry flag = 0.
• CM addr16 ; Call on Minus - Call if sign flag = 1.
• CP addr16 ; Call on Positive - Call if sign flag = 0.
• CPE addr16 ; Call on Parity Even - Call if parity flag = 1.
• CPO addr16 ; Call on Parity Odd - Call if parity flag = 0.
• Immediate addressing
• Three byte instruction
RET (PC)L ← ((SP)) ; (SP) ← (SP) + 1
(PC)H ← ((SP)) ; (SP) ← (SP) + 1
• (RET - Return to the main program)
• It is an unconditional return instruction. This instruction is placed at the end of the
subroutine program, in order to return to the main program. When this instruction is
executed, the top of the stack is poped to (loaded in) the program counter .

• One byte instruction

• Three machine cycles:
• Opcode fetch - 4 T
• Memory read - 3 T
• Memory read - 3 T
Register indirect addressing
R<condition>
• If <condition> is TRUE then,
(PC)L ← ((SP)) ; (SP) ← (SP) + 1
(PC)H ← ((SP)) ; (SP) ← (SP) + 1
• It is conditional return instruction.
• In a conditional return instruction a flag condition is tested. If the flag condition is true, then
the program control return to main program by poping the top of the stack to the program
counter. If the flag condition is false, then the next instruction is executed.
• There are eight conditional return instructions:
• RZ ; Return on Zero - Return if zero flag = 1.
• RNZ ; Return on Not Zero - Return if zero flag = 0.
• RC ; Return on Carry - Return if carry flag = 1.
• RNC ; Return on No Carry - Return if carry flag = 0.
• RM ; Return on Minus - Return if sign flag = 1.
• RP ; Return on Positive - Return if sign flag = 0.
• RPE ; Return on Parity Even - Return if parity flag = 1.
• RPO ; Return on Parity Odd - Return if parity flag = 0.
• One byte instruction
• Register indirect addressing
RST n
• It is a restart instruction. The restart instructions are also called software interrupts.
Each restart instruction has a vector address. The vector address is fixed by the
manufacturer (INTEL).
• When a restart instruction is executed, the content of the program counter is pushed to
the stack and the vector address is loaded in the program counter. The vector address is
internally generated (computed) by the processor. The vector address for RST n is
obtained by multiplying n by 8. Thus the program control is branched to a subroutine
program stored in this vector address.
• One byte instruction
• Register indirect addressing
• Three machine cycles:
• Opcode fetch - 6 T
• Memory write - 3 T
• Memory write - 3 T
• There are eight restart instructions.
RST 0 RST 1 RST 2 RST 3 RST 4 RST 5 RST 6 RST 7
PCHL (PC) ← (HL)
• The content of the HL register pair is moved to the program counter. Since this
instruction alters the content of the program counter, the program control is
transferred to a new address. This instruction is used by the system designer to
implement the system subroutine to execute a program.
• One byte instruction
• One machine cycle:
• Opcode fetch - 6T
• Implied addressing
Machine control Instructions in 8085:
DI
• (DI - Disable Interrupts)
• When this instruction is executed, all the interrupts except TRAP are disabled. [When the
interrupts are disabled the processor will not accept or recognize the interrupt request made
by the external devices through the interrupt pins.]
• When the processor is doing an emergency work, it can execute DI instruction to prevent the
interrupts from interrupting the processor.
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
EI
• (EI - Enable Interrupts)
• This instruction is used (or executed) to allow the interrupts after disabling. (The interrupts
except TRAP are disabled after processor reset or after execution of DI instruction. When we
want to allow the interrupts, we have to execute EI instructions.)
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
SIM
• (SIM - Set Interrupt Mask)
• The SIM instruction is used to mask the hardware interrupts RST 7.5, RST 6.5 and RST 5.5. It is also used to send data through
the SOD line. (SOD: Serial Output Data pin of the 8085 processor.) The execution of SIM instruction uses the content of the
accumulator to perform the following functions:
• i) Program the interrupt mask for the hardware interrupts RST 5.5, RST 6.5 and RST 7.5.
• ii) Reset the edge-triggered RST 7.5 input latch.
• iii) Load the SOD output latch.
• One byte Instruction
• One machine cycle:
• Opcode fetch - 4T
[If the mask set enable bit is set to "1" then the interrupt mask bits
for RST 7.5, RST 6.5 and RST 5.5 (D0 , D1 and D2 ) are recognized
and if it is "0" then these bits are not recognized by the processor.
The interrupt mask bits D0 , D1 and D2 can be independently set
to "1" to mask the particular interrupt and reset to "0" to unmask
the particular interrupt. If the bit D4 isset to "1", then an internal
flip-flop is reset to "0" in order to disable the RST 7.5 interrupt.
If the serial output enable is "1", the serial output data is sent to
the SOD pin.]
Example program:
EI ; Enable all interrupts of 8085
MVI A,0BH ; Move 0BH to A-register
SIM ; Mask 6.5 and 5.5, Enable 7.5
RIM
• (RIM - Read Interrupt Mask)
• The RIM instruction is used to check whether an interrupt is masked or not. It is also used to read data from the
SID line. (SID: Serial Input Data pin of 8085 processor).
• When a RIM instruction is executed, the accumulator is loaded with 8-bit data. The 8-bit data in the accumulator
(content of accumulator) can be interpreted as shown in Fig.
• Bits D0 , D1 and D2 provide the mask status of the RST 5.5, RST 6.5 and RST 7.5 interrupts respectively. If the mask
bit corresponding to a particular RST is "1", then the interrupt is masked and if the mask bit is "0" then the
interrupt is unmasked.
• If the interrupt enable bit (D3 ) is "0", the 8085's maskable interrupts are disabled. The interrupts are enabled if
this bit is "1".
[A "1" in a particular interrupt pending bit indicates that an
interrupt is being requested on the identified RST line.
When this bit is "0", no interrupt is waiting to be serviced.
The serial input data (bit D7 ) indicate the value of the signal
at the SID pin. ]
• One byte instruction
• One machine cycle:
• Opcode fetch - 4T
HLT
• (HLT - Halt program Execution)
• This instruction is placed at the end of the program. When this instruction is executed,
the processor suspends program execution and bus will be in idle state.
• One byte instruction
• Two machine cycle:
• Opcode fetch - 3T
• Bus idle - 2T
NOP
• (NOP - No operation)
• The NOP is a dummy instruction, it neither achieves any result nor affects any CPU
registers. This is an useful instruction for producing software delay and reserve memory
spaces for future software modifications.
• One byte instruction
• One machine cycle :
• Opcode fetch - 4T
Timing Diagram of 8085 Instructions:
• The execution of an instruction is the execution of the machine cycles
of that instruction in a predefined order.
• Therefore, from the knowledge of the timing diagrams of machine
cycles, the timing diagram of an instruction can be obtained.

Example: STA 1250H etc….

The sequence of operations that a processor
h a s t o c a r r y o u t w h i l e e xe c u t i n g a n
instruction is called Instruction cycle.
Each instruction cycle of a processor in turn
consists of a number of machine cycles.
The time required to access the memory or
input/output devices is called Machine cycle.
To execute an instruction, the processor will
r u n o n e o r m o re m a c h i n e c yc l e s i n a
particular order.
The seven Machine Cycle in 8085
Microprocessor are :
Opcode Fetch Cycle
Memory Read
Memory Write
I/O Read
I/O Write
Interrupt Acknowledge
Bus Idle
T-State:
The T-state is the time period of the internal
clock signal of the processor.
Timing Diagram of Opcode Fetch Machine Cycle in 8085:

• Each instruction of the processor has one-byte opcode. The opcodes

are stored in memory.
• The opcode fetch machine cycle is executed by the processor to fetch
the opcode from memory.
• Hence, every instruction starts with opcode fetch machine cycle.
• The time taken by the processor to execute the opcode fetch cycle is
either 4T or 6T. In this time, the first 3T states are used for fetching
the opcode from memory and the remaining T states are used for
internal operations by the processor.
Contd…
• At the falling edge of first T-state (T1 ), the
microprocessor outputs the low byte address on
AD0 -AD7 lines and high byte address on A8 to A15
lines. ALE is asserted high to enable the external
address latch. The other control signals are asserted
as follows.
• IO/M=0, S0 = 1, S1 = 1. (IO/M is asserted low to
indicate memory access.)
• At the middle of T1 , the ALE is asserted low and
this enables the external address latch to take low
byte of the address and keep on its output lines.
• In the second T-state (T2 ), the memory is requested
for read by asserting read line low. When read is
asserted low, the memory is enabled for placing the
opcode on the data bus. The time allowed for
memory to output the opcode is the time during
which read remains low.
• In the third T-state (T3 ), the read signal is asserted
high. On the rising edge of read signal, the opcode is
latched into microprocessor. Other control signals
remain in the same state until the next machine
cycle.
• The fourth T-state (T4 ) is used by the processor for
internal operations to decode the instruction and
encode into various machine cycles, and also for
completing the task specified by 1-byte instruction.
During this state (T4 ) the address and data bus will
be in high impedance state.
Timing Diagram for Memory read cycle in 8085:
• The memory read machine cycle is executed by
the processor to read a data byte from memory.
• The processor takes 3T states to execute this cycle.
• At the falling edge of T1 , the microprocessor
outputs the low byte address on AD0 - AD7 lines
and high byte address on A8 to A15 lines.
• ALE is asserted high to enable the external
address latch.
• The other control signals are asserted as follows.
IO/M=0, S0 = 0, S1 = 1. (IO/M is asserted low to
indicate memory access.)
• At the middle of T1 , the ALE is asserted low and
this enables the external address latch to take low
byte of address and keep on its output lines.
• In the second T-state (T2 ), the memory is
requested for read by asserting read line low.
When read is asserted low, the memory is
enabled for placing the data on the data bus. The
time allowed for memory to output the data is
the time during which read remains low.
• At the end of T3 , the read signal is asserted high.
On the rising edge of read signal, the data is
latched into microprocessor. Other control signals
remain in the same state until the next machine
cycle.
Timing Diagram for Memory write Cycle in 8085
• The memory write machine cycle is executed by the
processor to write a data byte in a memory location.
• The processor takes 3T states to execute this
machine cycle.
• At the falling edge of T1 , the microprocessor outputs
the low byte address on AD0 - AD7 lines and high
byte address on A8 to A15 lines.
• ALE is asserted high to enable the external address
latch. The other control signals are asserted as
follows. IO/M=0, S0 = 1, S1 = 0. (IO/M is asserted low
to indicate memory access.)
• At the middle of T1 , the ALE is asserted low and this
enables the external address latch for latching the
low byte address into its output lines.
• In the falling edge of T2 , the processor output data
on AD0 to AD7 lines and then request memory for
write operation by asserting the write control signal
WR to low.
• At the end of T3 , the processor asserts WR high. This
enables the memory to latch the data into it. The
memory should prepare itself to accept the data
within the time duration in which write control signal
remains low. Other control signals remain in the
same state until the next machine cycle.
1
 Addition of numbers in an array of three numbers ( Assume 16 bit Result)

Address Hex Code Label Mnemonics Comments

6000 0E MVI C, 03H; Load register C with 03H
6001 01
6002 6 MVI B, 00H; Load register B with 00H
6100 80 H
6003 0
6101 80 H
6004 21 LXI H, 6100 H; Initialise memory pointer to 6100
6102 02 H
6005 0
6006 61
6007 AF XRA A; Clear Accumulator
6008 86 RPT ADD M; Add contents of accumulator with contents in memory
6009 D2 JNC NEXT; Jump to NEXT if carry is not set
600A 0D
600B 60
600C 3 INR B; Increment B for getting the higher byte of result
600D 23 NEXT INX H; Increment M, Memory location pointed by HL pair
600E 0 DCR C; Decrement C for the counter operation.
600F C2 JNZ RPT; Jump to RPT if register [C]= 0
6010 8
6011 60
6012 6F MOV L, A; Move contents of A to L
6013 60 MOV H, B; Move contents of B to H

Program to arrange the numbers in an array. [Ascending / Descending Order ]

Address Hex Code Label Mnemonics Comments

6000 0E MVI C, 04 H; C is initialised as a counter 1 to count the iterations
6001 9

6002 41 LOOP 1 MOV B, C; B is initialised as counter 2 to count the no of comparisons in each iteration
6003 21 LXI H, 6100 H; Memory Pointer initialised
6004 0
6005 61
6006 7E LOOP 2 MOV A, M; First number moved to accumulator.
6007 63 INX H; Memory Pointer incremented
6008 56 MOV D, M; Next number in array is moved to register D
6009 BA CMP D ; Numbers are compared.
600A DA / D2 JC / JNC NEXT; Go to the next comparison if [ A] < [ D] for ascending order
600B 11
600C 60
600D 77 MOV M, A; Otherwise exchange the numbers.
600E 2B DCX H ; Memory pointer Decremented
600F 72 MOV M, D ; Move [D] to memory
6010 63 INX H; Memory pointer incremented
6011 5 NEXT DCR B; Counter 2 decremented and then repeat the process
6012 C2 JNZ LOOP 2; Jump to LOOP 2 if [B] not equal to zero.
6013 6
6014 60
6015 0D DCR C; Decrement counter 1 and repeat the process
6016 C2 JNZ LOOP 1; Jump to LOOP 1 if [C] not equal to zero.
6017 2
6018 60

2
Example for Ascending order sorting:

3
 Program to Convert a Binary number to BCD number
Address Hex Code Label Mnemonics Comments
6000 06 MVI B, 00 H; Clear Register B to store the hundreds
6001 0
6002 48 MOV C, B; Clear Register C to store tens
6003 3A LDA 6200 H; The number to be converted is loaded to A
6004 0
6005 62

6006 FE HUN CPI 64 H; If the number > 100 (64 H), find the number of hundreds in the number
6007 64
6008 DA JC TEN; Jump to TEN if carry is generated Binary BCD Number
6009 11
Eg: 80 H 128 [ 100*1 + 10 *2 + 1* 8 ]
600A 60
600B D6 SUI 64 H ; Division by hundred
600C 64
600D 4 INR B; Increment register B
600E C3 JMP HUN; Jump to HUN
600F 6
6010 60
6011 FE TEN CPI 0A H; If number > 10 (0A H), Find the number of tens in the number
6012 0A
6013 DA JC UNIT; Jump to unit if carry
6014 1C
6015 60
6016 D6 SUI 0A H; Division by ten
6017 0A
6018 0C INR C; Increment the content of register C
6019 C3 JMP TEN; Jump to TEN
601A 11
601B 60
601C 57 UNIT MOV D, A; unit is saved in register D
601D 60 MOV H, B; Hundreds is moved to register H
601E 79 MOV A, C; Tens value stored to A
601F 7 RLC;
6020 7 RLC;
6021 7 RLC;
6022 7 RLC;
6023 82 ADD D; Add the units value to tens value in A
6024 6F MOV L, A; Move the content of accumulator to L

6025 76 HLT; Program Halted , now the result , ie, BCD number in [HL]
 Program to Convert a BCD to Binary number

Address Hex Code Label Mnemonics Comments

6000 21 LXI H, 6200 H; Memory pointer initialised

6001 0

6002 62

6003 7E MOV A, M; Content in memory location pointed is moved to A

6004 47 MOV B, A; Move the number to register B

6005 E6 ANI 0F H; To separate BCD1 and BCD 2, Mask higher nibble.

6006 0F

6007 4F MOV C, A; BCD 1 is saved in register C

6008 78 MOV A, B; Original BCD number is moved to A

6009 E6 ANI F0 H; Mask Lower nibble of BCD number

600A F0

600B 0F RRC;

600C 0F RRC;
Rotate four times to right to get BCD 2
600D 0F RRC;

600E 0F RRC;

600F 57 MOV D, A; Save BCD 2 to register D

6010 AF XRA A; Clear Accumulator

6011 1E MVI E, 0A; BCD2 X 10 as it comes at tenth place.

6012 0A

6013 83 LOOP ADD E; Add [E] to [A]

6014 15 DCR D; Decrement D register

6015 C2 JNZ LOOP; Jump to LOOP if [D] not equal to zero

6016 13

6017 60

6018 81 ADD C; (BCD2 x 10 ) + BCD1

6019 76 HLT; Program Halted , now the result , ie, Binary number in [A]
Timing Diagram of 8085 Instructions (Contd...):
• The execution of an instruction is the execution of the machine cycles of that
instruction in a predefined order.
• Therefore, from the knowledge of the timing diagrams of machine cycles, the
timing diagram of an instruction can be obtained.

Example: STA 526AH , PUSH B etc….

Timing Diagram of MOV Rd, M
• Though its a one byte instruction , it requires two machine cycles for
execution.

• Here in the given timing diagram, we have

considered MOV E, M;
[Suppose the instruction is stored in memory
location 2008 H and E register content is DB H,
H register content is 40H, and L register content
is [Link] us say location 4050H has the data
value AAH. When the 8085 executes this
instruction, the contents of E register will change
to AAH, as shown below.]
Timing Diagram for STA 526A H;
• Let the content of the accumulator
be C7H and it is desired to store the
content of the accumulator to a
memory location 526AH.
• The STA addr16 instruction is a
three byte instruction. The first byte
is the opcode of the instruction 32H.
The second byte is low byte address
6AH and the third byte is high byte
address 52H.
• Let the three bytes of the
instructions be stored in memory
locations 41FFH, 4200H and 4201H.
• Delay routines are the subroutines used for maintaining the timings of various operations
in a microprocessor.
• As an example, In control applications, certain equipment need to be ON/OFF after a
specified time delay. In some applications, a certain operation has to be repeated after a
specified time interval.
• A delay routine is generally written as a subroutine (It need not be a subroutine always. It
can even be a part of the main program.) In a delay routine a count (number) is loaded in
a register of microprocessor. Then it is decremented by one and the zero flag is checked to
verify whether the content of register is zero or not. This process is continued until the
content of the register is zero. When it is zero the time delay is over and the control is
transferred to the main program to carry out the desired operation.
• The delay time is given by the total time taken to execute the delay routine. It can be
computed by multiplying the total number of T states required to execute the subroutine
and the time for one T-state of the processor. The total of number of T states can be
computed from the knowledge of T states required for each instruction.
• The time for one T-state of the processor is given by the inverse of the internal
clock frequency of the processor.
• For example, if the 8085 microprocessor has 5 MHz quartz crystal then,

• For small time delays (< 0.5 millisecond) an 8-bit register can be used as counter,
but for large time delays (< 0.5 second) 16-bit register should be used as
counter. For very large time delays (>0.5 second), a delay routine can be
repeatedly called in the main program. The disadvantage in delay routines is
that the processor time is wasted.
• An alternate solution is to use a dedicated timer like 8253/8254 to produce
time delays or to maintain timings of various operations.
• The process of interrupting the normal program execution to carry out a specific task/work
is referred to as interrupt.
• The interrupt is initiated by a signal generated by an external device ( )
or by a signal generated internal to the processor ( ).
• When a microprocessor receives an interrupt signal, it stops executing the current main
program, saves the status (or content) of various registers (PC in case of 8085) in stack and
then executes a subroutine in order to perform the specific task requested by the interrupt.
The subroutine that is executed in response to an interrupt is also called
. At the end of ISR, the stored status of registers in stack are restored to
respective registers and the processor resumes the normal main program execution from
the point (instruction) where it was interrupted.
• When interrupt occured,
(SP) ← (SP) – 1 ; ((SP)) ← (PC)H
(SP) ← (SP) – 1 ; ((SP)) ← (PC)L
(PC) ← address of ISR
• When is executed in the ISR,
(PC)L ← ((SP)) ; (SP) ← (SP) + 1
(PC)H ← ((SP)) ; (SP) ← (SP) + 1
• The external interrupts are used to implement interrupt driven data transfer scheme. The
interrupts generated by special instructions are called software interrupts and they are
used to implement system services/calls (or monitor services/calls). The system /monitor
services are procedures developed by the system designer for various operations and
stored in memory. Theuser can call these services through software interrupts. The
interrupts generated by exceptional conditions are used to implement error conditions in
the system.

• Interrupts are useful for efficient data transfer between the processor and the peripheral.

Upon receiving an interrupt signal, the processor suspends the current

program execution,saves the status in a stack and executes an ISR to perform the data
transfer between the peripheraland the processor. At the end of ISR the processor status is
restored from stack and the processor resumes its normal program execution. This type of
data transfer scheme is called interrupt drivendata transfer scheme.
• The data transfer between the processor and peripheral devices can be
implemented either by or by . In polling
technique, the processor has to periodically poll or check the status/readiness of
the device and can perform data transfer only when the device is ready.
• In polling technique the processor time is wasted, because the processor has to
suspend its work and check the status of the device in predefined intervals.
Example:

In general interrupts can be classified in the following three ways:

• Interrupts initiated by external hardware by sending an appropriate signal to the interrupt pin of the
processor is called hardware interrupt. The 8085 processor has five interrupt pins
and the interrupts initiated by applying appropriate signal to these pins are called

are program instructions. When a software interrupt instruction is executed, the

processor executes an Interrupt Service Routine(ISR) stored in the vector address of that software
interrupt instruction. The software interrupts of 8085 are
The software interrupts of 8085 are vectored interrupts. Software interrupts cannot be masked or
be disabled.
• When an interrupt signal is accepted by the processor, and the program control automatically branches to
a specific address (called vector address) then the interrupt is called The automatic
branching to a vector address is predefined by the manufacturer of the processor. (In these vector
addresses the interrupt service subroutines(ISR) are stored.) In non-vectored interrupts the interrupting
device should supply the address of the ISR to be executed in response to the interrupt. All the 8085
interrupts excepts INTR are vectored interrupts.
• The interrupts whose request can be either accepted or rejected by the processor are called
The interrupts whose request has to be definitely accepted (i.e., it cannot be rejected) by the
processor are called In 8085 the hardware interrupts RST 7.5, RST 6.5, and RST
5.5 can be masked/unmasked using SIM instruction. All the hardware interrupts except TRAP are disabled
by executing DI instruction and they are enabled by executing EI instruction.
• Interrupts initiated by external hardware by sending an appropriate signal to the interrupt pin of the
processor is called hardware interrupt. The 8085 processor has five interrupt pins

• In 8085 the hardware interrupts RST 7.5, RST 6.5, and RST 5.5 can be masked/unmasked using SIM
instruction.
• All the hardware interrupts except TRAP are disabled by executing DI instruction and they are enabled
by executing EI instruction.
• All the 8085 interrupts except INTR are vectored interrupts, ie the program control automatically
branches to a specific address (called vector address) predefined by the manufacturer.
• If the interrupt is non vectored, then the interrupting device
has to supply the address of ISR when it receives INTA signal.
Then the processor starts executing ISR in this address.
Software Interrupts:
are program instructions. When a software interrupt instruction is
executed, the processor executes an Interrupt Service Routine(ISR) stored in the vector
address of that software interrupt instruction.
• The software interrupts of 8085 are
• The software interrupts of 8085 are vectored interrupts.
• Software interrupts cannot be masked or be disabled.
• When all the interrupts are enabled, the priority sequence of hardware interrupts from
is .
• When the 8085 processor accepts an interrupt, it will disable all the hardware interrupts except
TRAP. Hence in order to allow the higher priority interrupt while executing Interrupt Service
Subroutine (ISR) for lower priority interrupt, enable the interrupt system in the beginning of ISR
of lower priority interrupt, by executing EI instruction.

• All the hardware Interrupts except TRAP in 8085 can be Enabled or Disabled with the help of EI
and DI instructions respectively. Also the the interrupts except TRAP can be disabled by system
(processor) reset or after recognition of another interrupt.
• The only signal which can override TRAP is signal. (i.e., If the processor receives HOLD
and TRAP at the same time then HOLD is recognized first and only then is TRAP recognized.)

• All the hardware Interrupts except TRAP in 8085 can be Masked or Unmasked with the help of
instruction.
• An external device can interrupt the processor by placing a high signal on INTR pin of 8085. If
the processor accepts the interrupt, then it will send an acknowledge signal INTA to the
interrupting device.
• On receiving the acknowledge signal, the interrupting device has to place either an RST n
opcode (or CALL opcode followed by 16-bit address) on the data bus.
• On receiving the RST n opcode, the 8085 processor
generates the vector address of RST n instruction.
• [The INTR interrupt can be expanded to accept 8-interrupt
inputs using 8-to-3 priority encoder.]
• This opcode is read by the processor and then it generates the vector address of the RST
instruction internally.
Micro Processor Based System:
The microprocessor-based system to perform a specific task
consists of microprocessor as CPU, semiconductor memories
like EPROM and RAM, input device, output device and
interfacing devices. The memories, input device, output
device and interfacing devices are called .
The EPROM memory is used to store permanent programs and
data. The RAM memory is used to store temporary programs
and data. The input device is used to enter the program, data
and to operate the system. The output device is also used for
examining the results.

The microprocessor is the master, which controls all the activities

o f t h e sy ste m . To p e r fo r m a s p e c i f i c j o b o r t a s k , t h e
microprocessor has to execute a program stored in memory. The
program consists of a set of instructions stored in consecutive
memory location. In order to execute the program, the
microprocessor issues address and control signals, to fetch the
instruction and data from memory one by one. After fetching
each instruction it decodes the instruction and carries out the
task specified by the instruction.
• The basic data size of 8085 is 8-bit. Therefore, the memory word size of the memories interfaced with
8085 processor is also 8-bit or byte.
• The 8085 uses a 16-bit address to access memory and hence it can address upto 216 = 65,53610 = 64 k
memory locations.
• A memory unit is an integral part of any microcomputer system and its primary purpose is to store
programs and data. In a broad sense, a microcomputer memory system can be logicallydivided into
three groups. They are as follows:
� Processor memory
� Primary or main memory
� Secondary memory
• Processor memory refers to registers inside the microprocessor. These registers are used to hold data
and results temporarily when computation is in progress. Since the registers of the processor are
fabricated using the same technology as that of a microprocessor, there is no speed disparity between
these registers and a microprocessor. However, the cost involved in this approach forces a manufacturer
to include only a few registers in the microprocessor.
• The READY is an input signal that can be used by slow peripherals to get extra time in order to
communicate with 8085. The 8085 will work only when READY is tied to logic high. WheneverREADY is
tied to logic low, the 8085 will enter a wait state.
A typical semiconductor memory IC will have n address pins, m
data pins (or output pins) and a minimum of two power supply pins
(one for connecting required supply voltage (VCC) and the other for
connecting ground). The

The control signals needed for read

operation in EPROM are chip select (chip enable) and read control
(output enable).
• Using logical gates
• Using Decoder IC's
2 to 4 decoder [74LS139] and 3 to 8 decoder [74LS138] are generally used.

Example for using logical gates:

Pin diagram and truth table for 3 to 8 decoder IC.
• The IO devices connected to a microcomputer system provides an efficient means of communication between the microcomputer
system and the outside world.
• These IO devices are commonly called peripherals and include keyboards, displays, printers and disks (hard disk and Compact Disc
etc.)
• The IO devices are generally slow devices. So, they are connected to the system bus through ports. The ports are buffer IC which is
used to temporarily hold the data transmitted from the microprocessor to IO device or to hold the data transmitted from IO device to
the microprocessor.

� The input device will load the data to the port.

� When the port receives the data, it sends message to the processor to read the data.
� The processor will read the data from the port.
� After the data has been read by the processor the input device will load the next data into the port.

� The processor will load the data to the port.

� The port will send a message to the output device to read the data.
� The output device will read the data from the port.
� After the data has been read by the output device the processor can load the next data to the port.
The various INTEL IO port devices are 8212, 8155 /8156, 8255, 8355 and 8755.
• The INTEL 8255 is a device used to implement Table:
parallel data transfer between processor and slow
peripheral devices like ADC, DAC, keyboard, 7-
segment display, LCD, etc.
• It has 3 numbers of 8-bit parallel IO ports (ports A,
B and C).
• Port-A can be programmed in mode-0, mode-1 or
mode-2 as input or output port.
• Port-B can be programmed in mode-1 and mode-2
as IO port.
• When ports A and B are in mode-0, port-C can be
used as IO port. The individual pins of port-C can
be set or reset.
• INTEL 8255 requires four internal addresses and
has one logic low Chip Select (CS) pin. The address
of internal devices of 8255 are listed in Table.
• The 8255 has two control words: IO Mode
S e t c o n t r o l Wo r d ( M S W ) a n d B i t
Set/Reset (BSR) control word.
• The MSW is used to specify IO functions
a n d B S R wo rd i s u s e d to s e t / re s e t
individual pins of port-C. Both the control
words are written in the same control
register. The control register differentiates
them by the value of bit B7
• The BSR control word does not affect the
functions of ports A and B.
• Bit B7 of the control register specifies
either the IO function or the bit set/reset
function. If B7 = 1, then the bits B6 -
B0determine IO functions in various
modes. If bit B7 = 0, then the bits B6 -B0
determine the pin of port-C to be set or
reset.
 IO Modes of 8255
• The 8255 has three ports: Port-A, Port-B and Port-C. The
ports A and B are 8-bit parallel ports. Port-A can be In this mode, all the three ports can be
programmed to work in any one of the three operating programmed either as input or output port. In mode-0,
modes as input or output port. The three operating modes the outputs are latched and the inputs are not latched.
are : The ports do not have handshake or interrupt
capability. The ports in mode-0 can be used to
interface DIP switches, Hexa-keypad, LEDs and 7-
segment LEDs to the processor.
• Port-B can be programmed to work either in mode-0 or In this mode, only ports A and B can be
mode-1 as input or output port. programmed either as input or output port. In mode-1,
• Port-C pins (8 pins) have different assignments depending handshake signals are exchanged between the
on the mode of ports A and B. If ports A and B are processor and the peripherals prior to data transfer.
programmed in mode-0, then port-C can perform any one of The port-C pins are used for handshake signals. Input
the following function : and output data are latched. Interrupt driven data
• 1. As 8-bit parallel port in mode-0 for input or output. transfer scheme is possible.
• 2. As two numbers of 4-bit parallel port in mode-0 for input or
output. • Mode-2 : In this mode the port will be a bidirectional
• 3. The individual pins of port-C can be set or reset for various port (i.e., the processor can perform both read and
control applications. write operations with an IO device connected to a port
• If port-A is programmed in mode-1/mode-2 and port-2 is in mode-2).Only port-A can be programmed to work in
programmed in mode-1 then some of the pins of port-C are mode-2. Five pins of port-C are used for handshake
used for handshake signals and the remaining pins can be signals. This mode is used primarily in applications
used as input/ output lines or individually set/reset for such as data transfer between two computers or
control applications. floppy disk controller interface.
Port C pin assignments:
• The address line A0 of 8085 is connected to
A0 of 8255 and A1 of 8085 is connected to A1
of 8255 to provide the internal addresses. The
IO addresses allotted to the internal devices of
8255 are listed in Table. The data lines D0 -D7
are connected to D0 -D7 of the processor to
achieve paralleldata transfer. IO/ M is made
high and connected to active high pin of
decoder to ensure IO mapping else IO/ M is
active low for Memory mapping.
• The port and peripheral devices will have one logic low/high chip select pin. The processor can
access the port/peripheral device by supplying internal address and chip select signals. Therefore,
the port and peripheral device interfacing (IO interfacing) deals with allocation of various internal
addresses and generation of chip select signals.
• There are two ways of interfacing IO devices in 8085-based system.
�

In memory mapping of IO devices the ports are allotted a 16-bit address like that of the memory
location. Some of the chip select signals generated to select memory ICs are used for selecting the
IO port devices. Hence, the processor treats the IO ports as memory locations for reading and
writing (i.e., the devices which are mapped by memory mapping are accessed by executing memory
read cycle or memory write cycle).
In standard IO mapping or isolated IO mapping, a separate 8-bit address is allotted for the IO ports
and the peripheral ICs. The processor differentiates the IO-mapped devices, from the memory-
mapped devices in the following ways:
• A 8085 processor does not provide separate read (RD)
and write (WR) signals for memory and IO devices. But
it differentiates the memory and IO device accessed by
IO/M signal. The three signals RD, WR and IO/M can be
decoded as shown in Fig. to provide separate read and
write control signals for IO devices and memory devices.
• When the devices are IO-mapped, then only IN and
OUT instructions have to be used for data transfer
between the device and the processor. For the IO-
mapped devices a separate decoder should be used to
generate the required chip select signals.
• The address line A0 of 8085 is connected to
A0 of 8255 and A1 of 8085 is connected to A1
of 8255 to provide the internal addresses. The
IO addresses allotted to the internal devices of
8255 are listed in Table. The data lines D0 -D7
are connected to D0 -D7 of the processor to
achieve paralleldata transfer. IO/ M is made
high and connected to active high pin of
decoder to ensure IO mapping else IO/ M is
active low for Memory mapping.
• At the falling edge of T1, the microprocessor output the
8- bit port address on both the low order address lines
(AD0 -AD7) and high order address lines (A8 to A15). ALE
is asserted high to enable the external address latch. The
other control signals are asserted as follows. IO/M=1, S0
= 0 and S1 = 1. (IO/M is asserted high to indicate IO
access.)
• At the middle of T1, the ALE is asserted low and this
enables the external address latch to take the port
address and keep on its output lines.
• In the second T-state (T2) the IO device is requested for
read by asserting read line low. When read is asserted
low, the IO port is enabled for placing the data on the
data bus. The time allowed for IO port to output the data
is the time during which read remains low.
• At the end of T3, the read signal is asserted high. On the
rising edge of read signal the data is latched into
microprocessor. Other control signals remains in the
same state until the next machine cycle.
• IN instruction is used.
• At the falling edge of T1, the microprocessor outputs the
8-bit port address on low order address line(AD0 - AD7)
and high order address lines (A8 to A15).
• ALE is asserted high to enable the external address latch.
The other control signals are asserted as follows : IO/M=1,
S0 = 1 and S1 = 0. (IO/M is asserted high to indicate IO
access.)2.
• At the middle of T1, the ALE is asserted low and this
enables the external address latch for latching the port
address into its output lines.
• In the falling edge of T2, the processor output data on
AD0 - AD7 lines and then request IO port for write
operation by asserting the write control signal WR to low.
• At the end of T3 , the processor asserts WR high.
Thisenables the IO port to latch the data into it. The IO
port should prepare itself to accept the data within the
time duration in which write control signal remains low.
Other control signals remains in the same state until the
next machine cycle.
• OUT instruction is used.
• In many applications, an analog device has to be interfaced to digital system. But, the
digital devices cannot accept the analog signals directly. So, the analog signals are
converted to equivalent digital signal (data) using Analog-to-Digital Converter (ADC).
• TheA/D conversion is the process by which the analog signal is represented by an
equivalent binary data
• If the digital data is represented by n-bit binary then it can have 2n different values.
• In A/D conversion the given analog signal has to be divided into steps of 2n values, and
each step is represented by one of the 2n values.
• The resolution of the converter is the minimum analog value that can be represented by
the digital data. If the ADC gives n-bit digital output and the full scale analog input is X
volts, then the resolution is X / 2n volts.
• The conversion time is defined as the total time required to convert an analog signal into
its digital equivalent.
The ADC0809/0808 is an 8-bit ADC with an inbuilt 8-channel multiplexer.
The ADC0809/0808 is available as a 28-pin IC in DIP (Dual In-line Package).
The analog to digital converter is treated as an input device by the microprocessor.
Input Channel selection based on
ABC signals.
• During the analog to digital conversion process, Initially, microprocessor sends
an initializing signal (start of conversion-SOC) to the ADC to start the analog to
digital data conversion process. The start of conversion signal is a pulse of a
specific duration.
• The microprocessor has to wait for the digital data till the conversion is over.
After the conversion is over, the ADC sends end of conversion EOC signal to
inform the microprocessor that the conversion is over and the result is ready at
the output buffer of the ADC.
• These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC
and reading the digital output of the ADC are carried out by the CPU using 8255
I/O ports.
Example: Interfacing ADC 0808 with 8085 using 8255 ports. Use port A of 8255 for transferring
digital data output of ADC to the CPU and port C for control signals. Assume that an analog input is
present at I/P2 of the ADC and a clock input of suitable frequency is available for ADC.
Solution: The analog input I/P2 is used and therefore address pins A,B,C should
be 0,1,0 respectively to select I/P2.
The OE and ALE pins are already kept at +5V to select the ADC and enable the
outputs.
Port C upper acts as the input port to receive the EOC signal while port C lower
acts as the output port to send SOC to ADC .
Port A acts as a 8-bit input data port to receive the digital data output from the
ADC.
• The 8255 control word is written as follows:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 0
• In many applications, the microprocessor has to produce analog signals for controlling certain analog devices.
Basically the microprocessor system can produce only digital signals. In order to convert the digital signal to
analog signal a Digital-to-Analog Converter (DAC) has to be employed.
• The DAC will accept a digital (binary) input and convert to analog voltage or current.
• Every DAC will have "n" input lines and an analog output.
• The DAC requires a reference analog voltage (Vref) or current (Iref) source. The smallest possible analog value
that can be represented by the n-bit binary code is called resolution. The resolution of DAC with n-bit binary
input is 1/2n of reference analog value. Every analog output will be a multiple of the resolution.
• For example, consider an 8-bit DAC with reference analog voltage of 5 volts.
Now the resolution of the DAC is (1/28 ) × 5 volts. The 8-bit digital input can
take, 28 = 256 different values.
• The analog values for all possible digital input are as shown in Table
An is a system that has a software embedded in to a computer
hardware for doing a dedicated task. It may be an independent system or a part
of large system.
Eg: Mobile phones, TV remotes, Printers etc.

CPU of the embedded system can be Micro processor, Micro Controller or DSP or any
Application Specific Processor (ASP).
Vs
A Microprocessor does not contain RAM, ROM, I/O A Micro Controller contains the circuitary of Micro
ports, Timer/ Counters,Serial Communication ports Processor and in addition to that it has built in ROM,
internal to it. So for a system these are to be to RAM, I/O ports,Timer/ Counters,Serial Communication
interfaced externally. ports etc.
Bulkier System Less Size
More time to design PCB as more Hardware Les Time to design.
Expensive Less Expensive
More versatile as the designer can choose the amount Less versatile
of memory and required peripherals.
Access time for Memory and IO devices are high Less access time.
Less No. of pins are Multifuctional More pins are Multi functional
More Instructions required to move data between Less Instructions required to move data between
memory and CPU memory and CPU
Less No. of bit handling instructions More No. of bit handling instructions
8085, 8086, Pentium series etc 8051,8052, PIC, ARM etc..
Desktop, Laptop etc Mobile phones,Printers, TV remotes etc..
• 8 bit Micro controller
• 40 pin DIP
• 128 bytes of internal RAM
• 4K bytes of onchip ROM
• Two 16 bit Timers / Counters
• One Full duplex Serial port
• Four 8 bit I/O ports.
• 6 interrupt sources
• Harvard Architecture
Register Organisation in 8051:
• In 8051 , there is only one data type which is 8 bits.
• Since there is a large number of registers in 8051, they can be classified as General purpose
registers and Special function registers.
• Most widely used registers of 8051 are, A [accumulator], B, R0 to R7 of each bank of
registers. There are 4 such Banks of registers.
• These 32 registers (8 X 4 = 32) R0 to R7 of each bank, is known as General purpose registers .
• All of these general purpose registers are of 8 bit size.
• Registers A and B are used to hold results of mathematical and logical operations by CPU.
• Register B is used along with A for multiplication and division operations and has no other
function other than as a location where data is stored.
• In addition to hold the operands and results, Register A is used for all data transfers
between the 8051 and the external memory.
• Except Program Counter [PC] and DPTR register, all are 8 bit registers. PC and DPTR are 16
bit registers.
RAM memory space allocation in 8051:
• 128 bytes of RAM in 8051. ie, addresses drom 00 H
to 7F H.
• The total RAM space is divided in to three.
1. A total of 32 bytes from locations 00 H to 1F H
are set aside for Register banks and Stack.
• [0001 1111 = 1F H = 31 d is equivalent to 31 + 1 = 32
since we start from 00 H.]
• These 32 registers are organised as Four register
banks of eight registers each. R0 to R7 in each bank.
• The four register banks are numbered from 0 to 3.
• Each register can be addressed by its name (R0 to
R7), if the bank is selected, else by its RAM address.
• If the bank 3 is selected then R0 will point to R0 of
bank 3, else address 18 H will point to the same
location.
• Bank selection can be done using the bits RS0 and RS1 [PSW.4] RS0 [PSW.3]
RS1 in the program status word register. [PSW]
Bank 0 0 0
• upon Reset Bank 0 is selected.
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1
Register bank selection using PSW bits
2. A total of 16 bytes from location 20 H to 2F H are set aside for Bit addressable Read/
Write memory.
• If only one bit is needed, we can use the bit address ie, 00 H to 7F H along with instructions for
bit operation.
• If one byte is needed then address 20 H to 2F H along with instructions for byte operation.
3. A total of 80 bytes from locations 30 H to 7F H are used for read / write
storage operations known as scratch pad RAM.

Stack is a section of RAM used by the CPU to store information temporarily. the
information could be data or address.
• The register used to point towards the stack is called Stack pointer which is of 8 bit in 8051.
The address held in the SP is the location in internal RAM where the last byte of data was
stored by the stack operation.
• When the 8051 is powered up, the SP points to the location 07 H, (which can be changed with in
the program.) This means that the RAM location 08 H is the first location being used as stack of
8051 by default. ie, in Bank 1.
• Generally locations 08 H to 1F H can used as stack. If a given program needs more stack, we
can change the SP to RAM locations 30 H to 7F H using the program instructions. Can't use
locations 20 H to 2F H, as it is reserved for bit addressable memory.
• When we PUSH data in to the stack, the SP is incremented by one before
storing the data in to the stack, so that stack grows up as data is stored.
• With every POP or retrieval, top byte of stack [LIFO] is copied to the
register specified in the instruction and the the SP is decremented by one.
• The CPU can also use the use the stack to save the address of the instruction that comes just
after the CALL instruction so that the CPU can know where to resume after the execution of
the called sub routine.

• When 8051 is powered up, SP = 07 H. There fore the first location of stack is RAM location
08 H which belongs R0 of register bank 1. ie, Register bank 1 and Stack is using the same
memory space. So if in a program we need to use register bank 1 and 2 , it is needed to
relocate stack to another section of RAM.
ROM in 8051:
• 8051 has 4K bytes of internal ROM.
• Internal ROM of 8051 starts at 0000H and goes
upto 0FFF H which corresponds to 4K.
• Externally if needed it can interface upto 64K bytes
of memory externally. But the total of internal and
external ROM should be equal to 64K bytes. ie, if
we are using internal ROM and external ROM then,
internal from 0000 H to 0FFF H and external from
1000 H to FFFF H.
• If only external ROM is used for total 64K bytes,
then EA pin should be kept low for that. if EA pin is
high then first internal ROM then remaining can be
external ROM.
Program Status Word in 8051 [PSW]:
8051 Data Types and Directives:
• Data Type in 8051 is of 8 bits.
Assembler Directives:
Addressing Modes in 8051:

The various ways of accessing data by the CPU is known as Addressing

modes.
The five different addressing modes in 8051 are,
1. Immediate
2. Direct
3. Register
4. Register indirect
5. Indexed
ROM in 8051:
• 8051 has 4K bytes of internal ROM.
• Internal ROM of 8051 starts at 0000H and goes
upto 0FFF H which corresponds to 4K.
• Externally if needed it can interface upto 64K bytes
of memory externally. But the total of internal and
external ROM should be equal to 64K bytes. ie, if
we are using internal ROM and external ROM then,
internal from 0000 H to 0FFF H and external from
1000 H to FFFF H.
• If only external ROM is used for total 64K bytes,
then EA pin should be kept low for that. if EA pin is
high then first internal ROM then remaining can be
external ROM.
Program Status Word in 8051 [PSW]:
8051 Data Types and Directives:
• Data Type in 8051 is of 8 bits.
Assembler Directives:
Addressing Modes in 8051:

The various ways of accessing data by the CPU is known as Addressing

modes.
The five different addressing modes in 8051 are,
1. Immediate
2. Direct
3. Register
4. Register indirect
5. Indexed
The various ways of accessing data by the CPU is known as Addressing
modes.
The five different addressing modes in 8051 are,
1. Immediate
2. Direct
3. Register
4. Register indirect
5. Indexed
• 8051 has four 8 bit bidirectional ports, ie, 32 I/O pins.
• Port 0, Port 1, Port 2, Port 3
• All ports upon reset is configured as output port.

• Designated as AD0 to AD7

• Port address (SFR) is 080 H.
• Port 0 can be used for Address/ Data when connected to an external memory.
• For memory addressing, the lower byte of 16 bit address is in P0.
• When used as an output port, Port 0 needs as external Pull up resistor to sourcea high
value to the output circuit.
• When used as an output Port, whatever value comes in the port 0 SFR latch will be given
as the output.
• When external memory is accesed Port 0 (input) does not need a Pull up resistor.
• To work Port 0 as output port, Write the latch
(SFR) of port 0 with zero, so that what wver
comes at the latch can be given as output since
the lower N channel FET is in on state. ( refer
second fig.) By default, ie, without external puul
up resistor ,it can't source high output value.
• To make Port 0 as an input port , write a '1' to the
port 0 SFR, which will turn off the lower N
channel FET . This will make pin in the high
impedance or floating state.(refer first fig.) So
that whatever value sourced by the external
circuit can be read by activating 'Read Pin'.
• Ports 1 ,2 and 3 have internal pull ups.
• Bit addressing of Port 0 is possible.
• Port 0 is known is True bidirectional port as it
floats or at high impefance state when configured
as input port.
Fig. Internal structure of each Port 0 pin with and without
external Pull up resistor.
• 8 bit Bidirectional Port which is used only for I/O operations.
• Does not need external pull up resistor as it have internal pull
ups.
• Bit addressable.
• Writing '1' to SFR latch turns off the lower N cahnnel FET and
makes the pin suitable for input operations.
• To make it as an output port , whatever comes in latch can be
given as output.
• Now what happens when we write a '0' to the port pin by
mistake which is actually configured and wired as an input?
• To solve the above problem connecta current limiting resistor
to the external Vcc.
• When configured as input port, Port1, 2 and 3 will pull the
status of the pin to high due to its internal pullup resistors so
that it will source currents when externally pulled low. Due
to this property Port 1, 2 and 3 are known as Quasi
Bidirectional.
• CPL P1.2 is a instruction which read the Port latch,
compliments it and then written back to latch .
• 8 bit Bidirectional I/O port
• Time multiplexed between Higher order
address and data.
• Similar port structure to Port 1.
• Bit addressable
• No need of external pull ups.

• 8 bit bidirectional I/O port.

• Bit addressable
• Alternate functions in addition to normal I/O
operations.
• No need for external pull ups.
Machine Cycle in 8051:
• The Smallest interval of time to ccomplish any simple instruction, or part
of a complex instruction is called Machine cycle.
• A Machine Cycle is made up of 6 states. One machine cycle is 12 clock
cycles.
•A is the basic time interval for discrete operations of the Micro
controller such as Fetching, Decoding and Executing an opcode or
writing a data byte.
• Two oscillator pulses , two cycles, define a state.
• Program instructions may require one, two or four machine cycles to get
executed depending on the type of the instruction.
As in the figure there are two ALE pulses per Machine cycle. The ALE pulse is used as atiming pulse
for external memory access, indicates when every instruction byte is fetched. thus two bytes of a
single instruction can be fetched in one machine cycle. But single byte instructions are not executed
in half cycle. ie, the second ALE pulse is discarded for single byte instruction.
Timers and Counters in 8051:
• Two 16 bit up counters named Timer 0 and Timer 1 are in 8051.
• Each can be programmed to count internal clock pulses for generating time
delay as a Timer and external events as a Counter.
• Each Timer is divided in to two 8 bit registers called TL0 and TH0 for Timer 0 and
TL1 and TH1 for Timer 1.
• All Timer / Counter actions are controlled by the bit states in the Timer Mode
Control Register TMOD and Timer / Counter Control Register TCON along with
certain Program instructions. Four modes of operation are there.
• Timer increases by one in every Machine [Link], in every 12 clock cycles.
• Therefore the frequency of the Timer is always of oscillator frequency.
• As an example, for a crystal frequency of 12 Mhz, Timer frequency is
TMOD Register
• TMOD is not Bit addressable.
TCON Register:
Timer / Counter Control Logic using GATE bit:
Timer Mode 1 operation:
Steps to program Timer in Mode 1:
To find the Values to be loaded in to Timer in mode 1:
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Timer Mode 2 Programming in 8051:

8 bit Timer, with auto reload feature. Used for Baud rate setting in serial communication.

• T0 and T1 pins , ie, P3.4 and P3.5 respectively are used to connect the
external events.
• In comparison to Timer operation, here the clock source is from external
events. Otherwise similar to timer only.
• 1/24th of the crystal frequency is the maximum count rate that can be
achieved without loosing accuracy as it needs two machine cycle to sense
the changes by the micro controller.
• The change in external input ie, in pins T0 and T1 should hold for atleast
one machine cycle.

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Basics of Data communication:

• 8051 is a parallel device that transfers eight bits of data simultaneously over eight data lines
to parallel I/O devices such as Printers, DAC etc.
• Parallel data transfer over long distance is very expensive, hence Serial data communication
is widely used for long distance communication.
• In serial data communication, one bit of information , ata time is transferred over a single
line.
• The data byte is always transmitted with the least significant bit first.
• Serial communication in 8051 is Full Duplex in nature, ie, data is transmitted in both ways at
the same time.

Types of Serial Data communication: Serial Port in 8051:

Synchronous Serial Data Communication: • Full Duplex Serial communication using TxD (P3.1) and RxD (P3.0) pins.
• In which Transmitter and Receiver are synchronised with the common • RS232 I/O interfacing standard is used. Where '1' is represented using -3 V to -
clock signal. 25 V and '0' is represented by 3 V to 25 V. MAX 232 drivers are used to
Asynchronous Serial data Communication: interface it with TTL compatable devices.
• In which different clock sources are used for transmitter and receiver. • 8051 uses SBUF register to hold data during Serial communication.
• Data is transmitted using Start and Stop bits. • SBUF is physically two registers. One is write only used to hold data to be
transmitted out and the other is Read only used to hold the received data .
• Transmision begins with start bit, then data and end with the stop bit. Both mutually exclusive registers can be accessed using same address 99 H,
differentiated with the help of instruction, for transmit or receive.
• Four modes of Serial communication in 8051, selected with the SMx bits in
SCON register. [ Serial Port Control ]
• PCON is another special function register used to control data rates.

SCON Register:

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Baud Rate :
• For Synchronous data communication, Baud rate is Bits/ Second.
• For Asynchronous Data communiaction, Baud rate is the reciprocal of the time to send one
bit, because the data is preceded by a start and followed by a stop bit. it need not be equal
to the bits/ second always.
• For error free communication, the baud rate , no. of data bits, No. of start and stop bits ,
presence or absence of parity bit etc should be same for Transmitter and Receiver.

PCON Register:
• By default SMOD bit is Zero. Using program we can make it as '1' to
double the baud rate.

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Steps to Program 8051 to transmit serial data:

Importance of TI Flag:

Steps to Program 8051 to Receive data Serially:

Importance of RI Flag:

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LCD Interfacing to 8051:

Programming LCD using Time delay:

LCD programming using Busy flag: Timing diagram for Read / Write operations:

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ADC Interfacing with 8051:

The resolution of the converter is the minimum
analog value that can be represented by the
digital data.
If the ADC gives n-bit digital output and the full
scale analog input is X volts, then the resolution is
1/2n × X volts.

Timing diagram for ADC:

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• Used to convert digital signals to analog signals.

• Conversion is done with R/2R ladder network logic.

• The number of output levels that an n bit input DAC can produce is 2 n
• The DAC requires a reference analog voltage (Vref) or current (Iref) source. The
smallest possible analog value that can be represented by the n-bit binary code
is called resolution. The resolution of DAC with n-bit binary input is 1 /2n of
reference analog value. Every analog output will be a multiple of the resolution.

DAC Interfacing:

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Stepper Motor Interfacing with 8051:

• Stepper motor translates electrical pulses to mechanical movement, used for
position control.
• Examples are in Robotics, Dot matrix printers, Disc drives etc.
• Stepper motors generally have a permanent magnet rotor (shaft) and stator
surrounding it. There are variable reluctance type stepper motors also.
• The rotor of stepper motor runs in precise steps.
• Step angle is the minimum degree of rotation associated with a single step.
• Steps per revolution is the total number of steps needed to rotate one
complete revolution or 360 degrees. ie, if there are 180 steps per revolution
means each step is of 2 degrees.
• Unipolar, Bipolar and Universal configurations, 6 terminals, 4 terminals and 8
terminals respectively.

when coil A is energised

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8051 Programming in 'C' :

Data Types in 8051 C Programming:

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An is a system that has a software embedded in to a computer

hardware for doing a dedicated task. It may be an independent system or a part
of large system.
Eg: Mobile phones, TV remotes, Printers etc.

CPU of the embedded system can be Micro processor, Micro Controller or DSP or any
Application Specific Processor (ASP).

Application Domain of Embedded Systems: Features and characteristics of Embedded systems:

• In every element of modern day life, we could find an application of • It should perform one or a small number of dedicated functions efficiently.
Embedded systems. Following are a few among them,
• Consumer electronics: Mobile phones, Digital cameras, Printers, Washing machines,
• Low power consumption as most devices are battery powered.
Remote controls, Toys etc. • It should have limited number of memory and peripherals.
• Home security systems: Intruder and Fire alarm system etc • Application is not supposed to get altered by the user.
• Automobile: Anti lock Braking (ABS), Engine control unit, Electronic fuel injection,Door
and wiper controls etc. • Many of them are not directly accessible as it may be a part fo the large
• Medical equipments: Scanners, ECG and EEG, Testing and monitoring equipments. system.
• Banking: ATM, Currency counting machine etc. • It should be highly reliable.
• Networking: Routers, Switches etc.
• Many of the need to operate with time contraints (Speed of response).
• Factories: Control, Instrumentation and Alarm systems.
• Physical size is a constraint for many systems.
The list is incomplete and we could new domains for embedded system applications every where. • Code size is another constraint for many systems.

Current Trends:
• Multi-core processors:
It has become very clear that trying to improve processor performance by increasing clock frequencies
is fraught with difficulties, because the direct result of higher clock frequency is high power dissipation. Thus,
the option of using more than one processor core (at lower clock frequencies) is being tried out. Thus, the
current smart phones and gaming consoles use multi-core processors.
• Embedded and real-time operating systems:
With the emergence of complex applications, many new embedded and real-time operating systems
have become popular. Linux has emerged as a popular embedded OS, and others like Android and newer
versions of Symbion have came up for mobile applications and handheld devices.
• Newer areas of deployment of embedded devices:
Embedded devices have applications in the entertainment, healthcare and automotive segments.
Besides that, there are applications in the communication and military fields as well. Research and development
in these fields is going ahead.

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Real time Task:

• It is a task in which the performance is judged on the basis of time.
• It means that the result of computation is 'correct' only it has produced
the correct output within the specified time constraint , failure to that is
considered as a system failure or as a reduced 'quality of service'.
• Process control systems in Industries, Weapon guidance system, Air traffic
control, Anti lock braking systems etc are few examples for Real time
systems.
• All embedded systems are not Real time systems, eg. Printer, Mobile
phones etc.

Types of Real time tasks: Real time operating systems [RTOS]:

• Hard Real time systems: Characteristics:
In Hard real time systems the failure to meet the time deadline is a fatal • Time constraints
fault. Eg. Air traffic control, ABS etc. • Correctness [ logical and Time]
• Soft real time systems: • Task scheduling
Breaking the time deadline is unwanted, but not immediately critical. • Safety and Reliability
Eg. Navigation systems • Task Criticality - Cost of failure of task.
• Firm Real time systems: • Custom hardware
If the deadline is missed occassionally, the system won't fail. The results • Responsive and reactive
produced after the deadline is discarded. • Stable
Gaming console etc can be an example. • Exception handling
Eg. RT Linux, Vx Works, Windows NT, Solaris etc....

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Embedded Product Development Cycle [ EDLC]:

• It is an Analysis - Design - Implementation based problem solving approach for
Embedded product development.
• First what product is to be developed, next to find the good the design
to build it and finally to Implement or develop it.
• EDLC is essential for understanding the scope and complexity of the work
involved in any embedded product development.
Objectives of EDLC:
• Ensure that high quality products are delivered to end user.
• Risk minimisation and defect prevention in product development by project
management.
• Maximise the productivity.

Different phases of EDLC: EDLC Models:

Water fall or Linear Model:
• The life cycle of product development
is commonly reffered to as models. • In this model or approach each phase of EDLC is executed in sequence.
• The classic embedded life cycle • In linear model each phases are well documented, which gives a clear insight
management contains the phases, to what to be done and how it is to be done in the next phase.
Need - Conceptualisation - Analysis - • One significant feature in linear model is, even if a fault is identified in a phase,
Design - Development and Testing - the corrective measures is not done immediately as there is no feedback
Deployment - Support - upgrades - given in the model.
Retirement/disposal.
• Good documentation, easy project management, Good control over cost and
schedule.
• Well suited for the product development where the requirements are well
defined and within the scope, no changes are expected till the end of the
cycle.

Water fall or Linear model

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Iterative/ Incremental or Fountain Model of EDLC:
• It can be viewed as a cascaded model of linear models, where the cycles are repeated till
the requirements are met completely.

• The major advantage is that it provides a very good deployment cycle feedback after each
function or feature implementation and hence the data can be used as reference for
development of similar products in future.

• Since each cycle acts as a maintenance phase of the previous cycle, changes in functions
or features can be easily incorporated and hence more responsive to changing user needs.

• Risk is spread across each cycle with limited features and can be minimised easily.

• Project management and testing is much simpler to linear model.

• The project can be stopped at any point with bare minimum work.

• The main drawbacks are extensive review required after each cycle, Impact on operations
due to new releases, Training requirement after each new deployment, structured and
well documented interface definition across cycles to accomodate changes etc...

Tool Chain System:

• A toolchain is the set of tools that compiles source code into
executables that can run on your target device, and includes a
compiler, a linker, and run-time libraries.
 Debuggers:
• A debugger or debugging tool is a computer program used to test and
debug other programs (the "target" program). The main use of a
debugger is to run the target program under controlled conditions that
permit the programmer to track its operations in progress and monitor
changes in computer resources (most often memory areas used by the
target program or the computer's operating system) that may indicate
malfunctioning code.

Loaders:
In computer systems a loader is the part of an operating system that is responsible for loading programs and
libraries. It is one of the essential stages in the process of starting a program, as it places programs into memory • Typical debugging facilities include the ability to run or halt the target
and prepares them for execution. program at specific points, display the contents of memory, CPU registers
Loading a program involves reading the contents of the executable file containing the program instructions into
memory, and then carrying out other required preparatory tasks to prepare the executable for running. Once or storage devices (such as disk drives), and modify memory or register
loading is complete, the operating system starts the program by passing control to the loaded program code. contents in order to enter selected test data that might be a cause of
faulty program execution.

Profilers:
• Profiling is the process of measuring an application or system by running
an analysis tool called a profiler. Profiling tools can focus on many
aspects: functions call times and count, memory usage, cpu load, and
resource usage. Used to optimise the system.

Test Coverage:

Test coverage is defined as a technique which determines whether

our test cases are actually covering the application code and how much
code is exercised when we run those test cases. If there are 10
requirements and 100 tests created and if 90 tests are executed then test
coverage is 90%.

Junit is an open source test coverage tool for unit/module testing for java.

PyUnit – PyUnit (also called as Python Unit/Module Testing Framework) is

a widely used testing framework primarily used for unit testing.