Microprocessors (8085/8086): 8085 (8-bit NMOS, 5 hardware interrupts) vs.

8086 (16-bit,
multiplexed address/data lines).

[Link] Question Summary Correct Answer Explanation / Concept

(Year)

51 A stack-organized A) Zero addressing Instructions (like ADD) pop

(2022) computer uses: operands off the stack
implicitly without needing
memory addresses.

52 Affects processing D) 1, 2 and 3 Data bus width, addressing

(2022) power: schemes, and clock speed all
dictate how fast data moves
and is processed.

53 False statement about B) PC holds the The Program Counter (PC)

(2022) CPU registers: address of the holds the address of the next
instruction in instruction to be fetched.
execution

93 Correct statement for D) NAND/NOR are Order of inputs doesn't matter

(2022) logic gates: Commutative but not (A*B = B*A), but grouping
Associative does matter for NAND/NOR.

94 Karnaugh map is used B) minimize the A graphical tool used for

(2022) to: number of gates in Boolean algebra
digital circuits simplification.
95 Code where B) Gray code Prevents multiple bit
(2022) successive values transition errors in
differ by 1 bit: mechanical and optical
encoders.

96 XOR is a: C) Derived gate XOR is made from

(2022) combinations of basic gates
(AND, OR, NOT).

97 Fan-in and Fan-out B) Logic families Define how many inputs a

(2022) are characteristics of: gate can handle and how
many outputs it can drive.

98 IC fabrication broad D) Bipolar and MOS ICs are fundamentally

(2022) categories: grouped by Transistor type:
BJT (TTL/ECL) vs. Field
Effect (CMOS).

99 A decoder is a: D) Combinational Its output depends strictly on

(2022) circuit the current input, not on
previous states (no memory).

100 Max noise voltage B) Noise Immunity Also called noise margin; it's
(2022) before logical state a gate's tolerance to
changes: unwanted voltage spikes.

101 Min NAND gates for C) 4 The Sum of a half adder is an

(2022) Half Adder Sum: XOR operation, which takes
exactly 4 NAND gates.
102 A multiplexer B) Several inputs to Acts as a digital rotary switch
(2022) switches: single output selecting one of many data
lines.

103 Fastest type of Analog D) Parallel comparator Also known as a Flash ADC;
(2022) to Digital converter: type uses multiple comparators to
convert in a single clock
cycle.

132 False statement D) 8086 has 8-bit The 8086 has a 16-bit
(2022) regarding 8086/8088: external data bus... external bus, while the 8088
has an 8-bit external bus.

133 The 8086/8088 is a: B) 16-bit Internally, both operate using

(2022) microprocessor 16-bit registers and ALUs.

134 Correct statements D) a, b and d only Direct Memory Access allows

(2022) about DMA: hardware peripherals to
bypass the CPU for
high-speed RAM transfers.

135 Considerations for D) a, b and c Size/Map, Expandability, and

(2022) microprocessor Access Time are all critical
memory: design factors.

136 Statements applicable C) a, b and c Multiplexed displays use

(2022) to MP applications: persistence of vision; LCDs
use low power; keyboards
use matrix grids.
1 The heart of any (a) CPU The Central Processing Unit
(2013) computer is the: acts as the brain.

2 Collection of wires (b) Bus A shared communication link

(2013) connecting devices: (data, address, control
buses).

3 Unit that executes and (a) CPU Processes instructions.

(2013) controls operations:

4 Microprocessors can (d) All of these Used in computers, digital

(2013) be used to make: systems, and calculators.

5 Which of the following (a) buffer Buffers are temporary storage

(2013) is not a register: areas, whereas PC,
Accumulator, and Stack
Pointers are fixed CPU
registers.

6 Stack consists of: (b) RAM The system stack is a

(2013) designated area within the
volatile Random Access
Memory.

[Link] Question Summary Correct Answer Explanation & Concept

52 NAND gate is called (b) All logical Any basic logic gate (AND, OR, NOT) or
a universal gate functions can complex circuit can be constructed using
because: be realized only NAND gates.

55 Number of (c) 255 An $n$-bit flash ADC requires $2^n - 1$

comparators in an comparators. For 8 bits, this is $2^8 - 1
8-bit parallel (Flash) = 255$ comparators.
ADC:

56 The decimal (b) 229 In hex, E = 14. To convert to decimal:

equivalent of $(14 \times 16^1) + (5 \times 16^0) =
hexadecimal number 224 + 5 = 229$.
E5 is:

78 Which transistor is (d) MOSFET MOSFETs have a very thin insulating

highly affected by silicon dioxide layer at the gate, which
static electricity? can easily be punctured and destroyed
by static electrostatic discharge (ESD).

84 Cross-over distortion (b) Class B Occurs when the signal crosses zero
takes place in: power amps and one transistor turns off before the
other turns on. (Fixed by using Class
AB).

89 Stack memory is (b) Save return When a microprocessor calls a

used to: addresses subroutine, it pushes the Program
Counter (PC) address to the stack so it
knows where to return after the
subroutine finishes.
[Link] Question Summary Official Answer Explanation / Concept
(Exam)

41 Intel 8085 is an _____ 8 bit NMOS The 8085 is a classic 8-bit

(2016) MUP. microprocessor built using N-type
metal-oxide-semiconductor logic.

176 The Programmable handle one or Devices like the 8259A prioritize
(2016) interrupt controller more interrupt and multiplex multiple external
(PIC) is required to: requests at a hardware interrupts into the CPU.
time

177 The number of 5 They are TRAP (highest priority),

(2016) hardware interrupts RST 7.5, RST 6.5, RST 5.5, and
present in 8085 are: INTR.

179 SD RAM refers to: Synchronous Unlike asynchronous RAM,

(2016) DRAM SDRAM coordinates memory
access with the exact clock speed
of the computer's CPU bus.

180 A stack is normally Stacks permit The LIFO (Last-In, First-Out)

(2016) used in digital easy nesting of nature of stacks makes it perfect
computers because: subroutine for tracking return addresses
when functions call other
functions.
181 Multiplexing of address Intel 8086 The 8086 multiplexes its lower 16
(2016) and data lines is used address lines with data lines
in: ($AD_0 - AD_{15}$) to reduce the
total number of physical pins on
the chip.

185 In 8085 MPU, the flag 5 The 8085 ALU sets five flags:
(2016) flip flops have _____ Sign (S), Zero (Z), Auxiliary Carry
status indicators. (AC), Parity (P), and Carry (CY).

186 The 8085 is an 8080 It added built-in serial I/O,

(2016) enhancement of the hardware interrupts, and required
popular INTEL _____ only a single +5V power supply.
microprocessor.

188 The address bus of 32 lines Correction: The 8085 has a 16-bit
(2016) 8085 MPU is a group address bus (addressing 64KB).
of: The official key's answer of 32
lines is factually incorrect for the
8085 chip.

192 In the high-level semicolon The ; acts as a statement

(2016) programming language separator/terminator in Pascal
Pascal, each program syntax.
statement ends with:

196 Dynamic memory cells MOSFETs DRAM cells consist of one

(2016) are constructed using: MOSFET acting as a switch and
one tiny capacitor to hold the
binary charge.
199 ADA is: assembly Correction: Ada is actually a
(2016) language strongly typed, high-level
object-oriented programming
language designed for the US
DoD. The provided key is
inaccurate.

Q# Section Question & Correct Explanation

Options Answer

1 Microprocessor Microprocessor (D) all these Depending on the

can be above architecture and
application, processors can
involve micro-programming
(microcode),
macro-programming
(a) non (assembly/high-level), or
programmable be hardwired/fixed
(non-programmable for
specific embedded tasks,
though less common).

(b) macro
programmable

(c) micro
programmable
 (d) all these above

2 Microprocessor An OP code (B) instructs An Opcode (Operation

the CPU Code) is the portion of a
machine language
instruction that tells the
CPU what operation needs
(a) translates a to be performed (e.g.,
mnemonic ADD, SUB, MOV).

(b) instructs the

CPU

(c) Stores data

(d) all the above

3 Microprocessor Which of the (C) The instruction cycle (often
following cycle is introduction mistakenly printed as
required to fetch cycle introduction here) is the
and execute basic operational process
information of a computer where the
CPU fetches an instruction
from memory, decodes it,
and executes it.

a. Clock cycle

b. Tricycle

c. introduction
cycle (Note: likely
typo for
'instruction')

d. memory cycle
4 Microprocessor Stack memory is (B) to save The stack is a LIFO (Last
used return In, First Out) memory
addresses of a structure used primarily to
sub routine store the return address
and processor state (like
flags) during subroutines or
a. to provide interrupts.
additional memory
to the base
memory

b. to save return
addresses of a sub
routine

c. to save the
status of the
microprocessor

d. none of the
above
5 Microprocessor ACK indicates (A) Correct ACK (Acknowledgment) is
reception of data a communication control
character or signal sent by
a receiver to indicate that it
has successfully received a
block of data without
a. Correct data errors.

b. incorrect data

c. Insufficient data

d. [missing option]

6 Microprocessor Every processor (D) data bus, a A standard microprocessor

must necessarily control bus architecture requires all
have and an three: an address bus to
address bus specify memory locations,
a data bus to transfer the
actual data, and a control
bus to manage operations
a. data bus (read/write signals, etc.).

b. data bus and

address bus
 c. control bus

d. data bus, a
control bus and an
address bus

7 Microprocessor An instruction used (B) arithmetic The Carry flag is usually

to set the carry flag affected or set by
in a computer can arithmetic operations (like
be classified as addition with carry, STC -
Set Carry flag, or shifting
operations).

a. data transfer

b. arithmetic

c. logical

d. Program control
8 Microprocessor Which of the (B) debug Debugging is the
following actions systematic process of
detect locations finding and resolving bugs
and remove (errors or defects) in
mistakes from a computer programs,
programme routine software, or systems.

a. Erase

b. debug

c. Diagnose

d. Emulate
9 Microprocessor In 8086 (A) NMI NMI (Non-Maskable
microprocessor the Interrupt) has the highest
following has the priority among external
highest priority hardware interrupts in the
among all type 8086 microprocessor
interrupts. because it cannot be
disabled by software
instructions.

a. NMI

b. DIV 0

c. TYPE 255

d. OVER FLOW
10 Microprocessor In 8086 the (B) Signed The Overflow Flag (OF)
overflow flag is set numbers go indicates when the result of
when out of their a signed arithmetic
range after an operation is too large (or
arithmetic too small) to fit into the
operation destination register,
effectively changing the
a. The sum is more sign bit incorrectly.
than 16 bits

b. Signed numbers
go out of their
range after an
arithmetic
operation

c. Carry and sign

flags are set

d. during
subtraction

Q# Question & Options Correct Answer Explanation

11 8088 microprocessor differs (A) Data width on the The primary difference is the
with 8086 microprocessor in output external data bus width. The
8086 has a 16-bit external
data bus, while the 8088 has
an 8-bit external data bus
(though internally both are
a. Data width on the output 16-bit processors).

b. Address capability

c. Support of coprocessor

d. Support of MAX / MIN

mode

12 In ADC 0808 if ____ pin high (D) OE OE stands for "Output

enables output. Enable." In the ADC 0808
(an Analog-to-Digital
Converter), setting the OE
pin high enables the tri-state
output buffers to output the
a. EOC converted digital data.

b. I/PO-I/P7
 c. SOC

d. OE

13 The 8279 normally provides a (B) 16 The Intel 8279 is a

maximum of ____ seven programmable
segment display interface keyboard/display controller.
with CPU. It can drive multiplexed
displays and supports a
maximum of 16
seven-segment displays.

a. 8

b. 16

c. 32

d. 18
14 In 8086 microprocessor one (B) AAD AAD (ASCII Adjust for
of the following instructions is Division) is executed before
executed before an arithmetic division. (AAM, DAS, and
operation DAA are usually executed
after their respective
arithmetic operations to
adjust the result).

a. AAM

b. AAD

c. DAS

d. DAA

15 Intel's 8085 microprocessor (D) eight 8 bit The 8085 has the
chip contains registers Accumulator (A), flags (often
grouped as a PSW), and six
general-purpose registers
(B, C, D, E, H, L), which
function as 8-bit registers.
a. seven 8 bit registers

b. 8 seven bit registers

 c. seven 7 bit registers

d. eight 8 bit registers.

16 Some system architects do (A) result in large RISC (Reduced Instruction

not find RISC instruction increase in Set Computer) uses simpler
repertoire to be cost-effective programme size instructions. Complex tasks
because it require more lines of these
simple instructions, which
can significantly increase
the overall size of the
compiled program in
a. result in large increase in memory.
programme size

b. result in complex structure

of microcode

c. has been observed that an

average compiler does not
employ more than a limited
subset of available
instructions
 d. results in complex
decoding of opcode flied
resulting in longer execution
time

17 The zero flag of 8085 (D) CMP A CMP A compares the

microprocessor is to be set accumulator with itself by
keeping the content of the performing an internal
accumulator unchanged. subtraction ($A - A = 0$).
Which instruction is to be This sets the Zero Flag to 1,
used? but leaves the actual
contents of the accumulator
unchanged.

a. MOV A, A

b. ANI 00H

c. XRA A

d. CMP A
18 Let the content of the (C) 8DH LDA 3501H loads 72H into
memory location 3501H be A. CMA complements the
72H. Now consider the accumulator (72H = 0111
following program... The 0010; complemented = 1000
content of the memory 1101 = 8DH). STA 3502H
location 3502H after stores 8DH in 3502H.
execution of programme will
be

a. 27H

b. D8H

c. 8DH

d. 72H

19 The first operating system (D) Note: The answer Based on the provided
used in micro processor is key points to D, though answer key, the correct
historically CP/M was option for this specific exam
heavily tied to early is D.
microprocessors.

a. UNIX
 b. DOS

c. CP/M

d. MULTICS

20 After reset, the CPU brings (A) 0000H In the Intel 8085, an external
execution from memory hardware reset forces the
location Program Counter (PC) to
0000H, causing the
processor to start execution
from that address.

a. 0000H

b. 0001H

c. FFFFH

d. FFF0H
21 The maximum addressing (C) 64 K bytes The 8085 has a 16-bit
capability of Intel 8085 is address bus. The maximum
memory it can address is
$2^{16}$ bytes, which
equals 65,536 bytes or 64
KB.
a. 8 K bytes

b. 32 K bytes

c. 64 K bytes

d. 128 K bytes

22 If $CS=A^{\prime}15$ (D) 6000H-6FFF H & The chip select uses

A14A13 is used as the chip 7000 H-7FFF H A15(low), A14(high),
select logic of a 4k RAM... A13(high). This corresponds
then its memory range will be to binary 011X XXXX XXXX
XXXX (6000H-6FFFH) or
0111 ... (7000H). Based on
the provided answer key.

a. 3000 H-3FFFH

b. 7000 H-7FFFH
 c. 5000H-5FFFH & 6000
H-6FFF H

d. 6000H-6FFF H & 7000

H-7FFF H

23 The following sequence of (C) SP=27 FF The CALL instruction

instructions are executed... HL=1006 pushes the return address
The contents of the stack (1006H) onto the stack (SP
pointer (SP) and the HL drops by 2). POP H
register pair on completion of removes it from the stack
execution of these into HL, returning SP back
instructions are to 27FFH and setting HL to
1006H.

a. $SP=27 FF$ $HL=1003$

b. $SP=27 FD$, $HL=1003$

c. $SP=27 FF$ $HL=1006$

 d. $SP=27 FD$ $HL=1006$

24 The contents of Accumulator (B) A=F1, CY=1, S=1 3AH - 49H. Since 3A < 49, a
(A) and Register (B)... are 3A borrow (Carry = 1) is
H and 49 H respectively. The generated. The result in 2's
contents of A and the status complement is F1H, which is
carry flag (CY) and sign flag a negative number, setting
(S) after execution of SUB B the Sign flag to 1.
are

a. A=FO, CY=0, S=0

b. A=F1, CY=1, S=1

c. A=0F, CY=1, S=0

d. A=1F CY=1, S=1

25 The following program is run (A) 200A H and OFFC Two PUSH operations
on an 8085... At the H decrease SP by 4. A CALL
completion of execution... the pushes the return address
contents of the Program (decreases by 2). Then one
counter and Stack Pointer are POP increases SP by 2.
respectively Total SP change is $1000H -
4 = 0FFCH$. PC halts at the
HLT instruction (200AH).

a. 200A H and OFFC H

b. 2050 H and OCCF H

c. 200A H and CCFO H

d. 2050 H and OFFC H

26 A memory system of size 16 (C) 8 12 address lines give
Kbytes is required to be $2^{12} = 4K$ addresses. 4
designed using memory chips data lines mean 4K x 4 bits
which have 12 address lines = 2KB per chip. To get
and 4 data lines each. The 16KB, you need $16KB /
number of such chips 2KB = 8$ chips.
required is

a. 2

b. 4

c. 8

d. 16

27 The flag which is not used for (B) Auxiliary carry The Auxiliary Carry (AC) flag
branching in a flag is used internally for BCD
microprocessor is arithmetic operations (like
the DAA instruction). It is not
directly accessible for
conditional branching
instructions (like JZ, JC).
a. Carry flag
 b. Auxiliary carry flag

c. Overflow flag

d. Parity flag

28 The address bus of Intel 8085 (D) 64 bytes (Kbytes) With a 16-bit address bus,
is 16 bit and hence the the addressable memory is
memory which can be $2^{16} = 65,536$ locations,
accessed by this address bus which equates to 64
is KiloBytes.

a. 1k byte

b. 16 k bits

c. 32 k bits
 d. 64 bytes (typo in source:
Kbytes)

29 The register which keeps (D) Program counter The Program Counter (PC)
track of the sequences of is a dedicated register that
instruction execution always holds the memory
address of the next
instruction to be fetched and
executed by the CPU.

a. Memory address register

b. Memory buffer register

c. Stack pointer

d. Program counter
30 The scheme used for data (D) All the above Microprocessors use
transfer between synchronous transfer for
microprocessor and I/O matching speeds,
device asynchronous with
handshaking for different
speeds, and interrupt-driven
transfers for efficiency.

a. Synchronous data transfer

b. Asynchronous data
transfer

c. Interrupt driven data

transfer

d. All the above

Q# Question Correct Explanation

Answer

31 The number of bits 12 To address 4 KiloBytes (4096 bytes) of

needed to address 4 K memory, you need $2^{12}$ addresses.
memory is Therefore, 12 address lines/bits are
required.
32 Program counter is used Store address The Program Counter (PC) keeps track
to of the next of the execution sequence by holding
instruction to the memory address of the very next
be executed instruction the CPU needs to fetch.

33 The stack pointer in the 16 bit register Because memory addresses in the
8085 microprocessor is a which points 8085 are 16 bits wide, the Stack Pointer
to stack (SP) must also be a 16-bit register to
memory point to the top of the stack in memory.
locations

34 8086 microprocessor is 16 Bit The 8086 is a 16-bit microprocessor

......Bit microprocessor because its internal registers, Arithmetic
Logic Unit (ALU), and external data bus
are all 16 bits wide.

35 MAX1455 is a signal Pressure The MAX1455 is a highly integrated,

conditioning chip which piezoresistive sensor signal conditioner
senses commonly used for automotive pressure
sensing applications.

36 Which mode is used for Mode 2 In the Intel 8255 Programmable

double handshake in Peripheral Interface (PPI), Mode 2
8255 provides a bi-directional data bus with
interrupt-driven handshaking (often
called a double handshake).

37 Which is designed to 8255 The 8255 PPI chip is specifically

automatically manage the designed with control modes (Mode 1
handshake operation: and Mode 2) that automatically handle
 handshaking signals for data transfers
between the CPU and peripherals.

38 The no. of wait states One Depending on the clock speed of the
required to Interface 8279 8086, interfacing with slower peripheral
to 8086 clock are controllers like the 8279
(Keyboard/Display controller) typically
requires inserting wait states to
synchronize data transfer.

39 Which signal represents Both (Interrupt Note: The source text for this question
synchronization signal and Transfer) is slightly garbled, but it refers to signals
decide by interprocess used to synchronize hardware control,
arbitration with a certain relying on interrupt and transfer
delay or signal DMA: acknowledgement lines during DMA or
arbitration.

40 ...... is a dedicated Input-Output An IOP is an advanced controller that

processor that combines Processor unburdens the main CPU by handling
interface unit and DMA (IOP) all I/O processing, DMA transfers, and
as one unit peripheral interfacing independently.

41 The external device is Interrupt External peripherals request the CPU's

connected to a pin called attention by sending a signal to its
the ...... pin on the interrupt pins (like INTR or NMI on the
processor chip. 8086).

42 SP stands for Stack Pointer SP is the standard abbreviation for the

Stack Pointer register.
43 In a non-vectored Assigned to a Unlike vectored interrupts where the
interrupt, the address of fixed memory interrupting device supplies the vector
interrupt service routine is location address, non-vectored interrupts force
the CPU to jump to a predetermined,
fixed memory address to find the
service routine.

44 8086 is interfaced to two 64 Note: While the document's answer key

8259s, if 8259s are in points to 64 (which is the theoretical
master slave maximum for a single master connected
configuration the number to 8 slaves), physically connecting just
of interrupts available to two 8259s (1 master, 1 slave) actually
the 8086 microprocessor yields 15 interrupts ($8 + 8 - 1$). For the
is sake of the exam key, 64 is the
expected answer for maximum
cascaded capability.

45 In 8255, under the I/O 3 The 8255 operates in three I/O modes:
mode of operation we Mode 0 (Basic I/O), Mode 1 (Strobed
have ....... modes. I/O), and Mode 2 (Bi-directional Bus).

46 The 8279 normally 16 The Intel 8279 is designed to multiplex

provide a maximum of and drive up to sixteen 7-segment
...... seven segment displays (or a $16 \times 8$ display
display interface with RAM).
CPU
47 8088 microprocessor has 4 byte Note: The book's answer key lists 'D'
pre-fetch (16 bit address bus), which is incorrect
queue because the 8088 has a 20-bit address
bus. The correct technical fact listed
among the original options is that it has
a 4-byte instruction pre-fetch queue
(unlike the 8086, which has a 6-byte
queue).

48 Number of the times the 256 AL is an 8-bit register starting at 00h.

instruction sequence INC increases it by 1. It will count up to
below will loop before FFh (255), and on the 256th execution,
coming out of loop is: it will roll over to 00h. This sets the Zero
MOV AL, 00h / A1: INC Flag, causing the JNZ (Jump if Not
AL / JNZ A1 Zero) condition to fail and exiting the
loop.

49 In a 8086/8088 Bus Interface The 8086 architecture is split into two

Microprocessor, the unit Unit (BIU) parts: the Execution Unit (EU)
responsible for getting processes data, while the BIU handles
the instructions from all external bus operations, including
memory and loading in fetching instructions and queuing them.
the Queue is

50 The ...... address of a Physical The 8086 generates a 20-bit physical

memory is a 20 bit address by shifting a 16-bit segment
address for the 8086 register left by 4 bits and adding a 16-bit
microprocessor: logical/offset address.

Q# Question Correct Answer Explanation

51 DMA is particularly disk drive and Direct Memory Access (DMA) allows
suited for data transfer RAM high-speed I/O devices (like disk
between the drives) to transfer data directly to or
from the main memory (RAM) without
burdening the CPU.

52 Microprocessor 8085 64K The 8085 has a 16-bit address bus.

can address location up The maximum memory it can address
to is $2^{16}$, which equates to 65,536
bytes or 64 KB.

53 Assembly language uses alphabetic Assembly language uses

codes in place of human-readable mnemonics (like
binary numbers ADD, MOV, SUB) instead of the raw
used in machine 1s and 0s of machine code to make
language programming easier.

54 How many $128 \times 16 The required capacity is 2048 bytes

8$ RAM chips are (which is $2048 \times 8$ bits). Each
needed to provide a chip provides 128 bytes ($128 \times
memory capacity of 8$ bits). Therefore, you need $2048 /
2048 bytes? 128 = 16$ chips.

55 Chip select (CS) decoder In memory interfacing, an address

connects the output of decoder translates the higher-order
address lines into a specific Chip
Select ($\overline{CS}$) signal to
activate the correct memory chip.
56 What is the address 64 kB With 16 address pins, the processor
space for a CPU having can generate $2^{16}$ unique
16 pins reserved for addresses, which is equal to 64
generating an address? Kilobytes (kB).

57 8086 is designed to 2 modes The 8086 microprocessor operates in

operate in two modes: Minimum Mode (for
single-processor systems) and
Maximum Mode (for multiprocessor
systems).

58 If MN/MX bar is low, the Maximum mode The MN/$\overline{MX}$ pin is active
8086 operates in high for Minimum mode and active
low for Maximum mode. When pulled
low (0V), the processor enters
Maximum mode.

59 In 8279, the size of built 8 bytes The Intel 8279 Keyboard/Display

in FIFO RAM is controller features an internal $8
\times 8$ FIFO (First-In-First-Out)
sensor RAM used to store keyboard
entries.

60 ...... is a multifunction 8155 The Intel 8155 is a versatile peripheral

PPI device that contains chip that includes 256 bytes of static
RAM, Timer and I/O RAM, two 8-bit I/O ports, one 6-bit I/O
ports. port, and a 14-bit timer.

61 Which is not a part of Clock The Execution Unit (EU) of the 8086
the Execution Unit contains the ALU, general-purpose
(EU)? registers, and flags. The clock is a
 system-level component, not internal
to the EU.

62 Which group of Data transfer Data transfer instructions (like MOV,

instructions do not affect instructions PUSH, POP) only move data from
the flags? one place to another; they do not
perform arithmetic or logical
evaluations, so they leave flags
unchanged.

63 Which of the following 8086 The 8086 is a "real-mode" processor.

processor does not Protected mode, memory
supports memory management, and virtual memory
management and support were introduced later with the
protection mechanisms? 80286 and 80386 processors.

64 Shift instructions move Both left & right Microprocessors have instructions for
binary data to the ...... shifting bits to the left (SHL, SAL) and
by shifting them within to the right (SHR, SAR) to perform
the register or memory rapid multiplication/division or bit
location. manipulation.

65 Which of the following The 8086 has This statement is backwards. The
statements is false in 8-bit external 8086 actually has a 16-bit external
respect of 8086/8088 data bus and data bus, while the 8088 has an 8-bit
microprocessor? 8088 has an external data bus.
16-bit external
data bus.

66 The 8086/8088 is a 16 Bit processor Internally, both the 8086 and 8088
operate with 16-bit registers and a
 16-bit ALU, classifying them as 16-bit
microprocessors.

67 Which of the following a, b and d only DMA transfers data directly between
statements is correct in source and destination (b), is an I/O
respect of DMA (Direct technique (d), and is controlled by an
Memory access)? external peripheral/controller (a).
Statement c is false because a DMA
is not a processor capable "only" of
copying data.

68 Which of the following a, b and c Memory size and mapping, access

are considerations for time (speed), and future expandability
microprocessor memory are all critical factors when designing
design? the memory hierarchy for a
microprocessor.

69 Which of the following a, b and c Microprocessors are widely used to

statement is applicable control multiplexed 7-segment LED
for Microprocessor displays, interface with low-power
based applications LCDs, and scan matrix keyboards
(e.g., $5 \times 4$ matrices).