Memory Management • Address binding • Logical vs physical
address
Memory management is a core component of an operating system (OS) that controls how
memory is allocated, accessed, and protected. Two fundamental concepts in this domain are
address binding and the distinction between logical and physical addresses. Understanding
these ideas is essential for analyzing how programs are executed efficiently and safely in modern
systems.
Address Binding
Address binding refers to the process of mapping a program’s addresses (generated during
execution) to actual locations in main memory. A program typically uses symbolic names (like
variables), which are later converted into addresses. This binding can occur at three different
stages:
1. Compile-Time Binding
If the memory location where a program will reside is known at compile time, the compiler
generates absolute addresses. For example, if a variable x is assigned address 2000, then every
reference to x will directly use this fixed address.
Mathematically:
If base location = 2000 and offset of variable = 50
Then physical address = 2000 + 50 = 2050
However, this approach lacks flexibility because if the program is loaded into a different
memory location later, it must be recompiled.
2. Load-Time Binding
If the starting address is not known at compile time, the compiler generates relocatable code.
The actual physical address is determined when the program is loaded into memory.
Formula:
Physical Address = Base Address (decided at load time) + Offset
Example:
Base = 5000, Offset = 120
Physical Address = 5000 + 120 = 5120
This allows the program to be loaded at different memory locations without recompilation.
3. Execution-Time Binding
In modern systems, binding is often delayed until execution time. The CPU generates logical
addresses dynamically, and a hardware unit called the Memory Management Unit (MMU)
translates them into physical addresses.
This enables advanced features such as virtual memory, paging, and process isolation.
Logical vs Physical Address
Logical Address (Virtual Address)
A logical address is generated by the CPU during program execution. It represents the address as
seen by the program itself.
Example:
A program may refer to address 100, 200, 300, etc., regardless of where it is actually stored in
RAM.
Physical Address
A physical address refers to the actual location in the main memory (RAM). This is the real
address used by the memory hardware.
Address Translation
The transformation from logical to physical address is performed by the MMU. The simplest
scheme uses a base register and a limit register.
● Base Register: holds the starting physical address of the process
● Limit Register: defines the size of the process
Mathematical Representation
Let:
● Logical Address = LA
● Base Register = BR
● Physical Address = PA
Then:
PA = BR + LA
Condition for valid access:
0 ≤ LA < Limit
Example
Suppose:
Base Register = 1000
Limit = 500
If Logical Address = 200
Then:
PA = 1000 + 200 = 1200
This is valid since 0 ≤ 200 < 500.
If Logical Address = 600:
This is invalid because 600 ≥ 500 → causes a memory protection fault.
Importance of Logical vs Physical Address
1. Memory Protection
Logical addressing prevents one process from accessing another process’s memory. Each
process has its own logical address space.
2. Relocation
Programs can be loaded anywhere in memory without modification. Logical addresses
remain the same, while physical addresses change dynamically.
3. Efficient Memory Use
With techniques like paging and segmentation, logical memory can be mapped non-
contiguously to physical memory, reducing fragmentation.
Visualization of Mapping
Consider a process with logical addresses from 0 to 999. Suppose it is loaded into physical
memory starting at address 5000.
Then:
Logical Address Range: 0 → 999
Physical Address Range: 5000 → 5999
Mapping function:
PA = 5000 + LA
So:
LA = 0 → PA = 5000
LA = 250 → PA = 5250
LA = 999 → PA = 5999
Advanced Concept: Paging (Brief Insight)
In paging, logical memory is divided into fixed-size pages, and physical memory into frames.
The mapping is:
PA = (Frame Number × Page Size) + Offset
Example:
Page Size = 100 bytes
Page Number = 2
Offset = 30
Frame Number = 5
Then:
PA = (5 × 100) + 30 = 530
This allows non-contiguous allocation and improves memory utilization.
Address binding and the distinction between logical and physical addresses form the foundation
of memory management in operating systems. Address binding determines when and how
addresses are assigned, while logical and physical addressing enable flexibility, protection, and
efficiency. The mathematical relationships such as:
PA = Base + Logical Address
and
PA = Frame × Page Size + Offset
highlight how operating systems translate program-level addresses into real memory locations.
These mechanisms are crucial for multitasking environments, ensuring that multiple processes
can coexist safely and efficiently in memory.
Case Study 1: Process Relocation Using Base and Limit Register
Scenario
A process is loaded into memory using execution-time binding. The system uses a base
register and a limit register for address translation and protection.
● Base Register (BR) = 4000
● Limit Register = 800
● The CPU generates the following logical addresses:
LA₁ = 120, LA₂ = 750, LA₃ = 900
Analysis
Using the address translation formula:
PA=BR+LA
Step-by-step evaluation:
1. For LA₁ = 120
o Check: 0 ≤ 120 < 800
o PA = 4000 + 120 = 4120
2. For LA₂ = 750
o Check: 0 ≤ 750 < 800
o PA = 4000 + 750 = 4750
3. For LA₃ = 900
o Check: 900 ≥ 800
o Result: Memory Protection Fault
Learning Outcome (OBE Alignment)
● Apply address translation formulas
● Analyze memory protection using limit register
● Evaluate valid vs invalid memory access
OBE Questions
Q1. (Cognitive Level: Apply)
Calculate the physical addresses for LA = 120 and LA = 750.
Answer:
● PA₁ = 4000 + 120 = 4120
● PA₂ = 4000 + 750 = 4750
Q2. (Cognitive Level: Analyze)
Why does LA = 900 cause an error?
Answer:
Because it violates the condition:
0 ≤ LA < Limit → 900 ≥ 800 → invalid access, resulting in a memory protection fault.
Q3. (Cognitive Level: Evaluate)
Explain how the base and limit registers ensure memory protection.
Answer:
The base register ensures relocation by shifting logical addresses to physical memory, while the
limit register enforces bounds checking. Any logical address outside the limit is blocked,
preventing unauthorized memory access.
Case Study 2: Paging-Based Address Translation
Scenario
A system uses paging for memory management.
● Page Size = 256 bytes
● Logical Address = 1025
● Page Table Entry: Page 4 → Frame 9
Analysis
Step 1: Break logical address into page number and offset:
● Page Number = ⌊1025 / 256⌋ = 4
● Offset = 1025 mod 256 = 1
Step 2: Use paging formula:
PA=(Frame×Page Size)+OffsetPA
PA = (9 × 256) + 1 = 2305
Learning Outcome (OBE Alignment)
● Apply paging formula for address translation
● Decompose logical address into page number and offset
● Interpret page table mapping
OBE Questions
Q1. (Cognitive Level: Apply)
Find the page number and offset for logical address 1025.
Answer:
● Page Number = 4
● Offset = 1
Q2. (Cognitive Level: Apply)
Calculate the physical address.
Answer:
PA = (9 × 256) + 1 = 2305
Q3. (Cognitive Level: Analyze)
What happens if the page is not present in memory?
Answer:
A page fault occurs. The OS must load the required page from secondary storage into memory
before continuing execution.
Q4. (Cognitive Level: Evaluate)
Compare paging with base-limit addressing.
Answer:
● Paging allows non-contiguous memory allocation, reducing fragmentation
● Base-limit requires contiguous allocation
● Paging is more flexible but introduces overhead (page tables, translation time)