Features

• Compatible with MCS-51™ Products

• 4K Bytes of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 3.0V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 15 Programmable I/O Lines
•
•
Two 16-bit Timer/Counters
Six Interrupt Sources
8-bit
• Programmable Serial UART Channel
• Direct LED Drive Outputs Microcontroller
• On-chip Analog Comparator
• Low-power Idle and Power-down Modes with 4K Bytes
• Brown-out Detection
Flash
Description
The AT89C4051 is a low-voltage, high-performance CMOS 8-bit microcomputer with
4K bytes of Flash programmable and erasable read only memory (PEROM). The AT89C4051
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard MCS-51 instruction set. By combining a
versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C4051 is a power-
ful microcomputer which provides a highly-flexible and cost-effective solution to many
embedded control applications.
The AT89C4051 provides the following standard features: 4K bytes of Flash, 128
bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator
and clock circuitry. In addition, the AT89C4051 is designed with static logic for opera-
tion down to zero frequency and supports two software-selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port and interrupt system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator disabling all other chip functions until the next
hardware reset.

Pin Configuration

PDIP/SOIC

RST/VPP 1 20 VCC
(RXD) P3.0 2 19 P1.7
(TXD) P3.1 3 18 P1.6
XTAL2 4 17 P1.5
XTAL1 5 16 P1.4
(INT0) P3.2 6 15 P1.3
(INT1) P3.3 7 14 P1.2
(TO) P3.4 8 13 P1.1 (AIN1)
(T1) P3.5 9 12 P1.0 (AIN0)
GND 10 11 P3.7

Rev. 1001C–02/00

1
Block Diagram

2 AT89C4051
 AT89C4051

Pin Description Each machine cycle takes 12 oscillator or clock cycles.

XTAL1
VCC
Input to the inverting oscillator amplifier and input to the
Supply voltage.
internal clock operating circuit.
GND
XTAL2
Ground.
Output from the inverting oscillator amplifier.
Port 1
Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to Oscillator Characteristics
P1.7 provide internal pullups. P1.0 and P1.1 require exter-
XTAL1 and XTAL2 are the input and output, respectively,
nal pullups. P1.0 and P1.1 also serve as the positive input
of an inverting amplifier which can be configured for use as
(AIN0) and the negative input (AIN1), respectively, of the
an on-chip oscillator, as shown in Figure 1. Either a quartz
on-chip precision analog comparator. The Port 1 output
crystal or ceramic resonator may be used. To drive the
buffers can sink 20 mA and can drive LED displays directly.
device from an external clock source, XTAL2 should be left
When 1s are written to Port 1 pins, they can be used as
unconnected while XTAL1 is driven as shown in Figure 2.
inputs. When pins P1.2 to P1.7 are used as inputs and are
There are no requirements on the duty cycle of the external
externally pulled low, they will source current (IIL) because
clock signal, since the input to the internal clocking circuitry
of the internal pullups.
is through a divide-by-two flip-flop, but minimum and maxi-
Port 1 also receives code data during Flash programming mum voltage high and low time specifications must be
and verification. observed.

Port 3 Figure 1. Oscillator Connections

Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O
pins with internal pullups. P3.6 is hard-wired as an input to
the output of the on-chip comparator and is not accessible
as a general purpose I/O pin. The Port 3 output buffers can
sink 20 mA. When 1s are written to Port 3 pins they are
pulled high by the internal pullups and can be used as
inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C4051 as listed below:

Port Pin Alternate Functions

P3.0 RXD (serial input port)
Note: C1, C2= 30 pF ± 10 pF for Crystals
P3.1 TXD (serial output port) = 40 pF ± 10 pF for Ceramic Resonators
P3.2 INT0 (external interrupt 0)
Figure 2. External Clock Drive Configuration
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)

Port 3 also receives some control signals for Flash pro-

gramming and verification.

RST
Reset input. All I/O pins are reset to 1s as soon as RST
goes high. Holding the RST pin high for two machine
cycles while the oscillator is running resets the device.

3
Special Function Registers
A map of the on-chip memory area called the Special Func- User software should not write 1s to these unlisted loca-
tion Register (SFR) space is shown in the table below. tions, since they may be used in future products to invoke
Note that not all of the addresses are occupied, and unoc- new features. In that case, the reset or inactive values of
cupied addresses may not be implemented on the chip. the new bits will always be 0.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.

Table 1. AT89C4051 SFR Map and Reset Values

0F8H 0FFH

0F0H B 0F7H
00000000
0E8H 0EFH

0E0H ACC 0E7H

00000000
0D8H 0DFH

0D0H PSW 0D7H

00000000
0C8H 0CFH

0C0H 0C7H

0B8H IP 0BFH
XXX00000
0B0H P3 0B7H
11111111
0A8H IE 0AFH
0XX00000
0A0H 0A7H

98H SCON SBUF 9FH

00000000 XXXXXXXX
90H P1 97H
11111111
88H TCON TMOD TL0 TL1 TH0 TH1 8FH
00000000 00000000 00000000 00000000 00000000 00000000
80H SP DPL DPH PCON 87H
00000111 00000000 00000000 0XXX0000

4 AT89C4051
 AT89C4051

Restrictions on Certain Instructions Program Memory Lock Bits

The AT89C4051 is an economical and cost-effective mem- On the chip are two lock bits which can be left unpro-
ber of Atmel’s growing family of microcontrollers. It grammed (U) or can be programmed (P) to obtain the
contains 4K bytes of flash program memory. It is fully com- additional features listed in the following table:
pati bl e with the MCS-51 arc hitec tur e, and c an be
programmed using the MCS-51 instruction set. However, Lock Bit Protection Modes(1)
there are a few considerations one must keep in mind
Program Lock Bits
when utilizing certain instructions to program this device.
All the instructions related to jumping or branching should LB1 LB2 Protection Type
be restricted such that the destination address falls within 1 U U No program lock features.
the physical program memory space of the device, which is
2 P U Further programming of the Flash
4K for the AT89C4051. This should be the responsibility of
is disabled.
the software programmer. For example, LJMP 0FE0H
would be a valid instruction for the AT89C4051 (with 4K of 3 P P Same as mode 2, also verify is
memory), whereas LJMP 1000H would not. disabled.
Note: 1. The Lock Bits can only be erased with the Chip Erase
1. Branching instructions: operation.
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR.
These unconditional branching instructions will execute Idle Mode
correctly as long as the programmer keeps in mind that the
destination branching address must fall within the physical In idle mode, the CPU puts itself to sleep while all the on-
boundaries of the program memory size (locations 00H to chip peripherals remain active. The mode is invoked by
FFFH for the 89C4051). Violating the physical space limits software. The content of the on-chip RAM and all the spe-
may cause unknown program behavior. cial functions registers remain unchanged during this
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With mode. The idle mode can be terminated by any enabled
these conditional branching instructions the same rule interrupt or by a hardware reset.
above applies. Again, violating the memory boundaries P1.0 and P1.1 should be set to “0” if no external pullups are
may cause erratic execution. used, or set to “1” if external pullups are used.
For applications involving interrupts the normal interrupt It should be noted that when idle is terminated by a hard-
service routine address locations of the 80C51 family archi- ware reset, the device normally resumes program
tecture have been preserved. execution, from where it left off, up to two machine cycles
before the internal reset algorithm takes control. On-chip
2. MOVX-related instructions, Data Memory: hardware inhibits access to internal RAM in this event, but
The AT89C4051 contains 128 bytes of internal data mem- access to the port pins is not inhibited. To eliminate the
ory. Thus, in the AT89C4051 the stack depth is limited to possibility of an unexpected write to a port pin when Idle is
128 bytes, the amount of available RAM. External DATA terminated by reset, the instruction following the one that
memory access is not supported in this device, nor is exter- invokes Idle should not be one that writes to a port pin or to
nal PROGRAM memory execution. Therefore, no MOVX external memory.
[...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions, Power-down Mode
even if they are written in violation of the restrictions men-
In the power-down mode the oscillator is stopped, and the
tioned above. It is the responsibility of the controller user to
instruction that invokes power-down is the last instruction
know the physical features and limitations of the device
executed. The on-chip RAM and Special Function Regis-
being used and adjust the instructions used
ters retain their values until the power-down mode is
correspondingly.
terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before VCC
is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.
P1.0 and P1.1 should be set to “0” if no external pullups are
used, or set to “1” if external pullups are used.

5
Brown-out Detection
When VCC drops below the detection threshold, all port pins erated after a delay of typically 15 msec. The nominal
(except P1.0 and P1.1) are weakly pulled high. When VCC brown-out detection threshold is 2.3V ± 10%.
goes back up again, an internal Reset is automatically gen-

VCC
2.3V 2.3V

PORT PIN

INTERNAL RESET
15 msec.

Programming The Flash

The AT89C4051 is shipped with the 4K bytes of on-chip 9. Repeat steps 5 through 8, changing data and
PEROM code memory array in the erased state (i.e., con- advancing the address counter for the entire 4K
tents = FFH) and ready to be programmed. The code bytes array or until the end of the object file is
memory array is programmed one byte at a time. Once the reached.
array is programmed, to re-program any non-blank byte, 10. Power-off sequence:
the entire memory array needs to be erased electrically. set XTAL1 to “L”
Internal Address Counter: The AT89C4051 contains an set RST to “L”
internal PEROM address counter which is always reset to Turn VCC power off
000H on the rising edge of RST and is advanced by apply- Data Polling: The AT89C4051 features Data Polling to
ing a positive going pulse to pin XTAL1. indicate the end of a write cycle. During a write cycle, an
Programming Algorithm: To program the AT89C4051, attempted read of the last byte written will result in the com-
the following sequence is recommended. plement of the written data on P1.7. Once the write cycle
1. Power-up sequence: has been completed, true data is valid on all outputs, and
Apply power between VCC and GND pins the next cycle may begin. Data Polling may begin any time
Set RST and XTAL1 to GND after a write cycle has been initiated.
2. Set pin RST to “H” Ready/Busy: The Progress of byte programming can also
Set pin P3.2 to “H” be monitored by the RDY/BSY output signal. Pin P3.1 is
pulled low after P3.2 goes High during programming to indi-
3. Apply the appropriate combination of “H” or “L” logic
cate BUSY. P3.1 is pulled High again when programming is
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of
done to indicate READY.
the programming operations shown in the PEROM
Programming Modes table. Program Verify: If lock bits LB1 and LB2 have not been
programmed code data can be read back via the data lines
To Program and Verify the Array:
for verification:
4. Apply data for Code byte at location 000H to P1.0 to
1. Reset the internal address counter to 000H by
P1.7.
bringing RST from “L” to “H”.
5. Raise RST to 12V to enable programming.
2. Apply the appropriate control signals for Read Code
6. Pulse P3.2 once to program a byte in the PEROM data and read the output data at the port P1 pins.
array or the lock bits. The byte-write cycle is self-
3. Pulse pin XTAL1 once to advance the internal
timed and typically takes 1.2 ms.
address counter.
7. To verify the programmed data, lower RST from 12V
4. Read the next code data byte at the port P1 pins.
to logic “H” level and set pins P3.3 to P3.7 to the
appropriate levels. Output data can be read at the 5. Repeat steps 3 and 4 until the entire array is read.
port P1 pins. The lock bits cannot be verified directly. Verification of the
8. To program a byte at the next address location, lock bits is achieved by observing that their features are
pulse XTAL1 pin once to advance the internal enabled.
address counter. Apply new data to the port P1
pins.

6 AT89C4051
 AT89C4051

Chip Erase: The entire PEROM array (4K bytes) and the Programming Interface
two Lock Bits are erased electrically by using the proper
combination of control signals and by holding P3.2 low for Every code byte in the Flash array can be written and the
10 ms. The code array is written with all “1”s in the Chip entire array can be erased by using the appropriate combi-
Erase operation and must be executed before any non- nation of control signals. The write operation cycle is self-
blank memory byte can be re-programmed. timed and once initiated, will automatically time itself to
completion.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of All major programming vendors offer worldwide support for
locations 000H, 001H, and 002H, except that P3.5 and the Atmel microcontroller series. Please contact your local
P3.7 must be pulled to a logic low. The values returned are programming vendor for the appropriate software revision.
as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 41H indicates 89C4051

Flash Programming Modes

Mode RST/VPP P3.2/PROG P3.3 P3.4 P3.5 P3.7
Write Code Data(1)(3) 12V L H H H

Read Code Data(1) H H L L H H

Write Lock Bit - 1 12V H H H H

Bit - 2 12V H H L L

Chip Erase 12V (2) H L L L

Read Signature Byte H H L L L L

Notes: 1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at
XTAL 1 pin.
2. Chip Erase requires a 10 ms PROG pulse.
3. P3.1 is pulled Low during programming to indicate RDY/BSY.

7
Figure 3. Programming the Flash Memory

AT89C4051

PP

Figure 4. Verifying the Flash Memory

AT89C4051

8 AT89C4051
 AT89C4051

Flash Programming and Verification Characteristics

TA = 0°C to 70°C, VCC = 5.0 ± 10%
Symbol Parameter Min Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 250 µA
tDVGL Data Setup to PROG Low 1.0 µs
tGHDX Data Hold after PROG 1.0 µs
tEHSH P3.4 (ENABLE) High to VPP 1.0 µs
tSHGL VPP Setup to PROG Low 10 µs
tGHSL VPP Hold after PROG 10 µs
tGLGH PROG Width 1 110 µs
tELQV ENABLE Low to Data Valid 1.0 µs
tEHQZ Data Float after ENABLE 0 1.0 µs
tGHBL PROG High to BUSY Low 50 ns
tWC Byte Write Cycle Time 2.0 ms
tBHIH RDY/BSY\ to Increment Clock Delay 1.0 µs
tIHIL Increment Clock High 200 ns
Note: 1. Only used in 12-volt programming mode.

Flash Programming and Verification Waveforms

9
Absolute Maximum Ratings*
Operating Temperature ................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage ............................................ 6.6V conditions for extended periods may affect device
reliability.
DC Output Current...................................................... 25.0 mA

DC Characteristics
TA = -40°C to 85°C, VCC = 3.0V to 6.0V (unless otherwise noted)
Symbol Parameter Condition Min Max Units
VIL Input Low-voltage -0.5 0.2 VCC - 0.1 V
VIH Input High-voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High-voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V
VOL Output Low-voltage(1) IOL = 20 mA, VCC = 5V 0.5 V
(Ports 1, 3) IOL = 10 mA, VCC = 2.7V

IOH = -80 µA, VCC = 5V ± 10% 2.4 V

Output High-voltage
VOH IOH = -30 µA 0.75 VCC V
(Ports 1, 3)
IOH = -12 µA 0.9 VCC V
IIL Logical 0 Input Current VIN = 0.45V -50 µA
(Ports 1, 3)
ITL Logical 1 to 0 Transition Current VIN = 2V, VCC = 5V ± 10% -750 µA
(Ports 1, 3)
ILI Input Leakage Current 0 < VIN < VCC ±10 µA
(Port P1.0, P1.1)
VOS Comparator Input Offset Voltage VCC = 5V 20 mV
VCM Comparator Input Common 0 VCC V
Mode Voltage
RRST Reset Pulldown Resistor 50 300 KΩ
CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
Active Mode, 12 MHz, VCC = 6V/3V 15/5.5 mA
Power Supply Current Idle Mode, 12 MHz, VCC = 6V/3V 5/1 mA
ICC P1.0 & P1.1 = 0V or VCC
VCC = 6V P1.0 & P1.1 = 0V or VCC 100 µA
Power-down Mode(2)
VCC = 3V P1.0 & P1.1 = 0V or VCC 20 µA
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 20 mA
Maximum total IOL for all output pins: 80 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.

10 AT89C4051
 AT89C4051

External Clock Drive Waveforms

External Clock Drive

VCC = 3.0V to 6.0V VCC = 4.0V to 6.0V
Symbol Parameter Min Max Min Max Units
1/tCLCL Oscillator Frequency 0 12 0 24 MHz
tCLCL Clock Period 83.3 41.6 ns
tCHCX High Time 30 15 ns
tCLCX Low Time 30 15 ns
tCLCH Rise Time 20 20 ns
tCHCL Fall Time 20 20 ns

11
Serial Port Timing: Shift Register Mode Test Conditions
VCC = 5.0V ± 20%; Load Capacitance = 80 pF
12 MHz Osc Variable Oscillator
Symbol Parameter Min Max Min Max Units
tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs
tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns
tXHQX Output Data Hold after Clock Rising Edge 50 2tCLCL-117 ns
tXHDX Input Data Hold after Clock Rising Edge 0 0 ns
tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1) Float Waveforms(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a Note: 1. For timing purposes, a port pin is no longer floating
logic 1 and 0.45V for a logic 0. Timing measurements when a 100 mV change from load voltage occurs. A
are made at VIH min. for a logic 1 and VIL max. for a port pin begins to float when 100 mV change frothe
logic 0. loaded VOH/VOL level occurs.

12 AT89C4051
 AT89C4051

AT89C4051
TYPICAL ICC - ACTIVE (85˚C)
20
Vcc=6.0V

I 15
C Vcc=5.0V
C 10
Vcc=3.0V
m
A 5

0
0 6 12 18 24
FREQUENCY (MHz)

AT89C4051
TYPICAL ICC - IDLE (85˚C)
3
Vcc=6.0V

I
C 2 Vcc=5.0V
C

m 1
A
Vcc=3.0V

0
0 3 6 9 12
FREQUENCY (MHz)

AT89C4051
TYPICAL ICC vs. VOLTAGE- POWER DOWN (85˚C)
20

I 15
C
C 10

µ
A 5

0
3.0V 4.0V 5.0V 6.0V
Vcc VOLTAGE

Notes: 1. XTAL1 tied to GND for ICC (power-down)

2. P.1.0 and P1.1 = VCC or GND
3. Lock bits programmed

13
Ordering Information
Speed Power
(MHz) Supply Ordering Code Package Operation Range
12 3.0V to 6.0V AT89C4051-12PC 20P3 Commercial
AT89C4051-12SC 20S (0°C to 70°C)
AT89C4051-12PI 20P3 Industrial
AT89C4051-12SI 20S (-40°C to 85°C)
24 4.0V to 6.0V AT89C4051-24PC 20P3 Commercial
AT89C4051-24SC 20S (0°C to 70°C)
AT89C4051-24PI 20P3 Industrial
AT89C4051-24SI 20S (-40°C to 85°C)

Package Type
20P3 20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)
20S 20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)

14 AT89C4051
 AT89C4051

Packaging Information
20P3, 20-lead, 0.300" Wide, Plastic Dual Inline 20S, 20-lead, 0.300" Wide, Plastic Gull WIng Small
Package (PDIP) Outline (SOIC)
Dimensions in Inches and (Millimeters) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AD

1.060(26.9) 0.020 (0.508)

.980(24.9) PIN 0.013 (0.330)
1

.280(7.11) 0.299 (7.60) 0.420 (10.7)

.240(6.10) 0.291 (7.39) 0.393 (9.98)
PIN 1

.090(2.29)
.900(22.86) REF MAX
.050 (1.27) BSC
.210(5.33) .005(.127)
MAX MIN

SEATING
PLANE 0.513 (13.0)
0.497 (12.6) 0.105 (2.67)
.150(3.81) .015(.381) MIN 0.092 (2.34)

.115(2.92) .022(.559)
.014(.356)
.070(1.78)
.110(2.79) 0.012 (0.305)
.045(1.13)
.090(2.29) 0.003 (0.076)

.325(8.26)
.300(7.62)
0
REF 0.013 (0.330)
0 REF 8
0.009 (0.229)
.014(.356) 15
.008(.203)
0.035 (0.889)
.430(10.92) MAX 0.015 (0.381)

15
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© Atmel Corporation 1999.

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ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
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1001C–02/00/xM