Introduction to Microcontrollers

Michele Magno
IIS Group - ETH Zurich

[Link]@[Link]

1
Outline

 MCU Architecture
 CPU
 Power Consumption
 MCU Peripherals
 ARM Architecture
 ARM Coretx
 ARM Instruction Set
 STM32 ARM Coretex Mx Family
 ISA
 Data Sheet Examples

2
 What is a microcontroller ?

A Microcontroller is a small CPU with many support devices built

into the chip
 Self Contained (CPU, Memory, I/O)
 Application or Task Specific (Not a general-purpose computer)
 Appropriately scaled for the job
 Small power consumption
 Low costs ( $0.50 to $5.00.)

3
Example of MCU Architecture
Clock Memory ADC - DAC I/O Port

CPU

BUS

DMA TIMERs USARTx

4
Performance Metrics
 How we compare and classify microcontrollers?
 Performance Metrics NOT easy to define and mostly application
depended.
Eletrical: Computation:
 Power Consumptions  Clock Speed
 Voltage Supply  MIPS (instructions per sec)
 Noise Immunity  Latency
 Lateness of the response
 Sensitivity  Lag between the begin and the end
of the computation
Goal: best tradeoff  Throughput
 Tasks per second
power consumptions Vs  Byte per second
performances

5
 Power as a Design Constraint

 Why worry about power?

 Battery life in portable and mobile platforms
 Power consumption in desktops, server farms
- Cooling costs, packaging costs, reliability, timing
- Power density: 30 W/cm2 in Alpha 21364
(3x of typical hot plate)
Where does power go in CMOS?
Dynamic power Power due to short-
circuit current Power due to
consumption
during transition leakage current

P = ACV f + τAVIshort f + VIleak

2

6
Dynamic Power Consumption
C – Total capacitance V – Supply voltage
seen by the gate’s outputs Trend: has been dropping
Function of wire lengths, with each successive fab
transistor sizes, ...

2
ACV f
A - Activity of gates f – clock frequency
How often on average do Trend: increasing ...
wires switch?

Reducing Dynamic Power

1) Reducing V has quadratic effect; Limits?
2) Lower C - shrink structures, shorten wires
3) Reduce switching activity - Turn off unused parts or
use design techniques to minimize number of transitions

7
Short-circuit Power Consumption

τAVIshort f
Finite slope of the input signal
causes a direct current path
between VDD and GND for a
Vin Ishort Vout short period of time during
switching when both the NMOS
CL and PMOS transistors are
conducting

Reducing Short-circuit
1) Lower the supply voltage V
2) Slope engineering – match the rise/fall time of the input and output signals

8
Leakage Power

VIleak

Sub-threshold
current

Sub-threshold current grows exponentially with

increases in temperature and decreases in Vt

9
How can we reduce
power consumption?
 Dynamic power consumption
 Reduce the rate of charge/discharge of highly loaded nodes
 Reduce spurious switching (glitches)
 Reduce switching in idle states (clock gating)
 Decrease frequency
 Decrease voltage (and frequency)
 Static power Consumption
 Smaller area (!)
 Reduce device leakage through power gating
 Reduce device leakage through body biasing
 Use higher-threshold transistors when possible

Power performance tradeoffs!

10
Operating Modes

11
Why Ultra-low Power Is so Important

 Longer battery life

 Smaller products
 Simpler power supplies
 Less EMI simplifies PCB
 Permanent battery
 Reduced liability

12
Clock Distribution
System Clock
Key Features:
Generator
• MCLK Main clock provided to the CPU
ACLK

SMCLK
• SMCLK Sub-Main clock provided to the peripherals
• ACLK Auxiliary clock at low frequency provided to the
MCLK

peripherals
• Peripherals can work at High and Low frequency
CPU

• Each Clock can be disabled (Clock Gating, reducing

dynamic power) by setting the status register SR.
• The CPU can be disabled (reducing Leakage power) by
setting the SR.

13
 Clock System Generator

Clock system Module

provides the clocks for the
MCU devices

14
 Memory
 RAM (usually SRAM)
 Volatile memory for runtime execution
 Fastest access, low amount (<100Kb)
 Allocates variables
 Flash ROM
 On-chip non-volatile memory used for code or data storage
 8-512Kb, about 10k write cycles
 Bootloader: protected section to upload code in flash
 (Ferroelectric Random Access Memory) FRAM
 Forefront of next generation non-volatile memory technology
 On-chip non-volatile memory faster (50ns) and lower power (250x less)
than Flash.
 External memory
 Connected via serial (I2C, SPI) or dedicated (FSMC) interface
15
 Memory - Address Space
 On-Chip FLASH/ROM and RAM memory
 Everything is mapped into a single, contiguous address space:
 All memory, including RAM, Flash/ROM, information memory,
special function registers (SFRs), and peripheral registers.
Memory Address Description Access
End: 0FFFFh Interrupt Vector Table
Word/Byte
Start: 0FFE0h
End: 0FFDFh
Flash/ROM
Word/Byte
0F800h
Start *:
01100h

Flash / ROM End *:

010FFh
0107Fh Information Memory Word/Byte
Start: 01000h (Flash devices only)
End: 0FFFh Boot Memory
Word/Byte
Start: 0C00h (Flash devices only)

RAM End *:
09FFh
027Fh RAM Word/Byte
Start: 0200h
End: 01FFh
16-bit Peripheral modules Word
Start: 0100h
Peripherals End:
Start:
00FFh
0010h
8-bit Peripheral modules Byte

End: 000Fh
Special Function Registers Byte
Start: 0000h

16
16
Interrupts
 A way to respond to an external event (i.e., Main Prog
flag being set) without polling ISR
:
How it works: :
:
 H/W senses flag being set :
 Automatically transfers control to s/w that RETI
“services” the interrupt
 When done, H/W returns control to
wherever it left off

Advantages:
 Transparent to user
 cleaner code
 μC doesn’t waste time polling

17
Interrupts: details

 3 types
 System reset
 (Non)-maskable NMI
 Maskable

 Interrupt priorities
could be fixed and
defined by the
arrangement of
modules or set in the
interrupt priority
register

18
(Non)-Maskable Interrupts

 Sources
 An edge on the RESET pin when configured in NMI mode
 An oscillator fault occurs
 An access violation to the flash memory

 Are not masked by GIE (General Interrupt

Enable), but are enabled by individual interrupt
enable bits

19
NMI Interrupt Handler example

20
 Maskable Interrupts

 Caused by peripherals with interrupt capability

 Each interrupt can be disabled individually by
an interrupt enable bit
 All interrupts can be disabled by GIE bit in the status
register

21
 Interrupt acceptance

1) Any currently executing instruction is completed.

2) The ProgramCounter PC, which points to the next instruction, is pushed onto the
stack.
3) The StatusRegister SR is pushed onto the stack.
4) The interrupt with the highest priority is selected if multiple interrupts occurred
during the last instruction and are pending for service.
5) The interrupt request flag resets automatically on single-source flags. Multiple source
flags remain set for servicing by software.
6) The SR is cleared. This terminates any low-power mode. Because the GIE bit is
cleared, further interrupts are disabled.
7) The content of the interrupt vector is loaded into the PC: the program continues with
the interrupt service routine at that address.

22
 Return from Interrupt

RETI - Return from Interrupt Service Routine

1. The SR with all previous settings pops from the stack. All
previous settings of GIE, CPUOFF, etc. are now in effect,
regardless of the settings used during the interrupt service
routine.
2. The PC pops from the stack and begins execution at the
point where it was interrupted.

23
 Timers
 Correct system timing is a fundamental requirement for the proper
operation of a real-time application;
 If the timing is incorrect, the input data may be processed after the output
was updated
 The timers may be driven from an internal or external clock;
 Usually timers include multiple independent capture and compare
blocks, with interrupt capabilities;
 Main applications:
 Generate events of fixed-time period;
 Allow periodic wake-up from sleep;
 Count external signals/events;
 Signal generation (Pulse Width Modulation – PWM);
 Replacing delay loops with timer calls allows the CPU to sleep between operations,
thus consuming less power.

24
24
Timers
• The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.

• They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input
capture) or generating output waveforms (output compare and PWM).

• Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds
using the timer prescaler and the RCC clock controller prescalers.

• General-purpose TIMx timer features include:

- 16-bit up, down, up/down auto-reload counter.

- 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any

factor between 1 and 65535.

- Up to 4 independent channels for:

‣ Input capture
‣ Output compare
‣ PWM generation (Edge- and Center-aligned modes)
‣ One-pulse mode output
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 Timers

General-purpose timer block diagram

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 Timers

PATH: TimerX - Channel 1 - output compare

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 Timers

PATH: TimerX - Channel 2 - output compare

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 Timers

PATH: TimerX - Channel 3 - output compare

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 Timers

PATH: TimerX - Channel 4 - output compare

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Timers

24MHz

31
Timers

32
Timers

The counter clock can be divided by a prescaler.

33
 Timers

The main block of the programmable timer is a 16-

bit counter with its related auto-reload register.
The counter can count up, down or both up and
down.

CNT

CK_CNT

34
 Timers

In upcounting mode, the counter counts from 0 to

the auto-reload value (content of the TIMx_ARR
register), then restarts from 0 and generates a
counter overflow event.

Period

Timer Interrupt
Autoreload
Register

CNT

CK_CNT

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 Timers

Output compare mode: This function is used to

control an output waveform or indicating when a
period of time has elapsed.

Timer Interrupt
Autoreload
Register

Compare
Register
CNT
CH1 Interrupt

OC1

CK_CNT

36
 Timers

Output compare mode: This function is used to

control an output waveform or indicating when a
period of time has elapsed.
Used to schedule
periodic events

Timer Interrupt
Autoreload
Register

Compare
Register
CNT
CH1 Interrupt

OC1

CK_CNT

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 Watchdog Timer (WDT)

 WDT module performs a controlled

system restart after a software
problem occurs
 Can serve as an interval timer
(generates interrupts)
 WDT Control register is
password protected

38
 Watchdog timer (WDT )
 The 16-bit WDT module can be used in:
 Supervision mode:
- Ensure the correct working of the software application;
- Perform a PUC;
- Generate an interrupt request after the counter overflows.

 Interval timer:
- Independent interval timer to perform a “standard” interrupt upon
counter overflow periodically;
- Upper counter (WDTCNT) is not directly accessible by software;
- Control and the interval time selecting WDTCTL register;

39
 Digital I/O
Independently programmable
individual I/Os Port1
Port3
…
Port2 Port6

Function Select Register PxSEL yes yes

Interrupt Edge Select Register PxIES yes no

 Several ports Interrupt Enable Register PxIE yes no

Interrupt Flag Register PxIFG yes no

 Each has 8 I/O pins Direction Register PxDIR yes yes

Output Register PxOUT yes yes

 Each pin can be configured Input Register PxIN yes yes

as input or output P1.

P2.
 Some pins can be configured P3. 7 6 5 4 3 2 1 0

to assert an interrupt request P4.

P5.

P6.

40
 GPIO – General Purpose I/O

 Avoid floating inputs!!!

Use a pull-up/down resistor, GND, or internal programmable logic

To Input Logic
VCC Button
VCC Button
Button produces
either Vcc Port Pin
or Floating input. 5.6KΩ
5.6KΩ
Adding a pull-down
resistor fixes it.
Some ports have internal
programmable resistors

41
 GPIO - Inside Inputs/Outputs

 Each pin is independent

 Ports (out) and Pins (in) are
different!!!

Output section

Input section

42
Interfaces
 Several protocols for inter-chip communication
UART, I2C, SPI, USB,…

 Serial communication protocols

 Meant for short distances “inside the box”
 Low complexity
 Low cost
 Low speed ( a few Mbps at the fastest )
 Serial communication is employed where it is not practical,
either in physical or cost terms, to move data in parallel
between systems.

43
 I2C
 Shorthand for an “Inter-integrated circuit” bus
 I2C devices include EEPROMs, thermal sensors, and real-
time clocks
 Used as a control interface to signal processing devices that
have separate data interfaces, e.g. RF tuners, video decoders
and encoders, and audio processors.
 I2C bus has three speeds:
 Slow (under 100 Kbps)
 Fast (400 Kbps)
 High-speed (3.4 Mbps) – I2C v.2.0
 Limited to about 3 meters for moderate speeds

44
 I2C (Inter-Integrated Circuit) protocol
 Communications is always initiated and completed by
the master, which is responsible for generating the clock
signal;
 In more complex applications, I2C can operate in multi-
master mode;
 The slave selection by the master is made using the
seven-bit address of the target slave;
 The master (in transmit mode) sends:
 Start bit;
 7-bit address of the slave it wishes to communicate with;
 A single bit representing whether it wishes to write (0) to or
read (1) from the slave;
 The target slave will acknowledge its address.
45
 I2C Bus Configuration

 2-wire serial bus – Serial data (SDA) and Serial clock (SCL)
 Half-duplex, synchronous, multi-master bus
 No chip select or arbitration logic required
 Lines pulled high via resistors, pulled down via open-drain drivers
(wired-AND, avoid short
circuit among the bus)

46
I2C Features

 “Clock stretching” – when the slave (receiver) needs more time to

process a bit, it can pull SCL low. The master waits until the slave
has released SCL before sending the next bit.
 “General call” broadcast – addresses every device on the bus
 10-bit extended addressing for new designs. 7-bit addresses all
exhausted

Start Direction Data bits

Address bits Receiver Ack Stop

47
Example
I2C bridge

48
 Sensors data acquisition example
Realization with digital sensor:
 Data acquisition procedure:

49
 SPI
 Shorthand for “Serial Peripheral Interface”
 Defined by Motorola on the MC68HCxx line of
microcontrollers
 Generally faster than I2C, capable of several Mbps

Applications:
 Like I2C, used in EEPROM, Flash, and real time clocks
 Better suited for “data streams”, i.e. ADC converters
 Full duplex capability, i.e. communication between a codec and
digital signal processor

50
 Serial Peripheral Interface (SPI) protocol
 Supports only one master;
 Can support more than a slave;
 Short distance between devices, e.g. on a printed circuit
boards (PCBs);
 Special attention needs to be observed to the polarity and
phase of the clock signal;
 The master sends data on one edge of clock and reads
data on the other edge. Therefore, it can send/receive at
the same time.
51
SPI Bus Configuration

 Synchronous serial data link operating at full duplex

 Master/slave relationship
 2 data signals:
 MOSI – master data output, slave data input
 MISO – master data input, slave data output
 2 control signals:
 SCLK – clock
 /SS – slave select (no addressing)

52
SPI structure

 As the register transmits the byte to the slave on the

MOSI signal line, the slave transfers the contents of its
shift register back to the master on the MISO signal
line, exchanging the contents of the two shift registers.

53
 SPI vs. I2C

 For point-to-point, SPI is simple

and efficient
 Less overhead than I2C due to lack
of addressing, plus SPI is full
duplex.

SPI
 For multiple slaves, each slave
needs separate slave select signal
 SPI requires more effort and more
hardware than I2C

I2 C

54
 UART
 Shorthand for “Universal Asynchronous Receiver-Transmitter “
 A UART’s transmitter is essentially just a parallel-to-serial converter
with extra features.
 The UART bus is a full-duplex bus.
 The essence of the UART transmitter is a shift register that is loaded
in parallel, and then each bit is sequentially shifted out of the device
on each pulse of the serial clock.
 Application:
 Communication between microprocessors, pc
 Used to interface the microcontroller with others transmission bus as: RS232,
RS485, USB, CAN BUS, KNX, LonWorks ecc.
 Used to connect microntroller with modem and transceiver as: telephone
modem, Bluetooth, WIFi, GSM/GPRS/HDPSA

55
 UART
 Asynchronous serial devices, such as UARTs, do not share a common
clock
 Each device has its own, local clock.
 The devices must operate at exactly the same frequency.
 Logic (within the UART) is required to detect the phase of the
transmitted data and phase lock the receiver’s clock to this.
 Bitrate: 2400, 19200, 57600,115200, 921600…
 One of the problems associated with serial transmission is
reconstructing the data at the receiving end, because the clock is not
transmitted.
 Difficulties arise in detecting boundaries between bits.

56
 UART
 The transmission format uses:
 1 start bit at the beginning
 Settable 5,6,7,8 data bits string length
 Settable 1 or 0 even/odd parity bit control
 settable 1, 1.5, 2 stop bits end of each frame.

 Parity control
 The parity bit control is accordingly set to 0 or 1 to have and odd
number of frame 1 bits in odd parity either an even number of frame
1 bits in the even parity
 The control can detect 1 bit error in the frame
57
 UART transmission
UART can transmit either with 2 or 4 wires
 2 wires mode has transmit and receive  4 wires mode has transmit and receive
lines lines plus 2 handshake signals, RTS
request to send, CTS clear to send

UART UART
Tx FIFO Rx FIFO

Rx FIFO Tx FIFO

58
 Analog to Digital Converters
 Most engineering applications require some form of data processing:
measurement, control, calculation, communication or data recording;

 These operations, either grouped or isolated, are built into the measuring
instruments;

 The measuring equipment must maintain:

- Compatibility and communication between measuring devices;
- Acceptable error margin;
- Noise and interference immunity;
- Predictable measurement uncertainty;
- Suitable type of control (analogue/digital);
- Mathematical processing capacity;
- …

59
 Direct Memory Access

 Direct Memory Access (DMA) allows memory-to-memory or

peripheral-to-memory communication without the intervention of the
main CPU.
 The CPU initiates the data transfer and then can do other tasks or go in
stand-by
 The DMA controller handles the actual data stream and sends an interrupt
when done

60
 Direct Memory Access
 Concept of DMA: move functionality to peripherals
 Peripherals use less current than the CPU;
 Delegating control to peripherals allows the CPU to shut down (saves
power) or perform other tasks (increase processing capabilities);
 “Intelligent” peripherals are more capable, providing a better opportunity for
CPU shutoff;
 DMA can be enabled for repetitive data handling, increasing the throughput
of peripheral modules;
 Minimal software requirements and CPU cycles.

61
ARM Processors Families

62
STM32 ARM® CortexTM-M Family

63
 Embedded ARM Cortex Processors

 Cortex M0:
 Ultra low gate count (less
that 12 K gates).
 Ultra low-power (3
µW/MHz ).
 32-bit processor.

64
 Embedded ARM Cortex Processors (2)

 Cortex M1:
 The first ARM processor
designed specifically for
implementation in
FPGAs.
 Supports all major FPGA
vendors.
 Easy migration path from
FPGA to ASIC.

65
 Embedded ARM Cortex Processors (3)

 Cortex M3:
 The mainstream ARM
processor for
microcontroller
applications.
 High performance and
energy efficiency.

66
 Embedded ARM Cortex Processors (4)

 Cortex M4:
 The latest embedded
processor for DSP.

67
STM32 ARM® CortexTM-M Family

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 STM32L1x - Block Diagram

69 Presentation Title 14/ 69

 STM32L1x – Power profile
128 Kbytes Flash die 70
Typ current
VDD Range

340µA/MHz 105°C
25°C

 Wake up time

249µA/MHz1 12µA  Stop to Run: 8μs

Full speed (32MHz)
 Standby to run: 50μs
6.2µA
1
183µA/MHz
MSI clock (4.2MHz) 9 µA
2.7μA
1.4μA
4.4 µA 2
1.2µA 2
500nA
3 900nA
3
300nA
Dynamic Run Low-Power Run Low-Power Sleep Stop w/ RTC Standby
From Flash @ 32KHz + 1 timer @ 32KHz or w/o RTC

1/ Dhrystone power consumption value executed from Flash with VDD=3V

2/ Stop and standby with RTC given with VDD=1.8V
3/ Stop and standby without RTC given with VDD=3V
70
 STM32F4 – CORTEX M4
STM32F401 – 84 MHz, the
smallest, cost-effective
solution with outstanding
power efficiency
STM32F405/415 – 168 MHz
up to 1 Mbyte of Flash with
advanced connectivity and
encryption
STM32F407/417 – 168 MHz,
up to 1 Mbyte of Flash
adding Ethernet MAC and
camera interface
STM32F427/437 – 180 MHz,
up to 2 Mbytes of dual-bank
Flash with SDRAM interface,
Chrom-ART Accelerator™,
serial audio interface, more
performance and lower static
power consumption
STM32F429/439 – 180 MHz
CPU/225 DMIPS, up to 2
Mbytes of dual-bank flash
adding an LCD-TFT
controller

71
STM32F101 Product Lines

72
 STM32F10x Product Lines (2)
All lines include: Connectivity Line: STM32F107
Multiple communication peripherals Up to 256 KB 2x12-bit ADC Ethernet
72MHz USB 2.0 2 x Audio 2x PWM
Up to 5 x USART, 3xSPI, 2xI²C Flash / (1µs) IEEE158
CPU OTG (FS) Class I2S CAN timer
64KB SRAM TempSensor 8
ETM*
Connectivity Line: STM32F105
FSMC**
Up to 256 KB 2x12-bit ADC PWM
72MHz (1µs) USB 2.0 2 x Audio 2x
Dual 12-bit DAC*** Flash /
CPU OTG (FS) Class I2S CAN timer
64KB SRAM TempSensor

Multiple 16-bit Timers Performance Line: STM32F103

Up to 1MB 2/3x12-bit ADC PWM
Main Osc 4-16MHz (25MHz on 105/107) 72MHz
Flash / (1µs) USB–FS
SDIO* I2S* CAN
CPU Device timer
96KB SRAM TempSensor
Internal 8 MHz RC
and 40 kHz RC
USB Access Line: STM32F102
Real Time Clock with Battery 1x12-bit ADC
Up to 128KB
domain & 32KHz ext osc 48MHz
Flash / 16KB (1µs) USB–FS
CPU Device
SRAM Temp sensor
2 x Watchdogs

Reset circuitry and

Access Line: STM32F101
Brown Out Warning Up to 1MB 1x12-bit ADC
36MHz (1µs)
Flash / 80KB
CPU
Up to 12 DMA channels SRAM Temp sensor

* Performance/Access Lines 256KB Flash or more, Value Line: STM32F100

Value Line with 100+pins and ALL Connectivity
devices Up to 512KB 1x12-bit ADC PWM
24MHz (1.2µs) HDMI-
** Performance and Access and Value devices Flash / 32KB
CPU CEC timer
with 256KB Flash or more. SRAM Temp sensor
*** ALL Value line devices and
Performance/Access devices with 256KB Flash
or more
73
Development of the ARM Architecture
v4 v5 v6 v7
Halfword and Improved SIMD Instructions
Thumb-2
signed halfword interworking Multi-processing
/ byte support CLZ v6 Memory architecture
Architecture Profiles
Saturated arithmetic Unaligned data support
7-A -
System mode DSP MAC
Applications
instructions Extensions:
7-R - Real-
Thumb Thumb-2
time
instruction set Extensions: (6T2)
7-M -
(v4T) Jazelle TrustZone®
Microcontroller
(5TEJ) (6Z)
Multicore
(6K)
Thumb only
(6-M)

 Note that implementations of the same architecture can be different

 Cortex-A8 - architecture v7-A, with a 13-stage pipeline
 Cortex-A9 - architecture v7-A, with an 8-stage pipeline

74
Which architecture is my processor?

75
 Data Sizes and Instruction Sets
 ARM is a 32-bit load / store RISC architecture
 The only memory accesses allowed are loads and stores
 Most internal registers are 32 bits wide
 Most instructions execute in a single cycle

 When used in relation to ARM cores

 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)
 Doubleword means 64 bits (eight bytes)

 ARM cores implement two basic instruction sets

 ARM instruction set – instructions are all 32 bits long
 Thumb instruction set – instructions are a mix of 16 and 32 bits
 Thumb-2 technology added many extra 32- and 16-bit instructions to the original 16-
bit Thumb instruction set
 Depending on the core, may also implement other instruction sets
 VFP instruction set – 32 bit (vector) floating point instructions
 NEON instruction set – 32 bit SIMD instructions
 Jazelle-DBX - provides acceleration for Java VMs (with additional software support)
 Jazelle-RCT - provides support for interpreted languages
76
Datasheet example : system architecture

77
Datasheet example

78
Datasheet example: Timers

79
Datasheet example

80
Questions?

81