EXPERIMENT NO.

Simulation of All Types of Flip-Flops using VHDL and Xilinx ISE 14.7

AIM

To model, simulate, synthesize and implement different types of flip-flops (SR, JK, D and T)
using VHDL in Xilinx ISE 14.7 and verify their operation through simulation waveforms and
FPGA implementation.

SOFTWARE / HARDWARE REQUIRED

 Xilinx ISE Design Suite 14.7

 ISim Simulator
 FPGA Trainer Kit (Spartan-3 / Spartan-6)
 VHDL Language

THEORY

A flip-flop is a clock-controlled bistable multivibrator used to store one bit of binary data.
Flip-flops change their state only on the active edge of the clock signal and are the basic
building blocks of registers, counters and memory circuits.

1. SR FLIP-FLOP (SET–RESET FLIP-FLOP)

An SR (Set–Reset) Flip-Flop is a basic type of bistable sequential circuit used to store one
bit of binary information. It has two control inputs:

 S (Set) – used to set the output to logic ‘1’

 R (Reset) – used to reset the output to logic ‘0’

and two complementary outputs:

 Q – normal output
 – complement of Q

The output of an SR flip-flop changes only on the active edge of the clock signal (in edge-
triggered designs). Hence, it is a synchronous memory element.
Working Principle

The behavior of the SR flip-flop depends on the values of inputs S and R at the time of the
clock edge:

1. S = 0, R = 0 (No Change)
The flip-flop retains its previous state.

Qnext=QpresentQ_{next} = Q_{present}Qnext=Qpresent

2. S = 0, R = 1 (Reset Condition)
The output is reset to logic ‘0’.

Qnext=0Q_{next} = 0Qnext=0

3. S = 1, R = 0 (Set Condition)
The output is set to logic ‘1’.

Qnext=1Q_{next} = 1Qnext=1

4. S = 1, R = 1 (Invalid / Forbidden Condition)

This condition produces an undefined or indeterminate output because both set and
reset are activated simultaneously. Hence, this input combination is not allowed.

Truth Table of SR Flip-Flop

S R Q (Next State) Operation

0 0 Q (Previous) No Change
0 1 0 Reset
1 0 1 Set
1 1 X (Invalid) Forbidden

Characteristic Equation

The characteristic equation of an SR flip-flop is:

Qnext=S+R‾⋅Q

This equation shows how the next state depends on the present state and the inputs.
Advantages

 Simple and easy to design

 Requires fewer logic gates
 Basic building block for understanding other flip-flops

Disadvantages

 The condition S = 1 and R = 1 is invalid and may cause unpredictable output

 Not suitable for all practical applications due to this forbidden state

VHDL CODE – SR FLIP-FLOP (Spartan-6, Rising Edge Triggered)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity SR_FF is

Port ( S : in STD_LOGIC;

R : in STD_LOGIC;

CLK : in STD_LOGIC;

Q : out STD_LOGIC;

Qbar : out STD_LOGIC);

end SR_FF;

architecture Behavioral of SR_FF is

begin

process(CLK)

begin
 if rising_edge(CLK) then

if (S = '0' and R = '0') then

Q <= Q; -- No change

elsif (S = '0' and R = '1') then

Q <= '0'; -- Reset

elsif (S = '1' and R = '0') then

Q <= '1'; -- Set

else

Q <= 'X'; -- Invalid condition

end if;

end if;

end process;

Qbar <= not Q;

end Behavioral;

UCF CODE – SR FLIP-FLOP (Typical Spartan-6 Trainer Kit)

# Clock input (on-board oscillator or push button)

NET "CLK" LOC = "P56" | IOSTANDARD = LVCMOS33;

# SR Inputs (Switches)

NET "S" LOC = "P37" | IOSTANDARD = LVCMOS33;

NET "R" LOC = "P38" | IOSTANDARD = LVCMOS33;

# Outputs (LEDs)

NET "Q" LOC = "P80" | IOSTANDARD = LVCMOS33;

NET "Qbar" LOC = "P81" | IOSTANDARD = LVCMOS33;

IF YOU ARE USING A COMMON SPARTAN-6 BOARD (EXAMPLE: NEXYS-3)

# Clock (100 MHz onboard)

NET "CLK" LOC = "V10" | IOSTANDARD = LVCMOS33;

# Inputs (Switches)

NET "S" LOC = "T10" | IOSTANDARD = LVCMOS33;

NET "R" LOC = "T9" | IOSTANDARD = LVCMOS33;

# Outputs (LEDs)

NET "Q" LOC = "U16" | IOSTANDARD = LVCMOS33;

NET "Qbar" LOC = "V16" | IOSTANDARD = LVCMOS33;

Thus, the SR Flip-Flop was successfully modeled, simulated, synthesized and implemented
using VHDL and Xilinx ISE 14.7 on a Spartan-6 FPGA. The functional behavior of the
flip-flop was verified through simulation waveforms and hardware testing.

The output Q was observed to set, reset, hold or become invalid according to the input
combinations of S and R on the rising edge of the clock signal. The experimental results were
found to be in good agreement with the theoretical truth table of the SR flip-flop.

Hence, the objective of the experiment to study and implement the working of an SR flip-flop
using VHDL was successfully achieved.

2. JK FLIP-FLOP

A JK Flip-Flop is an improved version of the SR flip-flop in which the invalid condition is

eliminated. It has two inputs:
  J (Set input)
 K (Reset input)

and two outputs:

 Q and its complement

The JK flip-flop changes its state only on the active edge of the clock signal, making it a
synchronous sequential circuit.

Working Principle

The operation of the JK flip-flop depends on the values of J and K at the clock edge:

1. J = 0, K = 0 (No Change)
The output retains its previous state.
2. J = 0, K = 1 (Reset)
The output Q becomes 0.
3. J = 1, K = 0 (Set)
The output Q becomes 1.
4. J = 1, K = 1 (Toggle)
The output toggles to the complement of its previous state.

This toggling feature makes the JK flip-flop very useful in counters and frequency-divider
circuits.

Truth Table of JK Flip-Flop

J K Q (Next State) Operation

0 0 Q (Previous) No Change

0 1 0 Reset

1 0 1 Set

1 1 Q Toggle

Characteristic Equation

Qnext=JQ‾+K‾QQ
Advantages

 No invalid input condition

 Can perform set, reset, hold and toggle operations
 Widely used in counters and registers

Applications

 Binary counters
 Shift registers
 Frequency dividers
 Control circuits

VHDL CODE – JK FLIP-FLOP (Rising Edge Triggered)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity JK_FF is

Port ( J : in STD_LOGIC;

K : in STD_LOGIC;

CLK : in STD_LOGIC;

Q : out STD_LOGIC;

Qbar : out STD_LOGIC);

end JK_FF;

architecture Behavioral of JK_FF is

begin

process(CLK)
 begin

if rising_edge(CLK) then

if (J = '0' and K = '0') then

Q <= Q; -- No change

elsif (J = '0' and K = '1') then

Q <= '0'; -- Reset

elsif (J = '1' and K = '0') then

Q <= '1'; -- Set

else

Q <= not Q; -- Toggle

end if;

end if;

end process;

Qbar <= not Q;

end Behavioral;

UCF FILE – JK FLIP-FLOP (SPARTAN-6, XILINX ISE 14.7)

Generic Spartan-6 UCF Example

# Clock input
NET "CLK" LOC = "P56" | IOSTANDARD = LVCMOS33;

# Inputs (Switches)

NET "J" LOC = "P35" | IOSTANDARD = LVCMOS33;

NET "K" LOC = "P36" | IOSTANDARD = LVCMOS33;

# Outputs (LEDs)

NET "Q" LOC = "P80" | IOSTANDARD = LVCMOS33;

NET "Qbar" LOC = "P81" | IOSTANDARD = LVCMOS33;

Example for Nexys-3 (Spartan-6 Board)

# Clock (on-board oscillator)

NET "CLK" LOC = "V10" | IOSTANDARD = LVCMOS33;

# Inputs (Switches)

NET "J" LOC = "T10" | IOSTANDARD = LVCMOS33;

NET "K" LOC = "T9" | IOSTANDARD = LVCMOS33;

# Outputs (LEDs)

NET "Q" LOC = "U16" | IOSTANDARD = LVCMOS33;

NET "Qbar" LOC = "V16" | IOSTANDARD = LVCMOS33;

The JK Flip-Flop was successfully modeled, simulated and implemented using VHDL and
Xilinx ISE 14.7. The observed results matched the theoretical truth table, thus verifying the
correct operation of the JK flip-flop.

Hence, the working of the JK Flip-Flop was studied and verified successfully using VHDL
on a Spartan-6 FPGA. The objectives of the experiment were achieved.

[Link] – D FLIP-FLOP
 A D Flip-Flop (Data or Delay Flip-Flop) is a fundamental sequential circuit used to
store one bit of data. It has a single data input D, a clock input CLK, and two outputs Q
and its complement .

The D flip-flop transfers the value present at the D input to the output Q only at the
active edge of the clock (rising edge in this experiment). Between clock edges, the output
remains unchanged, making it a reliable memory element.

Working Principle

 At the moment of the rising clock edge, the input D is sampled.

 The output Q becomes equal to the value of D.
 Until the next clock edge, the output holds its previous value, irrespective of changes
in D.

Truth Table of D Flip-Flop

D Q (Next State) Operation

0 0 Reset

1 1 Set

Characteristic Equation

Qnext=D

Advantages

 Simple structure and easy implementation

 No invalid input condition
 Widely used in registers, counters and memory circuits

Applications

 Data storage and registers

 Shift registers
 Synchronization circuits
 Pipeline registers in processors
VHDL CODE – D FLIP-FLOP (Rising Edge Triggered)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity D_FF is

Port ( D : in STD_LOGIC;

CLK : in STD_LOGIC;

Q : out STD_LOGIC;

Qbar : out STD_LOGIC);

end D_FF;

architecture Behavioral of D_FF is

begin

process(CLK)

begin

if rising_edge(CLK) then

Q <= D; -- Output follows input D at clock edge

end if;

end process;

Qbar <= not Q;

end Behavioral;

SAMPLE UCF FILE – D FLIP-FLOP (SPARTAN-6, XILINX ISE 14.7)

Generic Spartan-6 UCF Example

# Clock input

NET "CLK" LOC = "P56" | IOSTANDARD = LVCMOS33;

# Data input (Switch)

NET "D" LOC = "P34" | IOSTANDARD = LVCMOS33;

# Outputs (LEDs)

NET "Q" LOC = "P80" | IOSTANDARD = LVCMOS33;

NET "Qbar" LOC = "P81" | IOSTANDARD = LVCMOS33;

Example for Nexys-3 (Spartan-6 Board)

# Clock (100 MHz onboard oscillator)

NET "CLK" LOC = "V10" | IOSTANDARD = LVCMOS33;

# Data input (Switch)

NET "D" LOC = "T10" | IOSTANDARD = LVCMOS33;

# Outputs (LEDs)

NET "Q" LOC = "U16" | IOSTANDARD = LVCMOS33;

NET "Qbar" LOC = "V16" | IOSTANDARD = LVCMOS33;

The D Flip-Flop was successfully modeled, simulated and implemented using VHDL and
Xilinx ISE 14.7. The obtained results matched the theoretical operation of the D flip-flop.

Thus, the working of the D Flip-Flop was studied and verified using VHDL on a Spartan-6
FPGA, and the objective of the experiment was successfully achieved.

5. THEORY – T FLIP-FLOP
A T (Toggle) Flip-Flop is a type of bistable sequential circuit used mainly in counters and
frequency divider applications. It has a single input T (Toggle), a clock input CLK, and two
outputs Q and its complement .

The T flip-flop changes its output state only on the active edge of the clock signal. Its
operation depends on the value of the T input:

 When T = 0, the flip-flop holds its previous state (no change).

 When T = 1, the flip-flop toggles its output, i.e., Q becomes the complement of its
previous value.

Thus, the T flip-flop can perform the toggle operation and is widely used in designing binary
counters.

Working Principle

 At every rising edge of the clock, the value of T is checked.

 If T = 0, the output Q remains unchanged.
 If T = 1 the output Q toggles Q Q.

Truth Table of T Flip-Flop

T Q (Next State) Operation

0 Q (Previous) No Change
1 Q Toggle

Characteristic Equation

Qnext=T⊕Q

(where ⊕ represents Exclusive-OR operation)

Advantages

 Simple design and easy implementation

 Useful for toggle and counting operations
 No invalid input condition
Applications

 Binary counters
 Frequency dividers
 Control circuits
 Timing circuits

VHDL CODE – T FLIP-FLOP (Rising Edge Triggered)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity T_FF is

Port ( T : in STD_LOGIC;

CLK : in STD_LOGIC;

Q : out STD_LOGIC;

Qbar : out STD_LOGIC);

end T_FF;

architecture Behavioral of T_FF is

begin

process(CLK)

begin

if rising_edge(CLK) then

if T = '1' then

Q <= not Q; -- Toggle

 else

Q <= Q; -- No change

end if;

end if;

end process;

Qbar <= not Q;

end Behavioral;

SAMPLE UCF FILE – T FLIP-FLOP (SPARTAN-6, XILINX ISE 14.7)

Generic Spartan-6 UCF Example

# Clock input

NET "CLK" LOC = "P56" | IOSTANDARD = LVCMOS33;

# Toggle input (Switch)

NET "T" LOC = "P39" | IOSTANDARD = LVCMOS33;

# Outputs (LEDs)

NET "Q" LOC = "P80" | IOSTANDARD = LVCMOS33;

NET "Qbar" LOC = "P81" | IOSTANDARD = LVCMOS33;

Example for Nexys-3 (Spartan-6 Board)

# Clock (100 MHz onboard oscillator)

NET "CLK" LOC = "V10" | IOSTANDARD = LVCMOS33;

# Toggle input (Switch)

NET "T" LOC = "T10" | IOSTANDARD = LVCMOS33;

# Outputs (LEDs)

NET "Q" LOC = "U16" | IOSTANDARD = LVCMOS33;

NET "Qbar" LOC = "V16" | IOSTANDARD = LVCMOS33;

The T Flip-Flop was successfully modeled, simulated and implemented using VHDL and
Xilinx ISE 14.7. The experimental results matched the theoretical truth table, thus verifying
the correct operation of the T flip-flop.

Hence, the working of the T Flip-Flop was studied and verified using VHDL on a Spartan-6
FPGA. The objective of the experiment was successfully achieved.

Conclusion-

Thus, the working of different types of flip-flops namely SR, JK, D and T flip-flops was
successfully studied, modeled, simulated and implemented using VHDL and Xilinx ISE
14.7 on a Spartan-6 FPGA.

The functional behavior of each flip-flop was verified through simulation waveforms and
hardware testing. The SR flip-flop exhibited set, reset and hold operations, the JK flip-flop
performed set, reset, hold and toggle operations without any invalid condition, the D flip-flop
correctly transferred the input data to the output on every rising edge of the clock, and the T
flip-flop toggled its output when the toggle input was high.