3.

10
INSTRUCTION CYCLE computer to perform:aspecified
3.2 a command given to the programmer
An instruction is a
a particular task writes
given data. To
perform data are stored a
a program. Program and in the mernoryher
instructions, called memory ata time and executes it.
one instruction from the to the final result.
fetches
a program
one by one to produce
of
instructions out to fetch an instruction
necessary steps that a CPU carries ann instruction
The
memory, and to execute it, constitute cycle.
data from the execute cycle, In fetch cycle a CPU Aninsi
cycle and fetches
cycle consists of fetch
a
memory. The necessary op
code of an instruction) from the steps
machine memory, constitute a fetchcycle. wi
an opcode from the
carried out to fetch
out to get data, if any, from the memory and
The
ne
steps which are carried to
an instruction, constitute an execute perton
specific operation specified in a fixed slot of time while
cycle.
an opcode (FC) is the ime The
required to fetch which depends on requi
execute an instruction (EC) is variable thetype ofb instrucian
executed. The total time required to execute an instruction is given
IC = FC+ EC

3.2.1 Fetch Operation

An instruction may be more
The 1st byte of an instruction is its opcode, than ne
are data or operand address. Thee program counter
long. The other bytes (PC)ke
memory address of the next instruction to be executed..n the beginningof afet
the content the
of program counter, which is the address of
the memory locationy
sent to the memory. The memory places
opcode is available, is the opcodeontte
bus so as to transfer it to the CPU, The entire operation offetching an opcode hl
clock cycles. A slow memory may take more time. In case of a slow memorv h
has to wait tillthememory sends the opcode. The clock cycle for which the CP
called wait cycle. Most of the CPUs have been designed to introduce wait cylest
with slow memories.
3.2.2 Execute Operation
The opcode fetched from the memory goes to the data register, DR (data a

buffer in Intel 8085) and then to instruction register, IR. From the instruction re
goes to the decoder circuitry which decodes
the instruction. The decoder cia
within the microprocessor. After the instruction is decoded, execution begis
operand is in the general purpose registers, execution is immediately pertoT
time taken in decoding and execution is one
or
clock cycle. If an instruction conu
operand address which are still memory,the CPU has to perform
so

operations to get the desired

in the
data. After receiving performs
operation. A read cycle the data it

is similarto a fetch cycle. case of a

read cycle the
In
INSTRUCTION CYCLE

FETCH CYCLE EXECUTE

CYCLE

CLOCK

EC
<br>

MICROPROCESSOR ARCHTECTUNE
211
roeived from the memory are data or operand
instructions write operation is performed,In address instead are
of an opcode. In sOme
write cvele data sent
the memory an output
[Link], we see that in sone cases an from the CPU to
or

involve one or more read or write cvcles or execute cycle may

iinstruction and etch cycle respectively. both Figures. 34 and 35 shWs ar

GET OPOOOE FROM

MEMOrY
MEMORY GETS
CLOCK
SEND ADORESS
OPCODE FROM TRANSFEP
TO MEMORY OPCODE TO P
MEMORY LOCATON

TIME

Fig. 3.5 Fetch Cycie

3.2.3 Machine Cycle and State
The necessary steps carried out to perform the operation
of accessing either mermory or
I/O device, constitute a machine cycle. In other words necessary steps out to
perform a fetch, a read or a write operation constitute a Machine cycle. carried
necessary
steps include to send mnemory or The
I/0 address; IO/M, ALE, RD(or WR) etc signals.
In a machine cycle one basic operation such as opcode fetch, memory
e memory
write, I/0 read or I/O write is performed. An instruction cycle consists read,
of
several machine cycles. The opcode of an instruction is fetched in the first mmachine
cycle of an instruction cycle. Most of the single-byte instructions
require oniy one
machine cycle to fetch the opcode and execute the instruction. Two-byte and three-byte
instructions require more than one mnachine cycle. Additional machine cycles are
needed to read data from or to write data into the memory or I/O devices. Figures 3.6
shows instruction cycle for MVI r, data. It has two machine cycles: one for fetching
opcode, and the other for reading data from the memory and to execute the instruction.
INSTRUCTION CYCLE NEXT
INSTRUCTION
CYCLE
CLOCK M, (OPCODE FETCH) M(READ DATA
& EXECUTE)
T T
T

Fig. 3.6 Typical Instruction Cycle

One subdivision of an operation performed in one clock cycle is called a state or
T-state. The subdivisions are internal states synchronised with the system clock. So,
one clock cycle of the system clock is referred to as a state.
3.2.4 Instruction and Data Flow
A computer receives instructions and data both in binary fornm. A group of 8 bits is
called a byte. Data and instructions for computers are specified in the byte form. The
word length of a computer is the number of bits it handles at a time. The word lengthof
an 8-bit microprocessor is of one byte, that of a l6-bit microprocessor is of two bytes
and so on. Two kinds of words, namely instruction word (instruction code or opcode)
and data word are processed during an instruction cycle. In the beginning of a fetch
cycle the content of the program counter is transferred to a special register known as
 3.12 FUNDAMENTALS OF MICROPROCESSORS ANO
MICOCOT
memory address register, MAR or simply address register, AR;(address
8085). The content of MAR is transferred to the memory through buter
the addrer
sending certain control signals to the memory the microprocessor also indicate
wants to read the content of the memory. The decoder circuitry in
activated and the memory understands what is to be done. Then the the metts
opcode to the microprocessor through the data bus. The opcode firrstcomes
data register(MDR) or simply data register (DR) as shown in Fig. 3.7 in
incaseek
INSTRUCTION MDR MEMORY
REGISTER DATA BUS

CPU
INSTRUCTION
DECODER
PROGRAM MEMORY
MAR ADDRESs
CONTROL COUNTER
BUS

Fig. 3.7 Flow of instruction word (opcode)

8085,there is a data buffer for this purpose. The operation code is then placed
instruction register (IR). The instruction is decoded by instruction decoder
and
executed. Finally, the content of the program counter is incremented. t
The execution of an instruction requires the flow of data word in the mos te
instructions. The flow of a data word is shown in Fig. 3.8. A data word is received et
from the memory or input device. The data word flows to
data bus and is placed in the accumulator or any the processor throught
other general purpose regi
depending upon the instruction. After the execution of an instruction the data is pae
in a register or a memory location. After the execution of a program the result (data
placed in the memory or sent to an output device. When a
memory, it is also held in MDR (or DR or data word is written into
Data Buffer) until the write operatian
complete.

INTERNAL DATA BUS

TEMPORARY
REGISTER ACCUMULATOR
DR

GENERAL PURPOSE
REGISTERS TO
DATA BUS
ALU MEMORY
<br>

MICROPROCESSOR ARCHITECTURE 3.13

3.3 TIMING DIAGRAM

The necessary steps which are carried out in a machine cycle can be represented
graphically. Such a graphical representation is called timing diagram. The timning
diagram for opcode fetch, memory read, memory Write, I/O read andI/Owrite will be
discussed below.
3.3.1 Timing Diagram for Opcode Fetch Cycle
In a fetch cycle the microprocessor fetches the opcode of an instruction from the
memory. Figures 3.9 shows the timing diagram for an opcode fetch cycle. T,T2, T3, and
T, are consecutive four clock cycles. The microprocessor issues a low IO/M signal to
indicate that it wants to make communication with the memory. Again the micro
processor sends out high So and S signals to indicate that it is going to perform fetch
operation.
During the first clock cycle, T, the microprocessor sends out the address of the
memory location where the opcode is available. The 16-bit memory address is sent
through the address bus A and address/ data bus AD. The 8 MSBs of the memnory
address are sent over the A bus, and 8 LSB of the memory address over AD bus. Since,
the AD bus is needed to transfer data during subsequent clock cycles, it is used in
time-multiplexed mode. Therefore, it has to be made available to carry data during I2
and T4. To accomplish this the microprocessor sends an address latch enable singal
ALE to latch the 8 LSB of the memory address either in the memory or an external
latch so that the complete 16-bit memory address may be available in the subsequent
clock cycles. 16-bit memory address is needed by the memory to obtain the opcode
from the given memory address. During T,,AD bus becomes ready to carry data. In T,
the microprocessor makes RD low. Now, memnory gets the opcode from the specified
memory location and places it on the data bus. During T,, the opcode is placed in the
instruction register, IR which is within the micröprocessor. The memory is disabled
M

SIGNAL Tg T
CLK

IOM

S, So

Ag-A15 TX PCH

OUT IN

|ADG-ÁD PCL Do-D, (OPcODE)

ALE

RD

Fig. 3.9 Timing Diagram for Opcode Fetch Operation

 when RiD goes high during T. The fetch cycle is completed
by
decoded in T,. The microprocessor examines READY signal
in lfit T.
T.
microprocessor enters into T, state. If it is low, the microprocessorinserts is
in between T, and T, a
If an instruction is one byte long, only one machine cyycle as
shown
required to fetch and execute the instruction. Examples of one byte in Fig:
are MOV, SUB, ADD, RAL, etc. As the operands are in the \ong
general purposeinsty
the decoding ofthe operation code andits execution takes only one cdock te
instruction is two or three bytes long, it requires more machine
machine cycle M, is for fetching the opcode from the memory. Subsequent cycles.
Te
cycles M, M3 etc. are required eitherto read data or address from the memory
or to write data
into the memory or I/O devices. Figure 3.10shows thetiming orl/0
two byte instruction MVIr, data. The first machine cycle shows fetch cycde, ciagpn
M

and
read cyce.
M

CLK

1O/M

So
S, So

Ag-A15
PC (MSBs) OF ADDRESS (PC+1)H

OUT IN OUT IN

ADy-AD, PCL OPCODE (PC+1)DATA

LSBs OF
ADDRESS
ALE

RD

OPCODE FETCH CYCLE READ CYCLE

Fig.3.10 Timing Diagram for MVI r, Data

3.3.2 Memory Read

rlocatis
In a memory read cycle the microprocessor memory
reads the content of a CPUN
content isthen placed either in the
the accumulator any other register ft
or of
let us take an example of two byte long instruction.
MVIA, 05
In thecoded form it is written as
3E, 05
where 3E is opcode for MVI A instruction
This instruction requires
and 05 is data. machie

two machine cycles, M and M,. Thediagramfirsti for

is to fetch the operation code 3E from
M

fetch operation has already been the memory. The timing

shown in Fig. 3.9. The: second machine
Imemorrre
readingthe data (05) from memory
IO/M goes the as a
shown in Fig..3.11. It is are:
<br>

MICROPROCESSOR ARCHITECTURE
3.15

SIGNAL T T2 Ta

CLK
SIGNAL
T2 T3

10M CLK

So IO/M

A-A15 PCH So

OUT IN
AgrAysX
AD,-AD, PCL DATA

AD,AD;XAoa Do-D,

ALE ALE

RD WR

Fig. 3.11 Timing Diagram for Memory Read Fig. 3.12 Timing Diagram for Memory Write
Operation Operation

respectively for read operation, see Table 3.1. On the address lines Ag -A15, the 8
MSBs of the memory address of the data (05) are sent. During T, 8 LSBs of the memory
address of the data are sent on ADo -AD¬. During T,8 LSBs of the address is latched
RD goes low in T, to enable the
and ADo -AD, are made free for data transmission.
memory for read operation. Now, data is placed on data bus. During T, the data enters
into the CPU. In T3, RDgoes high and disables the
memory. For MVI A, 05 instruction
the data enters into the accumulator. The timing diagram for
an opcode fetch cycle and
a memory read cycle are same except the status signals S, and So. MR cycle consists of
only three clock cycles.
Now, consider a three byte long instruction, for example; LXI H, 2500H. This
memory
instruction requires three maehine cycles, one fetch cycle and two consecutive
to
read cycles. The 1st machine cycle is to fetch the opcode, the 2nd machine cycle read
8
LSBs of the 16-bit data (2500), and the 3rd machine cycle to read 8 MSBs of the 16-bit
data (2500). The instruction LDA2400H requires four machine cycles. The 1st machine
cycle is to fetch the operation code, the 2nd machine cycle for reading the 8LSBs of the
memory address (2400H), the third machine cycle for reading 8 MSBs of the memory
address. In the fourth machine cycle the microprocessor sends the memory address
2400H toget its content into the accumulator.
3.3.3 VO Read
In an I/O read cycle the microprocessor reads the data available at an input port or
input device. The data is placed in the accumulator. An I/0 read cycle is similar to
memory read cycle. The only differernce between a memory ready cycie and I/O read
cycle is that signal IO/M goes high in case of I/Oread. It indicates that the address
on
the A-bus is for an input device. In timing diagram all other signals will remain same as
 3.16

shown in Fig. 3.11. n case of I/O device orlI/O portonthe address is onlw 8s.
therefore, the address of I/O device is duplicated both and ADbuses,)
A A

The IN instruction is used for I/O read. It is two byte long. It requires
machine cycles for execution. The first machine cycle is opcode fetch cycle, s
device (or the
machine cycle is a memory read cycle to read the input input port)
and the third machine cycle is I/Oread cycle read the data fromthe device
to
orpn
3.3.4 Memory Write
In memory write cycle the CPU sends data from the accumulator: or any other
a
tep
to the memory. The timing diagram fora memory write cycle is showniin Fig-312
status signals S and S are 1 and respectively for write operation. WR goesloW
O

indicating that the write operation is to be performed. During T, the AD-busis

disabled as it is done in case of memory
or But
I/Oread operation.
as
the data tobee
out to the memory is placed on the AD-bus. As soon WR goes high in T the
A; STA
M, 2500H etc. use mem
operation is terminated. The instructions MOV
write cycle.
3.3.5 VO Write
In an I/O write cycle the CPUsends data to an I/0 port or I/0 device from
accumulator. An I/O write cycle is similar to a memory write cycle. In case ofl/0
cycle IO/M goes high indicating that the address sent out by the CPU is for l/0 &e

or I/O port. The address of an I/O port or device is duplicated on both A and ADi
The OUT instruction is used for I/Owrite. It is a two byte long instruction. It
reçu

three machine cycles. The first machine cycle is for opcode fetch operation, the setn
machine cycle is a memory read cycle for reading the I/0 device address fromá
memory and the third machine cycle is an I/O write cycle for sending data to thel,
device.
PROBLEMS
1. What are the various registers of 8085? Discuss their function.
2. Discuss the function of ALUof 8085.
3. What are various status flags provided in 8085? Discuss their roles.
4. Discuss the function of the following signals of 8085:
IO/M, INTR, INTA, HOLD, HLDA and READY.
5. Discuss the function of the following signals of 8085:
RD, WR, ALE,
S and S1.
6. Discuss instruction cycle, machine cycle and state.
7. Discuss fetch operation and execute operation.
8. Draw and explain the timing diagram for fetch operation.
9. Draw and explain the timing diagram for memory read operation.
10. Draw and explain the timing diagram of memory write operation.
data.
11. Draw and explain the
timing diagram for the instruction MVIr,
12. Draw and explain the timing diagram for
13. Draw and explain the timing diagram for
I/0 read operation.
14. How many machine cycles are
I/0 write operation.
instructions of
Intels

required by the following

Justify your answers. add:
MOV r,r; MVIr, data; MOV r, M; LXI rp, data; and
LDA addr; status
IN

15. Explain the requirement a program

of counter, stack pointer and
architecture of
<br>

HAPIER 7
PERIPHERAL DEVICES
AND INTERFACING
INTRODUCTION
7.1
microprocessor combined with memory and devices, forms
a
A

microcomputer. The microprocessor input/output

is the heart of a
microcomputer. Memories and
input/output devices are interfaced to microprocessor to form a
microcomputer. In
ee of large and minicomputers the memories and input/output devices are
eherfaced to CPUby the manufacturer. In a microprocessor-based system
the designer
e to select suitable memories and input/output devices for his task and
interface
them to the microprocessor. The selected memories and input/output devices should
be compatible with microprocessor. If a particular device is not compatible, an
additional electronic circuit has to be designed through which the device may be
interfaced to the CPU.

72 ADDRESS SPACE PARTITIONING

The Intel 8085 uses a 16-bit wide address bus for addressing memories and
I/0
64 K bytes of memory and
devices. Using 16-bit wide address bus it can access 2
I/Odevices. The 64 K addresses are to be assigned to memories and I/O devices for
their addressing. There are two schemes for the allocation of addresses to memories
and input/output devices:
1. Memory mapped I/O scheme
2 I/0 Mapped I/O scheme
72.1 Memory Mapped VO Scheme
In memory mapped
I/0 scheme there is only one address space. Address space is
defined as the set of all possible addresses that a microprocessor can generate. Some
addresses are assigned to memories and some addresses to I/O
devices. An I/O device
is also treated as a memory location and one address is assigned to it. Suppose that
memory locations are assigned the addresses 2000 to 24FF. One address is assigned to
each memory location. Any one of these addresses cannot be assigned to an I/O device.
The addresses for
assigned
I/o devices are different from the addresses which have been
to memories. The addresses which have not been assigned to memories
can be assigned to
I/O devices. For example, 2500, 2501, 2502 etc. may be assigned to
VO devices. One address is assigned to each I/O device.
In this scheme all the data transfer instructions of the microprocessor can be used
for both memory as well as
I/O devices. For example, MOVA, M will be valid for data
nster from the mnermory location or I/O device whose address is in H-L pair. If the
HL pair contains the address of memory location, data will be transferred from the
a
hemory location to the accumulator. If the H-L pair contains the address of an I/O
evice, data will be moved from the I/0 device to the accumulator. The memory
Pped I/O scheme is suitable for a small system.
<br>

7.2 FUNDAMENTALS OF
MICROPROCESSORS ANDI MICROCOTHOLE

7.2.2 VO Mapped VO Scheme

In this scheme the addresses assigned to memory locations can also be assigred
devices. Since, the same address may be assigned to a memory location
device, the microprocessor must issue a signal to distinguish whether the ot an L/
address
the address bus is for a memory location or an I/O device. The Intel 8085issues
IO/Msignal for this purpose. When this signal is high the address on the:address
for an 1/o device. this signal is low, the address on the address bus busis
When
memory location. Two extra instructions IN and OUT are used to address isfot
I/O devices
The IN instruction is used to read to data of an input device. The OUT instruction
used to send data to an output device. This scheme is suitable for. alarge system.

7.3 MEMORY AND VO INTERFACING

Several memory chips and I/0 devices are connected to a microprocessor. Figure
71
shows a schematic diagram to interface memory chips or I/0devices to a micro-

MEMORY VO DEVICE

ADDRESS BUS

DATA BUS

CONTROL BUS

Fig. 7.1 Schematic Diagram for Memory and /O lnterfacing

processor. An address decoding circuit is employed to select the required I/O devie r
amemory chip. Figure 7.2 shows a schematic diagram of a decoding circuit. IFIO/MS
high the decoder 2 is activated and the required I/O device is selected. If IO/Mis loN
thedecoder 1 is ativated and the required memory chip is selected. A few MSBs of te
address lines are applied to the decoder to select a memory chip or an I/O device.
7.3.1 Memory Interfacing
The address of a memory location or an I/O device is sent out by the microproces
[Link]
The corresponding memory chip or I/0 device is selected by a decoding PLA
PROM or
decoding task can be performed by a decoder, a Comparator, a bipolar
a to 8 lines
(Programmed logic array). In this section the application of 74LS138, l
decoder willbe illustrated. Figure 7.3 shows the interface of memory chips tuh be high
74LS138. G1, G2A and G2B are enable signals. To enable 74LS138, G1 should
logi
C are
1proper
and G2A and G2B should below. A, and B
select lines. By applying lines. An
8outputTableZ1
to select lines any one of the outputs can be selected. Yo, Y,...Y, are
output lines goes low when it is selected. Other output lines remain high. high,al
.
G2Bis
showsthe truth table for 74LS138. When G1 is low or G2A is high oor
<br>

PERIPHERAL DEVICES ANDINTERFACING

MEMORY
PROM
CHIP SELECT
Y
SIGNALs PROM

RAM
Y
DECODER-1 RAM

RAM

RAM
IOM ENABLE UNUSED
RESERVED
FOR FUTURE

Yo
ENABLE NPUT DEVICE
Y.
INPUT DEVICE

OUTPUT DEVICE

OUTPUT DEVICE
DECODER-2 Y
UNUSED
VO DEVICE RESERVED
SELECT FOR FUTURE
SIGNALS

Fig.7.2 Interfacing of Memory and VO Devices

output lines become high. Thus, 74LS138 acts as decoder only when G1 is high, and
G2A and G2B are low.
The memory locations for EPROM1 will lie in the range 0000 to 1FFF. These
are the
memory locations for ZONE 0 for the memory chip which is connected to the output
7 E000 to
line Y, of the decoder. Similarly, for ZONE is 2000 to 3FFF and for ZONE is
1

FFFF. Table 7.2 shows the memory locations for various

zones.

Table 7.1 Truth table for 74LS138

INPUTS OUTPUTS
ENABLE SELECT
G1 <x
A Yo Y2 Ys Y4 Ys Ys
G2A G2B B
X H H X X X H I
H I
H H II H I

H H H H H H
X X X X X I I I

L H H H H I I
H I
I

H I
H H I H IH H H
H H I H L H H IH H IH
I
H L H H
H IH I I I I

H
L I
I

L H I
H L II I I
H
II H H H
H L
I
H IH I I

H H I
H
H L H I
H
IIH H H H
H H H H I
H H I
I

XDenotes
irrelevant
<br>

FUNDAMENTALS OF MICROPROCESSORS
SAND MICROCONTROAL
7.4

Ays
EPROM 1

Y614 EPROM 2
A2
13
Ag RAM 1

12
RAM 2

11
6 RAM 3
5V
74LS138
10
5 RAM 4
IOM

G24 RAM 5

RAM 6

16 G
Vcc

GND

Fig. 7.3 Interfacingg of Memory Chips using 74LS138

Table 7.2 Memory Locations for Various Zones

Decoder Output Memory Device Zones ofthe Address SpaceMemory Locations Address

Yo EPROM 1
ZONE O 0000 to 1FFF
EPROM2 ZONE 1
2000 to 3FFF
Y2 RAM 1 ZONE 2 4000 to 5FFF
RAM 2 ZONE 3 6000 to 7FFF
RAM 3 ZONE 4 8000 to 9FFF
RAM 4 ZONE 5 A000 to BFFF
Y6 RAM 5 ZONE 6 CO00 to DFFF
RAM 6 7 E000 to FFFF
Y7 ZONE

The entire memory address (64K for 8085) has been divided into 8 zones. Adtre
of the 74LSI
lines A15, A14 and Aj3 have been applied to the select lines A. Band C EPROM or a
The logic applied to these lines selects a particular memory device, an
..
RAM. Other address lines A, Aj,A, and Aj go directly to memory hi
decide the address of the memory location within a selected memory chipG2Bgoes
connected to G2B. When IO/M goes low for memory read/write operation,
low. G1 is connected to + 5 Vac. Supply and G2A is grounded.
7.3.2 VO Interfacing addes
the
Figure 74 shows the interface I/O devices through decoder 7474LS138. As for I/O
of
of an
used
I/O device is of 8 bits, only Ag -A1s lines of address bus areselectlines
addressing. The address lines Ag, Ag and A10 have been applied to aa
NAN

and C of through
the 74LS138. The address lines A1 -A1s are appliedlto G2B high. G24
gate. G2B becomes low only when all address lines A writ
-Ajs are read/
grounded. IO/M is connected to G1. When IO/M goes high tor I/0Connectet
operation, Gl goes high. Table 7.3 shows the addresses of devices
74LS138.
I/0
 Ae
- INPUT DEVICE 1

INPUT DEVICE 2

INPUT DEVICE 3
As
A4 12
5
lyw OUTPUT DEVICE 1
Ays
G28
Y OUTPUT DEVICE 2
A2
74LS138 10
At Ys
b OUTPUT DEVICE 3

G2A
UNUSED
FOR FUTURE
7 EXPANTION

IO G,
k
16 Vcc
8
GND

Fig.7.4 Interfacing of VO Devices Using 74LS138.

Table 7.3 Address of VO Devices connected to 74LS138

A14 A13 A12 A11 A0 Ag Ag Selected Corresponding
Output Lines Address Device
1 Yo F8 Input Device 1
1
F9 Input Device 2
FA Input Device 3
1
Output Device
FC Output Device
Y5 Output Device
Y6 FE Unused
1 1
0
1 1 Y7 FF Unused
1 1
1