Physical Design in VLSI
Interview Questions and Answers
A Comprehensive Guide for VLSI Professionals
Understanding Physical Design Fundamentals
1 What is Physical Design in VLSI?
Process of transforming a synthesized netlist into a manufacturable geometric layout. Includes floorplanning, placement,
clock tree synthesis, routing, and verification tasks.
2 What are the major steps in the physical design flow?
Floorplanning (macro and cell placement) • Placement (optimizing timing) • Clock Tree Synthesis (establishing low-skew
clock distribution) • Routing (connecting cells via metal layers) • Verification (STA, DRC, LVS)
3 Explain the purpose of floorplanning
Defines key areas of chip layout, allocating space for macros, I/O cells, and standard cells, aiming to minimize wirelength,
congestion, and optimize power distribution
Understanding Physical Design Fundamentals
4 What is placement and what factors affect it?
Locating standard cells and macros based on timing, congestion, and power considerations, using algorithms to achieve
high-quality results while obeying design constraints
5 Why is Clock Tree Synthesis critical?
Balances clock distribution across all sequential elements, minimizing skew and insertion delay to prevent timing
violations and promote stable chip operation
6 What is routing, and how is it classified?
Connects cells through metal layers. Divided into global routing (determining overall paths) and detailed routing
(allocating exact tracks, layers, and vias)
Understanding Physical Design Fundamentals
7 What is the difference between global and detailed routing?
Global routing establishes approximate paths focusing on congestion and wirelength, while detailed routing assigns
specific tracks and handles via creation, adhering to DRC rules
8 Explain GDSII generation in physical design
Final chip layout exported in GDSII format, a database representation used for photomask creation and foundry
manufacturing
9 Why is power planning required in VLSI design?
Ensures adequate power distribution via metal stripes and grids, aiming to prevent IR drop, electromigration, and ground
bounce issues
Understanding Physical Design Fundamentals
10 List common physical verification checks
LVS (Layout Versus Schematic) • DRC (Design Rule Checks) • ERC (Electrical Rule Checks) • LEC (Logical Equivalence Check)
11 What is a synthesized netlist?
Describes circuit in terms of cells and connections, output by logic synthesis tools after technology mapping and
optimization
12 What differentiates logical and physical synthesis?
Logical synthesis optimizes for area, timing, and power at RTL level, while physical synthesis uses placement data,
congestion, and physical constraints to further refine timing and area
Understanding Physical Design Fundamentals
13 Describe wire load models
Estimate parasitic resistance and capacitance based on net fanout, helping with timing analysis before placement and
routing
14 How does fanout affect delay?
Increasing fanout increases wire resistance and capacitance, causing longer delays in signal propagation, requiring design
to limit fanout or add buffers
15 What is clock skew and why does it matter?
Time difference in clock signal arrival at different elements, potentially causing setup/hold violations. Minimizing skew is
essential for reliable timing closure
Understanding Physical Design Fundamentals
16 What analyses are performed during floorplan?
Macro overlap • Congestion analysis • Channel spacing • Initial power grid establishment — checked to finalize effective
layout
17 How is macro placement optimized?
Placed to minimize wirelength, avoid congestion, and keep critical paths short. Reordering can improve floorplan
efficiency
18 What is input reordering during design?
Process of changing pin assignments to minimize wire crossings and critical paths, improving overall layout quality
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