KARPAGAM ACADEMY OF HIGHER EDUCATION

CLASS: II MSc Physics COURSE NAME: DIGITAL ELECTRONICS AND MICROPROCESSOR

COURSE CODE: 19PHP304 UNIT: I (FLIP-FLOPS) BATCH-2018-2020
REGISTERS
When a number of flip flops are connected in series, this arrangement is called a Register. The
stored information can be transferred within the registers; these are called as „Shift Registers‟. A shift
register is a sequential circuit which stores the data and shifts it towards the output on every clock cycle.
Basically shift registers are of 4 types. They are
 Serial In Serial Out shift register
 Serial In parallel Out shift register
 Parallel In Serial Out shift register
 Parallel In parallel Out shift register
Serial in Serial Out Shift Register
The input to this register is given in serial fashion i.e. one bit after the other through a single data
line and the output is also collected serially. The data can be shifted only left or shifted only right. Hence
it is called Serial in Serial out shift register or a SISO shift register.
As the data is fed from right as bit by bit, the shift register shifts the data bits to left. A 4-bit SISO
shift register consists of 4 flip flops and only three connections.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.
As the clock signal is connected to all the 4 flip flops, the serial data is connected to the left most or right
most flip flop. The output of the first flip flop is connected to the input of the next flip flop and so on.

In the above diagram, we see the shift right register; feeding the serial data input from the left
side of the flip flop arrangement.
In this shift register, when the clock signal is applied and the serial data is given; only one bit will
be available at output at a time in the order of the input data. The use of SISO shift register is to act as
temporary data storage device. But the main use of a SISO is to act as a delay element.
Serial in Parallel Out shift register
The input to this register is given in serial and the output is collected in parallel. The clear (CLR)
signal is connected in addition to clock signal to all the 4 flip flops in order to RESET them and the serial

Prepared by Mr. J. THIRUPATHY, Asst Prof, Department of Physics, KAHE 8/20

 KARPAGAM ACADEMY OF HIGHER EDUCATION
CLASS: II MSc Physics COURSE NAME: DIGITAL ELECTRONICS AND MICROPROCESSOR
COURSE CODE: 19PHP304 UNIT: I (FLIP-FLOPS) BATCH-2018-2020
lines are multiplexed into single serial data line.
Parallel in Parallel out shift register
In this register, the input is given in parallel and the output also collected in parallel. The clear
(CLR) signal and clock signals are connected to all the 4 flip flops. Data is given as input separately for
each flip flop and in the same way, output also collected individually from each flip flop.

In the 4 stage parallel in parallel out register. Qa, Qb, Qc and Qd are the parallel outputs and Pa,
Pb, Pc and Pd are the individual parallel inputs. There are no interconnections between any of the four
flip flops.

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and also as a
delay element similar to a SISO shift register.
COUNTERS

A counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal.

Types of counter

 Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state
flip-flops
 Synchronous counter – all state bits change under control of a single clock
 Decade counter – counts through ten states per stage
 Up/down counter – counts both up and down, under command of a control input
 Ring counter – formed by a shift register with feedback connection in a ring
 Johnson counter – a twisted ring counter

Prepared by Mr. J. THIRUPATHY, Asst Prof, Department of Physics, KAHE 10/20

De-Multiplexer:-

The demultiplexer is the inverse of the multiplexer, in that it takes a data input and n address
inputs. It has 2n outputs. The address input determine which data output is going to have the
same value as the data input. The other data outputs will have the value 0.

UNIT-III

Flip Flop:-

A flip-flop or latch is a circuit that has two stable states and can be used to store state
information. The circuit can be made to change state by signals applied to one or more control
inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-
flops and latches are a fundamental building block of digital electronics systems used in
computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for
storage of state, and such a circuit is described as sequential logic. When used in a finite-state
machine, the output and next state depend not only on its current input, but also on its current
state (and hence, previous inputs). It can also be used for counting of pulses, and for
synchronizing variably-timed input signals to some reference timing signal.

(a) Logic diagram

(b) Truth table

Basic flip-flop circuit with NOR gates

S.R Flip Flop:- When using static gates as building blocks, the most fundamental latch is the
simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-
coupled NOR logic gates. The stored bit is present on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant
state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the
Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while
S is held low, then the Q output is forced low, and stays low when R returns to low. The R = S =
1 combination is called a restricted combination or a forbidden state because, as both NOR gates
then output zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate
in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to
keep). The output would lock at either 1 or 0 depending on the propagation time relations
between the gates (a race condition). In certain implementations, it could also lead to longer
ringings (damped oscillations) before the output settles, and thereby result in undetermined
values (errors) in high-frequency digital circuits. Although this condition is usually avoided, it
can be useful in some applications.

To overcome the restricted combination, one can add gates to the inputs that would convert (S,R)
= (1,1) to one of the non-restricted combinations. That can be:

• Q = 1 (1,0) – referred to as an S-latch

• Q = 0 (0,1) – referred to as an R-latch
• Keep state (0,0) – referred to as an E-latch

Alternatively, the restricted combination can be made to toggle the output. The result is the JK
latch.

J-K FlipFlop:-

A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is
defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop
(note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs
are applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if
Q=1, it switches to Q=0 and vice versa.
A clocked JK flip-flop is shown in Figure below. Output Q is AND with K and CP inputs so that
the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q' is
ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was
previously 1.

Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1
(while J=K=1) after the outputs have been complemented once will cause repeated and
continuous transitions of the outputs. To avoid this, the clock pulses must have a time duration
less than the propagation delay through the flip-flop. The restriction on the pulse width can be
eliminated with a master-slave or edge-triggered construction. The same reasoning also applies
to the T flip-flop presented next.

(a) Logic diagram

(b) Graphical symbol

(c) Transition table

RACE AROUND CONDITION:-

Let us consider a JK Flip Flop (Hereby called FF). The excitation table of this FF is as follows :

J K Qn+1
0 0 Qn
010
101
1 1 Qn Bar ~ Complement of Qn

Let us say that a clock of certain frequency is fed to the FF, and consider the case of J=K=1, and
the propagation delay of FF is very very less than the clock pulse time
Then the FF continues complementing the output an unpredictable number of times, thus leading
to anomaly in the final output after the pulse time of the clock is completed

This condition is called Race Around condition and can be avoided by using a Master-Slave
JK FF

T Flip-Flop:-

The T flip-flop is a single input version of the JK flip-flop. As shown in Figure below, the T flip-
flop is obtained from the JK type if both inputs are tied together. The output of the T flip-flop
"toggles" with each clock pulse.

(a) Logic diagram

 (b) Graphical symbol

Master-Slave Flip-Flop

A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a
master and the other as a slave. The logic diagram of an SR flip-flop is shown in diagram. The
master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is
disabled by the inverter. The information at the external R and S inputs is transmitted to the
master flip-flop. When the pulse returns to 0, the master flip-flop is disabled and the slave flip-
flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop.

Logic diagram of a master-slave flip-flop

The timing relationship is shown in diagram and is assumed that the flip-flop is in the clear state
prior to the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on
the negative transition of the clock pulse. Some master-slave flip-flops change output state on the
positive transition of the clock pulse by having an additional inverter between the CP terminal
and the input of the master.
 Timing relationship in a master slave flip-flop

D Flip Flop:-

This latch exploits the fact that in the two active input combinations (01 and 10) of a gated SR
latch R is the complement of S. The input NAND stage converts the two D input states (0 and 1)
to these two input combinations for the next SR latch by inverting the data input signal. The low
state of the enable signal produces the inactive "11" combination. Thus a gated D-latch may be
considered as a one-input synchronous SR latch. This configuration prevents from applying the
restricted combination to the inputs. It is also known as transparent latch, data latch, or
simply gated latch. It has a data input and an enable signal (sometimes named clock, or control).
The word transparent comes from the fact that, when the enable input is on, the signal propagates
directly through the circuit, from the input D to the output Q.
Transparent latches are typically used as I/O ports or in asynchronous systems, or in synchronous
two-phase systems (synchronous systems that use a two-phase clock), where two latches
operating on different clock phases prevent data transparency as in a master–slave flip-flop..

Gated D latch truth table

E/C D Q Q Comment

0 X Qprev Qprev No change

1 0 0 1 Reset

1 1 1 0 Set
The truth table shows that when
the enable/clock input is 0,
the D input has no effect on the output. When E/C(Enable clock) is high, the output equals D.

Clocked SR Flip-Flop

The clocked SR flip-flop shown in diagram consists of a basic NOR flip-flop and two AND
gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0,
regardless of the S and R input values. When the clock pulse goes to 1, information from the S
4-bit synchronous counter
• The external clock pulses (pulses to be counted) are fed directly to each of the J-K
flipflops in the counter chain and that both the J and K inputs are all tied together in
toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH,
logic
“1” allowing the flip-flop to toggle on every clock pulse.
• Then the synchronous counter follows a predetermined sequence of states in response
to the common clock signal, advancing one state for each pulse.
• The J and K inputs of flip-flop FFB are connected directly to the output QA of flipflop
FFA, but the J and K inputs of flip-flops FFC and FFD are driven from separate AND
gates which are also supplied with signals from the input and output of the previous
stage.
• These additional AND gates generate the required logic for the JK inputs of the next
stage.
• If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop
outputs (Q) are “HIGH” we can obtain the same counting sequence as with the
asynchronous circuit but without the ripple effect, since each flip-flop in this circuit will
be clocked at exactly the same time.
• Then as there is no inherent propagation delay in synchronous counters, because all
the counter stages are triggered in parallel at the same time, the maximum operating
frequency of this type of frequency counter is much higher than that for a similar
asynchronous counter circuit.
UNIT-4
8085 Microprocessor
• A Microprocessor is a multipurpose, programmable, clock-driven, register-based
electronic device that reads binary instructions from a storage device called memory,
accepts binary data as input and processes data according to those instructions and
provide results as output.
• Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip
capable of performing ALU (Arithmetic Logical Unit) operations and communicating
with the other devices connected to it.
• Microprocessor consists of an ALU, register array, and a control unit.
• ALU performs arithmetical and logical operations on the data received from the
memory or an input device.
• Register array consists of registers identified by letters like B, C, D, E, H, L and
accumulator.
• The control unit controls the flow of data and instructions within the computer.

Block Diagram of a Basic Microcomputer

How does a Microprocessor Work?

High – Threshold Logic (HTL):
A high threshold logic gate is a modification of a DTL gate. It is designed for industrial
applications by providing large noise margin. Figure 7 shows the logic diagram of two –
input HTL NAND gate. This logic circuit has been designed for higher supply voltage
(15 V). It utilizes a zener diode of breakdown voltage of 6.9 V.

Fig. 7
The transistor T2 will conduct when the emitter of transistor T 1 is at 7.5 V, as the sum of
6.9 V zener voltage and VBE of T2 (0.6 V). The low output level of the HTL gate will be
0.2 V and high level will be about 15 V. When one of the inputs or both the inputs are
at low transistor T2 is off. When both the inputs are high transistor T 2 saturates.
The advantage of this gate is that its noise margin is high however it is slow in speed.

Transistor – Transistor Logic (TTL):

The TTL is the most popular amongst all logic families and is widely used IC
technology.. It is the modified form of DTL. The propagation delay time is reduced in
TTL by using multi-emitter transistor in place of diodes. Figure 8 shows the schematic
diagram of a basic TTL positive logic NAND gate. It consists of a multi-emitter
transistor T1. A two emitter transistor is equivalent to two transistors with common base
and common collector as shown in figure 9.
The operation of TTL NAND gate may be explained as follows:
When either of two inputs A or both the inputs are at logic 0, emitter base
junction of the multi-emitter transistor will be in forward bias and base current is
supplied by the resistor R1. The transistor T1 saturates and the voltage at the point will
be equal to VCE,Sat of the transistor ( 2.0 ≈ V). The transistor T2 will be in cutoff and
output voltage will be high (logic 1).

Fig. 8 Fig. 9

When both the inputs are at logic 1 (+5 V), the emitter base junctions of
transistor T1 will be reverse biased and current will flow, through R1 and through the
forward biased base collector junction of transistor T 1 into the base of transistor T2. In
this mode the transistor is said to be operated in the inverted mode, as the collector of
transistor T1 operates as emitter and the emitter as collector. The voltage at the point P
will be sufficient to drive the transistor T 2 into saturation, the output voltage will
therefore, be equal to VCE,Sat ( 2.0 ≈ V) or logic 0.
The propagation delay time of this gate is smaller than that of DTL NAND gate,
since when the transistor T2 goes into cutoff region from saturation region, the transistor
T1 saturates and provides a low impedance path to ground. Thus the stored base charge
of the transistor T2 is quickly removed thereby reducing the propagation delay time.
The output resistance of the basic TTL circuit (fig. 8) is low when the transistor
T2 saturates or output is low (logic 0). However, the output resistance of this circuit is
almost equal to the resistance R, when the transistor is in cutoff or output is high (logic
1). This will restrict the fan out of the gate. The reduction in resistor R would increase
the power dissipation in R and in the gate. Also the reduction in the value of R would
difficult to saturate the transistor T 2. To overcome this difficulty, TTL gate with totem
pole arrangement is used.

TTL NAND Gate with Totem-pole Output:

Figure 10 shows the standard form of a TTL circuit with input NAND gate. The circuit
works as follows:
Programmable Logic Array(PLA):

The PLA is similar to PROM in concept except that PLA does not provide full decoding of the
variable and does not generate all the minterms . The decoder is replaced by an array of AND
gates that can be programmed to generate any product term of the input variables. The product
terms are then connected to OR gates to provide the sum of products for the required Boolean
functions.
 Fig.7-14, the decoder in PROM is replaced by an array of AND gates that can be
programmed to generate any product term of the input variables.

 The product terms are then connected to OR gates to provide the sum of products for
the required Boolean functions.

 The output is inverted when the XOR input is connected to 1 (since x⊕1 = x’). The
output doesn’t change and connect to 0 (since x⊕0 = x).

 F1 = AB’+AC+A’BC’

 F2 = (AC+BC)’

The diagram uses the array logic graphic symbols for complex circuits. Each input goes
through a buffer and an inverter shown in the diagram with a composite graphic symbol which
has both the true and complement outputs. Each input and its complement are connected to the
inputs of each AND gate as indicated by the intersections between the vertical and horizontal
lines. The outputs of the AND gates are connected to the inputs of each OR gate.

 The output of the OR gates goes to an XOR gate where the other input
can be programmed to receive a signal equal to either logic 1 or 0. The
 output is inverted when the XOR input is connected to 1. The output
does not change when the XOR input is connected to 0 .

 The product terms generated in each AND gate are listed along the output of the gate in
the diagram. The product term is determined from the inputs whose crosspoints are
connected and marked with a X . The output of an OR gate gives the logic sum of the
selected product terms. The output may be complemented or left in its true form
depending on the connection for one of the XOR gate inputs.

 The programming table that specifies the PLA of Fig.4 is listed in Table 2. The PLA
programming table consists of three sections .The first section lists the product terms
numerically. The second section specifies the required paths between inputs and AND
gates. The third section specifies the paths between AND and OR gates.


 ECE 282: DIGITAL ELECTRONICS I – Lecture Notes by Dr.-Ing. S. I. Kamau 77

4.7.5 Shift Register Counters

All shift register counters use feedback whereby the output of the last flip-flop in the
shift register is in some way connected to the first flip-flop.

Ring counter
PSfrag replacements
This is a circulating shift register connected so that the last flip-flop shifts its value into
the first flip-flop. It operates by recirculating either a single ‘1’ or a ‘0’. An example of a
4-bit ring counter is shown on Figure 4.44.

D Q3 D Q2 D Q1 D Q0

Q3 Q2 Q1 Q0
CLK CLK CLK CLK

Figure 4.44: A 4-bit ring counter

Assuming that the initial state of the circuit is Q3 Q2 Q1 Q0 = 1000, the timing waveforms
for the circuit are shown on Figure 4.45.
1
CLK
0
1
PSfrag replacementsQ3 0
1
Q2
0
1
Q1
0
1
Q0
0

Figure 4.45: Timing waveforms for the 4-bit ring counter

The waveforms can be summarized by the table below:

Q3 Q2 Q1 Q0 clock pulses
1 0 0 0 before applying clock pulses
0 1 0 0 after clock pulse #1
0 0 1 0 after clock pulse #2
0 0 0 1 after clock pulse #3
1 0 0 0 after clock pulse #4 - recycles
 ECE 282: DIGITAL ELECTRONICS I – Lecture Notes by Dr.-Ing. S. I. Kamau 78

Note that although this does not progress through the normal binary counting sequence, it
is still a counter because each count corresponds to a particular state of the counter.
The circuit shown on Figure 4.44 is therefore a MOD 4 ring counter which recirculates
a ‘1’. In general, a MOD N ring counter requires N flip-flops. This type of a counter is
mostly used in sequencing operations.

Johnson Counter

This type of counter is also known as the twisted-ring counter. It is constructed ex-
PSfrag replacements
actly like a normal ring counter, except that the inverted output of the last flip-flop is
connected to the first flip-flop. Figure 4.46 shows a 3-bit Johnson counter.

D Q2 D Q1 D Q0

Q2 Q1 Q0
CLK CLK CLK

Figure 4.46: A 3-bit Johnson (twisted ring) counter

Assuming the initial state is Q2 Q1 Q0 = 000, the timing waveforms are shown on Fig-
ure 4.47.
1
CLK
0
PSfrag replacements 1
Q2
0
1
Q1
0
1
Q0
0

Figure 4.47: Timing waveforms for the 3-bit Johnson counter

The table below summarizes the timing waveforms:

Types of main memory;

The memory unit can be implemented using a variety of memory

chips- different speeds, different manufacturing technology, and
different sizes. The main memory types are:

1- Read Only Memories (ROM):

ROMs allow only read operation to be performed. This memory is non-volatile. Most
ROMs are programmed and cannot be altered.
This type of ROM is cheaper to manufacture than other types of ROM. The program
that controls the standard I/O functions (called BIOS) and configuration software are
kept in ROM,.
Other types of ROM include:
A- Programmable ROM (PROM).

B- Erasable PROM (EPROM) is read only memory that can be

reprogrammed using special equipment.

C- EAPROM, Electrically Alterable Programmable ROM is a

Read Only Memory that is electrically reprogrammable.

2- Read/Write Memory (RAM):-

Read/Write memory is commonly referred to as Random Access Memory (RAM), it is
divided into static and dynamic.

A-Static RAM (SRAM): used for implementing CPU registers and used for special high
speed memory called cache memory this greatly improves system performance. Static
RAM keeps its value without having to be refreshed.

B-Dynamic RAM (DRAM), the bulk of main memory in a typical computer system
consists of dynamic Ram. DRAM is where programmed, data are kept when a program
is running. It must be refreshed with in less than a millisecond or losses its contents.
1
The differences between RAM AND ROM

RAM ROM

1-Stand foe Random - Access memory 1- stand for Read Only Memory

2- Read /Write memory 2-READ Only Memory

3-Sending data (writing) to RAM memory 3-Sending data to ROM memory address is
address is called destructive write because in effective because the contents of ROM
the new data erases whatever was there can not changed (write not allowed )
before because this memory for read only

4-form of primary storage(main memory) 4-form of primary storage(main memory)

for holding temporary data and instruction for holding permanent data and instruction

5- Volatile : program and data are erased 5-Permanent : program and data are intact
when the power is off even power is off
6- Type of RAM is 6-Type of ROM is
a- Static RAM a- PROM
b- Dynamic RAM b-EPROM
c- EAPROM

NOTE: The Main Memory is called also primary memory or

primary storage