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Summer 24

The document outlines the final exam for the Logic Design course at Ain Shams University, consisting of four questions with a total of 40 marks. Questions cover topics such as circuit design for BCD detection, absolute value components, synchronous sequential circuits, and a 4-bit counter IC. The exam is scheduled for August 28, 2024, and is designed for engineering students in the MCTA, CESS, and COMM programs.

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Hassan Shehata
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3 views2 pages

Summer 24

The document outlines the final exam for the Logic Design course at Ain Shams University, consisting of four questions with a total of 40 marks. Questions cover topics such as circuit design for BCD detection, absolute value components, synchronous sequential circuits, and a 4-bit counter IC. The exam is scheduled for August 28, 2024, and is designed for engineering students in the MCTA, CESS, and COMM programs.

Uploaded by

Hassan Shehata
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Ain Shams University

Faculty of Engineering

i-Credit Hours Engineering Programs


MCTA, CESS, COMM Engineering Programs
Summer 2024 Course Code: CSE111 Time Allowed: 2 Hours
Logic Design – Final Exam
The Exam Consists of Four Questions in Two Pages. Maximum Marks: 40 Marks 1/2
Question (1): [10 Marks]
(a) Design a circuit, with four digital inputs (A3, A2, A1, A0) and one output B, to detect invalid
BCD data and output a HIGH signal for any invalid BCD combination. [6 Marks]
(b) Design a 40-to-1 multiplexer using 8-1 multiplexers. [4 Marks]
Question (2): [8 Marks]
(a) Create an absolute value component with an 8-bit input A that is a signed binary number, and
an 8-bit output Q that is unsigned and that is the absolute value of A. If the input is 00001111
(+15) then the output is also 00001111 (+15), but if the input is 11111111 (-1) then the output
is 00000001 (+1). Compose the circuit from adder(s), multiplexer(s) and logic gates. Use
modules for your components. [4 Marks]
(b) Use magnitude comparators (as modules) and logic gates to design a circuit that outputs 1
when an 8-bit input a is between 75 and 100, inclusive. [4 Marks]
Question (3): [12 Marks]
A clocked synchronous sequential circuit using positive edge triggered D FFs has an input X and
output Y. The excitation and output equations of the circuit are:
𝐷1 = 𝑄1 𝑋 ′ + 𝑄1′ 𝑄0 𝑋 + 𝑄1 𝑄0′ 𝑋
𝐷0 = 𝑄0 𝑋 ′ + 𝑄0′ 𝑋
𝑌 = 𝑄0 𝑄1 𝑋
(a) Draw the circuit diagram [4 Marks]
(b) Obtain the state diagram [4 Marks]
(c) Redesign the circuit using J-K FFs [4 Marks]
Question (4): [10 Marks]
The following 4-bit counter IC has two enable inputs ENT and ENP. If either of these inputs is at
logic 0, the counter stops counting asynchronously. Ripple carry (RC) output is normally at logic 0
and goes to logic 1 whenever the counter reaches its highest count. The function table of the counter
is given to the bottom. Consider that the counter has the input signals given in the timing diagram
applied. The parallel data present inputs are permanently connected as 1100. Assume the counter is
initially in the 0000 state. Redraw the given input waveforms in your answer sheet then draw the
waveforms for the five counter outputs.
AIN SHAMS UNIVERSITY, FACULTY OF ENGINEERING
MCTA, CESS, COMM Engineering Programs
Summer 2024 Course Code: CSE111 Time Allowed: 2 Hours
Logic Design – Final Exam
The Exam Consists of Four Questions in Two Pages. Maximum Marks: 40 Marks 2/2

End of Exam, Good Luck


Examination Committee Dr Mohamed Omar Examination Date: 28th Aug, 2024

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