PC-BASED MEASUREMENT AND

CONTROL

CHAPTER 2: COMPUTER INTERFACE

CONTENTS
PhD. NGUYỄN HOÀNG GIÁP
Outline
➢ Computer organization
➢ I/O data transfer schemes
➢ Principles of computer buses
➢ Addressing
➢ Overview of computer buses
Outline
➢ Computer organization
➢ I/O data transfer schemes
➢ Principles of computer buses
➢ Addressing
➢ Overview of computer buses
Computer organization
➢ The Control Unit (cu) and the Arithmetic and Logic Unit (ALU)
constitute the Central Processing Unit (CPU)
➢ Data and instructions need to get into the system and results need to get
out
✓ Input/output (I/O module)
➢ Temporary storage of code and results is needed
✓ Main memory (RAM)
Instruction Cycle
➢ Two steps:
✓ Fetch
✓ Execute
Fetch cycle
➢ Program Counter (PC) holds address of next instruction to fetch
➢ Processor fetches instruction from memory location pointed to by PC
➢ Increment PC
✓ Unless told otherwise
➢ Instruction loaded into Instruction Register (IR)
Execute cycle
➢ Processor interprets instruction and performs required actions:
✓ Processor - memory
❖ data transfer between CPU and main memory
✓ Processor - I/O
❖ Data transfer between CPU and I/O module
✓ Data processing
❖ Some arithmetic or logical operation on data
✓ Control
❖ Alteration of sequence of operations (e.g., jump)
✓ Combination of above
Example of program execution
Instruction cycle - state diagram
Outline
➢ Computer organization
➢ I/O data transfer schemes
➢ Principles of computer buses
➢ Addressing
➢ Overview of computer buses
I/O data transfer schemes
➢ Programmed I/O
➢ Interrupt driven data transfer
Programmed I/O

➢ Advantage:
✓ Simple: the processor is totally in control and does all the work
➢ Disadvantage:
✓ Polling overhead can consume a lot of CPU time
Interrupt driven data transfer
➢ Whenever an I/O device needs attention from the processor, it interrupts
the processor from what it is currently doing
➢ Interrupting is a mechanism by which other modules (e.g., I/O) may
interrupt normal sequence of processing
➢ Advantage:
✓ User program progress is only halted during actual transfer
➢ Cost: special hardware is needed to:
✓ Cause an interrupt {I/O device)
✓ Detect an interrupt (processor)
✓ Save the proper states to resume after the interrupt (processor)
Interrupt sources
➢ Program
✓ e.g, overflow, division by zero
➢ Timer
✓ Generated by internal processor timer
✓ Used in pre-emptive multi-tasking
➢ I/O
✓ from I/O controller
➢ Hardware failure
✓ e.g, memory parity error
Interrupt cycle
➢ Processor checks for interrupt
✓ Indicated by an interrupt signal
➢ If no interrupt, fetch next instruction
➢ If interrupt pending:
✓ Suspend execution of current program
✓ Save context
✓ Set PC to start address of interrupt handler (service) routine
✓ Process interrupt
✓ Restore context and continue interrupted program
Transfer of control via interrupts
Instruction cycle with interrupts
Instruction cycle (with interrupts) - state diagram
Interrupt handler (service routine)
Multiple Interrupts
➢ Approach 1: disable interrupts (sequential)
✓ Processor will ignore further interrupts whilst processing one
interrupt
✓ Interrupts remain pending and are checked after first interrupt has
been processed
✓ Interrupts handled in sequence as they occur
➢ Approach 2: priorities
✓ Low priority interrupts can be interrupted by higher priority
interrupts
✓ When higher priority interrupt has been processed, processor
returns to previous interrupt
Multiple interrupts - sequential
Multiple interrupts - priorities
Direct Memory Access (DMA)

➢ I/O exchanges occur directly with memory

✓ Delegating I/O responsibility from the CPU
➢ Processor grants I/O module authority to read from or write to memory
Outline
➢ Computer organization
➢ I/O data transfer schemes
➢ Principles of computer buses
➢ Addressing
➢ Overview of computer buses
Connections

➢ All the units is a computer must be connected

➢ Different type of connection for different type of unit
✓ Memory
✓ Input/output
✓ CPU
Computer Modules
Memory connection
➢ Receives and sends data
➢ Receives addresses (of locations)
➢ Receives control signals
✓ Read
✓ Write
✓ Timing
Input/Output connection(l)
➢ Similar to memory from computer's viewpoint
➢ Output
✓ Receive data from computer
✓ Send data to peripheral
➢ Input
✓ Receive data from peripheral
✓ Send data to computer
Input/Output connection(2)

➢ Receive control signals from computer

➢ Send control signals to peripherals
✓ e.g., disk
➢ Receive addresses from computer
✓ e.g. port number to identify peripheral
➢ Send interrupt signals (control)
CPU connection
➢ Reads instruction and data
➢ Writes out data (after processing)
➢ Sends control signals to other units
➢ Receives (& acts on) interrupts
Buses
➢ There are a number of possible interconnection systems

What is a Bus?
➢ A communication pathway connecting two or more devices
➢ Usually broadcast (all components see the signals)
➢ Often grouped
✓ A number of channels in one bus
✓ e.g., 32 bit data bus is 32 separate single bit channels
➢ Power lines may not be shown
Bus interconnection scheme
Data Bus

➢ Carries data
✓ Remember that there is no difference between "data" and
"instruction" at this level
➢ Width is a key determinant of performance
✓ 8, 16, 32, 64 bit
Address bus
➢ Identify the source or destination of data
➢ e.g., CPU needs to read an instruction (data) from a given location in
memory
➢ Bus width determines maximum memory capacity of system
✓ e.g., 8080 has 16 bit address bus giving 64k address space
Control Bus

➢ Control and timing information

✓ Memory read/write signal
✓ Interrupt request
✓ Clock signals
Single bus problems
➢ Several devices on one bus leads to:
✓ The bandwidth of that bus can limit the maximum I/O throughput
➢ The maximum bus speed is largely limited by:
✓ The width of the bus
✓ The number of devices on the bus
✓ The need to support a range of devices with:
❖ Widely varying latencies
❖ Widely varying data transfer rates
➢ Most systems use multiple buses to overcome these problems
Bus types

➢ Dedicated
✓ Separate data & address lines
✓ E.g., ISA bus
➢ Multiplexed
✓ Shared lines
✓ Address valid or data valid control line s Advantage: fewer lines
✓ Disadvantage: more complex control
✓ E.g., PCI bus
Synchronous bus timing diagram
Asynchronous bus timing – read diagram
Asynchronous timing - write diagram
Master versus slave

➢ A bus transaction includes two parts:

✓ Sending the address
✓ Receiving or sending the data
➢ Master is the one who starts the bus transaction by sending the address
➢ Salve is the one who responds to the address by:
✓ Sending data to the master if the master ask for data
✓ Receiving data from the master if the master wants to send data
Obtaining access to the bus
➢ One of the most important issues in bus design:
✓ How is the bus reserved by a devices that wishes to use it?
➢ Chaos is avoided by a master-slave arrangement:
✓ Only the bus master can control access to the bus. It initiates and
controls all bus requests
✓ A slave responds to read and write requests
➢ The simplest system:
✓ Processor is the only bus master
✓ All bus requests must be controlled by the processor
✓ Major drawback: the processor is involved in every transaction
Bus arbitration
➢ More than one module control the bus
✓ e.g., CPU and DMA controller
➢ Only one module may control bus at a time - bus arbitration
➢ Bus arbitration:
✓ A bus master wanting to use the bus asserts the bus request
✓ A bus master cannot use the bus until its request is granted
✓ A bus master must signal to the arbiter after it finishes using the bus
➢ Bus arbitration schemes usually try to balance two factors:
✓ Bus priority: the highest priority device should be serviced first
✓ Fairness: even the lowest priority device should never be completely
locked out from the bus
Bus arbitration schemes
➢ Distributed arbitration by self-selection
✓ Each device wanting the bus places a code indicating its identity on
the bus.
➢ Distributed arbitration by collision detection: Ethernet uses this.
➢ Daisy chain arbitration
✓ next slides
➢ Centralized, parallel arbitration
✓ next-next slides
The Daisy Chain bus arbitration

➢ Grant line chains through each device from the highest priority to the
lowest priority
➢ Advantage: simple
➢ Disadvantages:
✓ Cannot assure fairness:
A low-priority device may be locked out indefinitely
✓ The use of the daisy chain grant signal also limits the bus speed
Centralized arbitration with a bus arbiter
Simple implementation of a bus arbiter
Priority logic
Increasing the bus bandwidth
➢ Separate address and data lines (not multiplexed):
✓ Address and data can be transmitted in one bus cycle if separate
address and data lines are available
✓ Cost: more bus lines
➢ Data bus width:
✓ By increasing the width of the data bus, transfers of multiple words
require fewer bus cycles
✓ Cost: more bus lines
➢ Block (burst) transfers:
✓ Allow the bus to transfer multiple words in back-to-back bus cycles
✓ Only one address needs to be sent at the beginning
✓ The bus is not released until the last word is transferred
✓ Cost: increased complexity, increased response time for request
Outline
➢ Computer organization
➢ I/O data transfer schemes
➢ Principles of computer buses
➢ Addressing
➢ Overview of computer buses
Addressing
➢ Although the memory space is said to be flat, it does not mean that the
physical implementation of memory is homogeneous s Different portions
of memory are used for different purposes: RAM, ROM, I/O devices
➢ Even if all the memory was of one type, we still have to implement it
using multiple ICs
➢ This means that for a given valid address, one and only one memory-
mapped component must be accessed
Addressing cont.
➢ Address decoding is the process of generating chip select (CS*) signals
from the address bus for each device in the system
➢ The address bus lines are split into two sections:
✓ the N most significant bits are used to generate the CS* signals for
the different devices
✓ the M least significant signals are passed to the devices as addresses
to the different memory cells or internal registers
Addressing simple example
➢ Let's assume a very simple microprocessor with 10 address lines (1KB
memory)
➢ Let's assume we wish to implement all its memory space and we use 128x8
memory chips
➢ SOLUTION:
✓ We will need 8 memory chips (8x128=1024)
✓ We will need 3 address lines to select each one of the 8 chips
✓ Each chip will need 7 address lines to address its internal memory cells
Address decoding
➢ Discrete logic
✓ High chip-count
✓ Lacks flexibility
➢ Data decoders
✓ More appropriate than discrete logic
✓ All the memory blocks must have the same
size
➢ Field Programmable Gate Arrays (FPGA)
Address decoding example

➢ Design a partial address decoder for a system that contains

✓ 2MB of EPROM at a starting address 0X000000 using 1MX8 chips
✓ 2MB of RAM at a starting address 0X200000 using 512Kx8 chips
✓ 64KB I/O space starting at OXFFOOOO
➢ Solution
✓ For the EPROM we will need 2 1MX8 chips
✓ Tor the RAM we will need 4 512Kx8 chips
I/O Addressing
➢ Memory mapped I/O
✓ The same address space is used for both memory and I/O
✓ There are no specific I/O instructions
✓ It allows the computer to used the same instructions for both I/O transfers and
memory transfers
✓ They are only one set of read/write control signals
✓ This method is used in most of embedded processors
➢ Isolated I/O
✓ CPU has distinct input and output instructions
✓ Memory address and I/O address have its own address space
✓ If the address of interface registers are placed on the address lines the I/O read
or I/O write control lines are enabled.
✓ If the memory address is placed on the address lines the memory read and
memory write control lines are enabled.
✓ The intel x86 family uses this method
Device I/O port locations on PCs (partial)
Outline
➢ Computer organization
➢ I/O data transfer schemes
➢ Principles of computer buses
➢ Addressing
➢ Overview of computer buses
Motherboard components
ISA (Industry standard Architecture) -1981
➢ The ISA standard is based on PC/AT (16-bit / 8 MHz = 16
MB/s) -1984
➢ 62 pins (8-bit PC ISA) or 98 pins (16-bit PC/AT ISA).
➢ The ISA bus supported 1MB (PC/XT) / 16 MB (PC/AT)
memory and 64K I/O address spaces.
Original IBM 5170 PC/AT motherboard -1984
➢ 8-bit and 16-bit ISA slots
ISA (Industry standard Architecture) - 1981 (cont.)
➢ 16-bit ISA slot signals (PC/AT)
EISA (Extended ISA) -1988
➢ Created by 3rd-party PC clone vendors.
➢ 32-bit / 8 MHz = 32 MB/s.
➢ Software-based configuration (i.e. no IRQ, DMA jumpers).
➢ EISA slots accepted ISA cards but EISA cards would not work in ISA
slots.
➢ Was never popular because ISA + VLB carried the PC platform until
PCI came along.
EISA- 1988 (cont.)
➢ EISA slots-Accepts ISA cards too.
EISA- 1988 (cont.)
➢ EISA card - Does not fit in ISA slot.
VLB (VESA Local Bus )-1992
➢ 32-bit, 33 MHz = 133 MB/s.
➢ Created by Video Electronics Standards Association (VESA) for
attaching high-performance graphics cards to ISA, and later PCI,
motherboards.
➢ Custom slot that extends the 16-bit ISA slot (see next slide).
➢ The CPU memory bus only allowed one or two VLB card loads (due
to loading issues).
VLB (VESA Local Bus ) - 1992 (cont.)
VLB (VESA Local Bus ) - 1992 (cont.)

➢ 32-bit VLB Graphics Card

PCI (Peripheral Component Interconnect) - 1992
➢ Created by Intel (later PCI-SIG) to bring together best ideas from
prior bus architectures.
➢ 32-bit, 33 MHz = 133 MB/s
➢ Also supported 64-bit (while not commonly implemented) = 266
MB/s
➢ Full plug-and-play
✓ cards report memory, IRQ, I/O requirements - device drivers and
operating system make sure the cards get the resources they need
and that no resource clashes occur.
➢ Growing used PCI bandwidth eventually necessitated separate AGP
graphics card bus.
PCI (Peripheral Component Interconnect) - 1992 (cont.)

➢ 4x32-bit PCI slots + 4xl6-bit ISA slots.

PCI (Peripheral Component Interconnect) - 1992 (cont.)
➢ PCI bus now decoupled from CPU bus.
PCI (Peripheral Component Interconnect) - 1992 (cont.)
➢ PCI Bus interface signals (32/64 bit data).
PCI-X (PCI- Extended) - 1998
➢ 32/64-bit, 66/133/266/533 MHz (up to 4,266 MB/s).
➢ PCI-SIG (IBM, Compaq, HP)
✓ Note: Intel wanted a better option.
➢ Improved protocol over PCI
✓ MSI signals interrupts via memory writes in host PCI bridge rather
than dedicated INTx interrupt lines.
➢ Due to higher cost, normally only server PCs used 64-bit PCI-X.
✓ Desktop systems migrated directly from PCI to PCI Express,
bypassing PCI-X.
➢ Wide buses resulted in difficult length matching of the bus signals (in
worst case, violating Tsu/Th).
➢ PCI-X reached practical frequency limit due to loading and skew of the
wide buses
➢ The wide buses tied up most I/O pins on the chipsets, limiting overall
chip functionality.
PCI Express - 2004
➢ Actually not a bus but a point-to-point link.
➢ High-speed bi-directional serial link (2.5 / 5.0 / 8.0 Gbps per lane, 1 to
32 lanes).
➢ Clock 8b/10b encoded within serial data stream.
➢ Maintains software backwards compatibility of Configuration Space
registers (Plug-and-Play).
➢ Also software backwards compatible with regards to I/O and Memory
mapped device registers.
➢ No length matching between lanes needed (separate lane-to-lane de-
skew built into receiver).
PCI Express - 2004 (cont.)
➢ PCI Express VS. PCI slots.
PCI Express - 2004 (cont.)
➢ PCI Express l.0/1.1:
250 MB/s per lane (max 8 GB/s for 32 Lanes) - 2003/2005.
➢ PCI Express 2.0:
500 MB/s per lane (max 16 GB/s for 32 Lanes) - 2007.
➢ PCI Express 3.0:
800 MB/s per lane (max 26 GB/s for 32 Lanes) - 2010.
➢ PCI Express 4.0:
2GB/s per lane - Expected to be released 2017.
➢ Efficient and physically compact enables use for all platforms (mobile,
desktop, server).
➢ No longer need for separate AGP graphics bus slot (lots of available
bandwidth).