INTRODUCTION, CMOS LOGIC STRUCTURES, CMOS

Module – 4
C O M P L E M E N TA R Y L O G I C , P S E U D O N - M O S L O G I C , D Y N A M I C

CMOS LOGIC, CLOCKED CMOS LOGIC, CASCADE V O LTA G E

S W I T C H L O G I C , PA S S T R A N S I S TO R L O G I C , E L E C T R I C A L A N D

CMOS P H Y S I C A L D E S I G N O F L O G I C G AT E S , T H E I N V E R T E R , N A N D A N D

N O R G AT E S , B O D Y E F F E C T, P H Y S I C A L L AYO U T O F L O G I C G AT E S ,

I N P U T O U T P U T PA D S .

Circuit and Prof. CHANDRA SHEKAR P

Logic Asst. Professor

Design Dept. of ECE

ATME College of Engineering, Mysuru
CMOS Logic structures
❖ CMOS Complementary Logic
❖ Pseudo-nMOS Logic
❖ Dynamic CMOS Logic
❖ Clocked CMOS Logic (C2MOS)
❖ CMOS Domino Logic
❖ Cascade Voltage Switch Logic (CVSL)
❖ Pass Transistor Logic
 Simple single phase dynamic CMOS:
▪Precharge phase : Clk (ᴓ) = 0
Dynamic CMOS ▪Evaluate Phase : Clk (ᴓ) = 1
Logic
Input Capacitance : only one gate unit

Problem:
▪Inputs can only change during the precharge phase.
▪If they change during evaluate, charge redistribution can corrupt
output voltage.

❑Pull-up time improved by virtue of the active switch (p-

transistor
❑can be much larger).
❑Pull-down time increased due to the ground switch.
 Basic Concept
Dynamic CMOS •Dynamic CMOS gate uses:
Logic • n-transistor logic structure.
• Precharge to VDD using a p-transistor.
• Conditional discharge to VSS using an n-
transistor.
•Single phase clock (ϕ) controls the
logic:
• ϕ = 0: Precharge phase – output node
charged to VDD.
• ϕ = 1: Evaluate phase – output may
discharge based on input.
 Operation Details
•The output load is charged during the precharge phase.
Dynamic CMOS •During evaluation, the output may discharge based on
Logic inputs.
•The input capacitance is same as pseudo-nMOS logic.
•Pull-up time is longer due to the use of a ground switch.
Challenges
[Link] must switch before evaluation, else:
1. Charge sharing may corrupt output.
[Link] is difficult:
1. Output of one gate may affect the next before full
evaluation.
[Link] constraints:
1. Fast gates must wait for slowest gates.
2. Leads to clock synchronization challenges.
Example
Cascaded dynamic logic
4-phase logic – type A

Improved Designs
•Use 2-phase or 4-phase clocking:
• Adds sample and hold phase.
•Fig. 5.5a and 5.5b: Gate precharge and evaluate cycle.
• ϕ1: PZ precharged, Z held.
• ϕ2: PZ remains precharged; Z precharges via
transmission gate.
• ϕ3: Gate evaluates; PZ discharges conditionally.
• ϕ4: Z held in evaluated state.
Logic Gate Typing
•Four types of gates exist based on
evaluation phase.
•Must be sequenced correctly for
reliable operation.
Clocking Schemes
•Alternate 4-phase system
• Simpler layout, fewer clocks.
• Restrictions on gate interconnects
•2-phase system:
• Uses gate types 2 and 4.
• More compact but restrictive.
4 – phase logic – type B
Transistor Count & Performance
•For n-input gate:
• Transistors needed = n + 4 or n
+ 3.
•Clock frequency must suit slowest
gate:
• Fast gates waste time waiting
(“dead time”).
•Distributing 4+ clocks is a
challenge on large chips.
 Clocked CMOS Logic (C²MOS)
Clocked CMOS •Purpose: C²MOS logic was originally designed to achieve low power
dissipation in CMOS circuits.
Logic
•Usage: It's often used to construct latches or interface with other
dynamic structures that incorporate latches.
•Characteristics:
• It has the same input forms of logic as regular complementary gates.
• It has larger rise and fall times compared to regular CMOS gates due to
the series clocking transistors.
• The gates have the same input capacitance as regular complementary
gates.

•Power Dissipation: The reduced dynamic power dissipation is a key

advantage. The text mentions this stems from metal gate CMOS layout
considerations.
C²MOS is a type of CMOS logic that prioritizes low power consumption,
often used in circuits with latches. However, it comes with a tradeoff of
slower switching speeds (larger rise and fall times) compared to
standard CMOS logic.
CMOS Domino
Logic
CMOS Domino Logic •Cascading: Each state evaluates and causes the next state to evaluate,
•Modification: Domino logic is a similar to a stack of dominoes falling. Any number of logic stages may be
modification of clocked CMOS logic. cascaded. The sequence can evaluate within the evaluation clock phase.
•Limitations:
•Operation: It allows a single clock to
• Only non-inverting structures are possible.
precharge and evaluate a cascaded set
• Each gate must be buffered.
of dynamic logic blocks. This involves a • Charge redistribution can be a problem (similar to clocked-CMOS).
static CMOS buffer in each logic gate. •Static Domino Logic: A weak p-transistor can be included to make the
•Precharge Phase (Clock = 0): domino gate static. This helps balance the effects of leakage and stabilize the
• The output node of the dynamic output when the clock is held high. However, it can slow down the pull-up
gate is precharged high. time.
• The output of the buffer is low. •Advantages:
•Transistors in subsequent logic blocks • A single clock can precharge and evaluate all logic gates within a
block.
are turned off. Evaluation Phase (Clock =
•Disadvantages:
1):
• Complex logic circuits (e.g., arithmetic logic units) requiring XOR
• The gate conditionally discharges,
gates may be implemented conventionally (as complementary gates)
causing the output of the buffer to
due to the limitations of domino logic.
conditionally go high.
Domino logic uses a precharge and evaluation scheme with buffers to create
• Each gate in the sequence can make
a fast, cascaded logic structure. It's efficient for certain types of logic but has
at most one transition (1 -> 0).
limitations regarding inverting structures and complexity. The static version
• The buffer can only make a transition
addresses some leakage issues at the cost of speed.
from (0 -> 1).
 Cascade Voltage
Switch Logic (CVSL)
•What is CVSL?
•A differential CMOS
logic style.
•Requires both true
and complement
input signals.
•Key Components:
•Complementary CVSL Operation
•Switching Mechanism:
nMOS switch
• Inputs switch, causing nodes Q and Q-bar
structures. to be pulled high or low.
•Cross-coupled p • Positive feedback from p pull-ups
pull-up transistors. accelerates the switching.
Examples of Static Version
Static CVSL (A "Slower" Version)
•Description: A "static"
implementation of CVSL.
•Disadvantage: Slower than
conventional CMOS gates.
•Reason: p pull-ups "fight" the n
pull-down trees during
switching.
Clocked / Dynamic CVSL (Improved
Version)
•Description: Essentially two
domino gates operating on true
and complement inputs.
•Logic Tree: Uses a minimized
logic tree.
4input Xor CVSL logic
 Advantages of Clocked CVSL / Applications

•Over Domino Logic:

•Ability to generate any logic
expression. •Automated Logic Synthesis:
•Makes it a complete logic family. •Ability to generate any logic
•Trade-offs: function is advantageous.
•Extra routing. •Example:
•Increased active area.
•Greater complexity (due to double-
•Four-way XOR gate
rail logic). implementation.
Pass Transistor
Logic
Modified CMOS for
Better Layout

P-Pull Version
 Electrical and Physical Design of Logic
Gates
❖ Inverter
 Electrical and Physical Design of Logic
Gates
❖ NAND gates
 Electrical and Physical Design of Logic
Gates
❖ NOR Gate
 Electrical and Physical Design of Logic
Gates
❖ Body Effect
•Definition: Change in threshold voltage (Vt) due to source-
substrate voltage difference.
•Occurs when source ≠ substrate potential.
•Increases threshold voltage → slows down switching.
•Affects nMOS more prominently in series-connected
transistors.
•Body effect expressed as:
Vt = Vto + γ(√(|Vsb + 2φf|) - √(2φf))
•Vsb = Voltage between source and body
•ΔVt = Change in threshold voltage due to Vsb > 0
NAND Gate Example
•nMOS transistors A-C initially at 0V.
•Input D turns ON, charges internal node C1.
•When all inputs HIGH, output node discharges
through D.
•D experiences higher Vsb → higher Vt → slower
switching.
Impact on Gate Delay
•Fall time increases due to slowed discharge path.
•Series-connected nMOS more affected than
pMOS.
•Must account for worst-case body effect in
timing.
Design Implications
•Minimize internal node capacitance. •Layout Considerations
•Reduce number of series transistors in •Use buried contacts where allowed.
path. •Complete internal connections in
•Prefer NOR if pMOS delay impact is lower.
metal or polysilicon.
Optimization Strategies
•1. Time Sequencing: •Minimize parasitic capacitance by
• Early signals discharge internal nodes. layout rules.
• Late signals switch low-body-effect Summary
transistors. •Body effect slows down switching due
•2. Capacitance Minimization: to raised Vt.
• Use metal/poly for internal
•Most visible in series nMOS
connections.
• Avoid diffusion wiring between transistors.
internal nodes. •Smart layout and signal timing reduce
• Keep diffusion area minimal. its impact.
Input-Output (I/O) Structures
❖ General pad Layouts
❖ Vdd and Vss pads
❖ Output pads
❖ Input pads
❖ Tri-state pads
❖ Bi-directional pads
 Input-Output (I/O) Structures
Importance of I/O Structures
•I/O design is among the most challenging parts of CMOS
circuit design.
•Requires a deep understanding of:
• Pad layout constraints
• ESD protection
• Signal integrity
• Power delivery
•Poor I/O design can cause chip failure or poor system
performance.
 I/O Pad Frame – Overall Organization
Example Ordering:
•Pads are arranged along the chip LEFT:
INPUT A
periphery. INPUT B
•Standard pad size: ~150 μm × 150 μm. •TOP:
INPUT C
•Connection points must match VDD VDD
predefined locations for packaging. RIGHT:
•Pads are typically grouped: OUTPUT Z
• Power pads (VDD, VSS) OUTPUT Y
BOTTOM:
• Input pads OUTPUT X
• Output pads VSS VSS
 General Pad Layouts
•Pads consist of metal areas connected to power or signal buses.
•May include vias for connectivity.
•VDD/VSS pads connected using metal, poly, or stacked vias.
•No need to minimize power pad size.
Types:
[Link] metal connection
[Link] crossover for compact layout
[Link]-layer via connections for strength
 Output Pads – Requirements & Design
•Must handle:
• Large capacitive loads
• Fast switching requirements
•Use strong buffers:
• Often a two-stage inverter chain
• Sizing ratio ~2:7 for strength
•Output stage must meet:
• DC drive current
• Rise/fall time targets
 Output Pads – Additional Considerations
•Pad capacitance must be matched with required speed.
•Consider use of non-inverting or two-stage drivers.
•Buffers help avoid signal degradation and noise.
Example:
•A high capacitive load may require:
• Large transistor sizes
• Lower output resistance
 Input Pads – Structure and Timing
•Connected to external signals through pads.
•Must be protected against ESD and high voltage spikes.
•Input resistance: very high (limits input current).
Key Design Equation:
•Where:
• V = Voltage rise on gate
• I = Charging current
• Δt = Time
• C = Gate capacitance
ESD Protection – Input Pads

•Use of diode clamps (D1, D2) to VDD

and VSS.
•Resistors to limit current.
•Guard rings isolate sensitive areas.
Design Elements:
•Poly resistors
•Diffused guard rings
•Vias to connect to supply
 Input Pad Design Practices
•Clamp input pad to prevent latch-up and damage.
•Use wide diffusions and guard rings.
•Avoid punch-through and parasitic conduction paths.
Latch-up Prevention Tips:
•Separate nMOS and pMOS devices
•Tie guard rings to VDD/VSS
 Tri-State Pads
•Allow output to be driven or disabled (High-Z state).
•Used on shared data buses.
•Controlled by enable signal to activate buffer
 Bi-Directional Pads
•Combine input and tri-state
structures.
•Can switch between input
and output mode.
•Use direction control logic.
•Example Applications:
• Data buses
• Microcontroller
Summary
•Good I/O design ensures:
• Reliability
• Signal integrity
• Protection from ESD
•Use:
• Well-sized buffers
• ESD diodes and resistors
• Proper pad layout and ordering
•Pay attention to:
• Power rail placement
• Latch-up susceptibility