21EC307 - VLSI Design Laboratory
Consolidated Exercise Manual (Set-1 & Set-2)
1. Combinational Logic - Adders and Subtractors
1.1 3-bit Binary Adder (Dataflow Modeling)
Used in: Set-1 Q1a, Set-2 Q1a
module adder_3bit(input [2:0] A, B, input Cin, output [2:0] Sum,
output Cout);
assign {Cout, Sum} = A + B + Cin;
endmodule
1.2 2-input Adder (Behavioral Modeling)
Used in: Set-1 Q2b, Set-2 Q2b, Set-1 Q18b, Set-2 Q18b
module adder_2input(input [3:0] A, B, output reg [4:0] Sum);
always @(*) begin
Sum = A + B;
end
endmodule
1.3 2-input Adder (Structural Modeling)
Used in: Set-1 Q7b, Set-2 Q7b, Set-1 Q22b, Set-2 Q22b
module half_adder(input a, b, output s, c);
xor g1(s, a, b);
and g2(c, a, b);
endmodule
module full_adder_structural(input A, B, Cin, output Sum, Cout);
wire s1, c1, c2;
half_adder ha1(A, B, s1, c1);
half_adder ha2(s1, Cin, Sum, c2);
or g3(Cout, c1, c2);
endmodule
1.4 Full Subtractor using Half Subtractors
Used in: Set-1 Q19b, Set-2 Q19b
module half_subtractor(input a, b, output diff, borrow);
assign diff = a ^ b;
assign borrow = (~a) & b;
endmodule
module full_subtractor(input A, B, Bin, output Diff, Bout);
wire d1, b1, b2;
half_subtractor hs1(A, B, d1, b1);
half_subtractor hs2(d1, Bin, Diff, b2);
assign Bout = b1 | b2;
endmodule
1.5 2-input Subtractor (Behavioral)
Used in: Set-1 Q3b, Set-2 Q3b, Set-1 Q9b, Set-2 Q9b
module subtractor_behavioral(input [3:0] A, B, output reg [3:0] Diff);
always @(*) begin
Diff = A - B;
end
endmodule
2. Multipliers and Comparators
2.1 8-bit Multiplier (Dataflow)
Used in: Set-1 Q2a, Set-2 Q2a
module multiplier_8bit(input [7:0] A, B, output [15:0] Prod);
assign Prod = A * B;
endmodule
2.2 2-bit Magnitude Comparator (Behavioral/Dataflow)
Used in: Set-1 Q8b, Set-2 Q8b, Set-1 Q18a, Set-2 Q18a, Set-1 Q23b, Set-2 Q23b
// Modeling Style 1: Dataflow (assign)
module comparator_dataflow(input [1:0] A, B, output G, E, L);
assign G = (A > B);
assign E = (A == B);
assign L = (A < B);
endmodule
// Modeling Style 2: Behavioral
module comparator_behavioral(input [1:0] A, B, output reg G, E, L);
always @(*) begin
G = 0; E = 0; L = 0;
if (A > B) G = 1;
else if (A == B) E = 1;
else L = 1;
end
endmodule
3. Decoders, Mux, and General Combinational
3.1 3-to-8 Decoder
Used in: Set-1 Q3a, Set-2 Q3a, Set-1 Q13b, Set-2 Q13b, Set-1 Q27b, Set-2 Q27b
module decoder_3to8(input [2:0] in, output reg [7:0] out);
always @(*) begin
out = 8'b00000000;
out[in] = 1'b1;
end
endmodule
3.2 4-input Combinational Circuit (Case Statement)
Used in: Set-1 Q5a, Set-2 Q5a, Set-1 Q20a, Set-2 Q20a
module comb_4input_case(input [3:0] in, output reg out);
always @(*) begin
case(in)
4'b1010: out = 1'b1;
4'b1111: out = 1'b1;
default: out = 1'b0;
endcase
end
endmodule
3.3 Multiplexer (any style)
Used in: Set-1 Q14b, Set-2 Q14b, Set-1 Q28b, Set-2 Q28b
module mux_4to1(input [3:0] i, input [1:0] sel, output out);
assign out = i[sel];
endmodule
4. Arithmetic Logic Unit (ALU)
4.1 Multi-operation ALU (Behavioral)
Used in: Set-1 Q6a, Set-2 Q6a, Set-1 Q9a, Set-2 Q9a, Set-1 Q21a, Set-2 Q21a
module alu_8bit(input [7:0] A, B, input [2:0] op, output reg [7:0]
Out);
always @(*) begin
case(op)
3'b000: Out = A + B; // Add
3'b001: Out = A - B; // Sub
3'b010: Out = A & B; // AND
3'b011: Out = A | B; // OR
3'b100: Out = ~(A & B); // NAND
3'b101: Out = A ^ B; // XOR
3'b110: Out = ~(A ^ B); // XNOR
3'b111: Out = ~A; // NOT
default: Out = 8'b0;
endcase
end
endmodule
5. Sequential Logic - Flip Flops
5.1 RS Flip-Flop
Used in: Set-1 Q11b, Set-2 Q11b, Set-1 Q26a, Set-2 Q26a
module rs_ff(input r, s, clk, output reg q, qbar);
always @(posedge clk) begin
case({s,r})
2'b01: q <= 0;
2'b10: q <= 1;
2'b11: q <= 1'bx;
endcase
qbar <= ~q;
end
endmodule
5.2 JK Flip-Flop
Used in: Set-1 Q13a, Set-2 Q13a, Set-1 Q27a, Set-2 Q27a
module jk_ff(input j, k, clk, output reg q);
always @(posedge clk) begin
case({j,k})
2'b01: q <= 0;
2'b10: q <= 1;
2'b11: q <= ~q;
endcase
end
endmodule
5.3 D Flip-Flop
Used in: Set-1 Q12a, Set-2 Q12a, Set-1 Q26b, Set-2 Q26b
module d_ff(input d, clk, output reg q);
always @(posedge clk) begin
q <= d;
end
endmodule
5.4 T Flip-Flop
Used in: Set-1 Q6b, Set-2 Q6b, Set-1 Q14a, Set-2 Q14a, Set-1 Q28a, Set-2 Q28a
module t_ff(input t, clk, rst, output reg q);
always @(posedge clk) begin
if (rst) q <= 0;
else if (t) q <= ~q;
end
endmodule
6. Counters and Shift Registers
6.1 3-bit Up/Down Counter
Used in: Set-1 Q8a, Set-2 Q8a, Set-1 Q10a, Set-2 Q10a, Set-1 Q23a, Set-2 Q23a, Set-1 Q25a,
Set-2 Q25a
module up_down_counter(input clk, rst, mode, output reg [2:0] count);
always @(posedge clk) begin
if (rst) count <= 0;
else if (mode) count <= count + 1; // Up
else count <= count - 1; // Down
end
endmodule
6.2 Universal Shift Register
Used in: Set-1 Q7a, Set-2 Q7a, Set-1 Q12b, Set-2 Q12b, Set-1 Q17b, Set-2 Q17b, Set-1 Q22a,
Set-2 Q22a
module usr(input clk, rst, input [1:0] s, input [3:0] pin, input lin,
rin, output reg [3:0] q);
always @(posedge clk) begin
if (rst) q <= 0;
else begin
case(s)
2'b00: q <= q; // Hold
2'b01: q <= {q[2:0], lin};// Left Shift
2'b10: q <= {rin, q[3:1]};// Right Shift
2'b11: q <= pin; // Parallel Load
endcase
end
end
endmodule
7. LTspice CMOS Designs
7.1 CMOS Inverter
Used in: Set-1 Q21b, Set-2 Q21b, Set-1 Q24a, Set-2 Q24a, Set-1 Q30a, Set-2 Q30a
● PMOS: Source to VDD, Gate to Input, Drain to Output.
● NMOS: Source to GND, Gate to Input, Drain to Output.
● Simulation: Pulse input (0 to 1.8V), Transient analysis.
7.2 CMOS NAND Gate
Used in: Set-1 Q1b, Set-2 Q1b, Set-1 Q4b, Set-2 Q4b, Set-1 Q20b, Set-2 Q20b
● PMOS: Two PMOS in parallel (Sources to VDD, Drains to Output).
● NMOS: Two NMOS in series (Drain of N1 to Output, Source of N1 to Drain of N2, Source
of N2 to GND).
7.3 CMOS NOR Gate
Used in: Set-1 Q11a, Set-2 Q11a, Set-1 Q15b, Set-2 Q15b
● PMOS: Two PMOS in series (Source of P1 to VDD, Source of P2 to Drain of P1, Drain of
P2 to Output).
● NMOS: Two NMOS in parallel (Sources to GND, Drains to Output).