VLSI DESIGN

VLSI
IV SEM

04-04-2026
Dr. Sresta Valasa
 COURSE DESCRIPTION
MODULE 1: MOS Transistor, CMOS logic, Inverter, Long-Channel I-V and CV Characteristics, Non ideal
I-V Effects, DC-Transfer characteristics, Noise Margin. Second order effects, MOS parasitic
Introduction to capacitance, Power: Dynamic Power, Static Power. Introduction to MOS spice models and
MOS transistor: Scaling of MOS circuits. [10]

MODULE 2:
Fabrication of Fabrication of MOS transistor, Latch-up in CMOS, Stick Diagrams, Layout Design Rules. [8]
ICs:

MODULE 3: Static CMOS, Ratioed Circuits, Dynamic Circuits, Pass Transistor Logic, Transmission
Combinational and Gates, with examples, Domino, Dual Rail Domino, CPL, Cascode Voltage Switch Logic, Bi-
CMOS inverter circuits. Static latches and Registers, Dynamic latches and Registers, Sense
sequential MOS logic circuits:
Amplifier Based Register, clocking strategies. [12]

Arithmetic Building Blocks: Data Paths, Adders, Multipliers, Shifters, ALUs, Designing
MODULE 4: Memory and Array structures, Memory Core, Memory Peripheral Circuitry. Design of RAM,
Subsystem design: ROM, EPROM, EEPROM and flash memory with examples. [10]

04-04-2026 2
 COURSE DESCRIPTION
MODULE 5: Sheet resistance, standard unit of capacitance, Estimation of delays in NMOS and CMOS
Sheet resistance and inverters, driving of large capacitive loads, super buffers, RC Delay Model, Elmore Delay,
Linear Delay Model, Parasitic Delay, Delay in Logic Gate . [8]
delay models:

Self-directed Simulation of MOSFET based logic circuits using LTSPICE

learning

04-04-2026 3
 Course Learning Outcomes

➢Describe the basic operation of MOS transistors.

➢Design combinational and sequential circuits using MOS devices.

➢Design the layout and discuss the MOS fabrication process.

➢Describe various issues involved in subsystem design.

➢Analyze the delay models and the circuit performance.

04-04-2026 4
 Reference Books

“CMOS DIGITAL INTEGRATED Digital Integrated Circuits – A Design

“Basic VLSI Design”, 3rd Ed., PHI
CIRCUITS:Analysis and Design” 3rd Ed. Perspective”, 2nd ed. by J. Rabaey, A.
By: Pucknell douglas [Link],
McGraw-Hill. BY:Sung-mo (Steve) Kang Chandrakasan, B. Nikolic
kamran

04-04-2026 5
 Reference Books

“CMOS VLSI Design:A Circuits and Systems

Amar Mukherjee, “Introduction to NMOS &
Perspective” 4th ed. Addison-Wesley
CMOS VLSI systems Design”, Prentice Hall,
By: Neil H. E. Weste, David Money Harris
1986.

04-04-2026 6
 Static CMOS
At every point in time (except during the switching transients), each gate output is connected to
either VDD or Vss via a low-resistance path.

➢ A static CMOS gate is a combination of two

networks, called the pull-up network (PUN)
and the pull-down network(PDN).
➢ The figure shows a generic N input logic gate
where all inputs are distributed to both the
pull-up and pull-down networks.
➢ When PUN is ON, output goes to logic '1’.
➢ When PDN is ON, output is going to logic
‘0’.
➢ They are in push-pull configuration.
➢ 2N transistors are required to implement the
static CMOS logic.
Full voltage swing

Full voltage swing

 Nmos = + parallel
. series

Pmos = + series
. parallel
 Pmos = + series Nmos = + parallel
. parallel . series

𝒇 = 𝑨. 𝑩 𝒇= 𝑨+𝑩 𝒇 = 𝑫 + 𝑨. (𝑩 + 𝑪 )
 Pmos = + series Nmos = + parallel
. parallel . series
𝒇 = 𝑨 + 𝑩 . 𝑪 + 𝑫 . (𝑬 + 𝑭 + 𝑮. 𝑯 )
PUN PDN
 Ratioed logic
➢ Also known as pseudo-NMOS logic.
➢ Ratioed logic is an attempt to reduce the number of transistors required to implement a given logic
function, at the cost of reduced robustness and extra power dissipation.
➢ In ratioed logic, the entire PUN is replaced with a single unconditional load device that pulls up the
output for a high output.
➢ Instead of a combination of active pull-down and pull-up networks, such a gate consists of an NMOS
pull-down network that realizes the logic function, and a simple load device.
➢ In pseudo NMOS, we have one PMOS which is connected to power supply VDD
and to GND in the input terminal.
➢ There is an pull down network where NMOS are been used depending on the
required NMOS the input varies.
➢ When compared to static CMOS (2N transistor) the number of input terminal in
pseudo NMOS will be N+1 (i.e n NMOS and one PMOS).
➢ PMOS transistor is always ON, because it is connected to GND.
➢ When input is 0, NMOS is OFF and o/p voltage will be 1, because PMOS is always
conducting.
➢ When input is 1, NMOS is ON and PMOS is always ON. So, there will a direct path
between VDD and GND. Since both are conducting, we will not get the output as
exact zero.
𝒇= 𝑨+𝑩+𝑪+𝑫 𝒇 = 𝑨. 𝑩. 𝑪. 𝑫

Nmos = + parallel
. series

out
𝒇 = 𝑨𝟏 + 𝑨𝟐 + 𝑨𝟑)(𝑩𝟏 + 𝑩𝟐)𝑪
 Dynamic Circuits
• Static CMOS logic with a fan-in of N requires 2N devices.
• Pseudo-NMOS logic style requires only N + 1 transistors to implement an N input logic
gate, but unfortunately it has static power dissipation.
• Dynamic logic requires N+2 transistors for N-input function with no static power
dissipation
• Dynamic circuit operation is divided into two modes
➢ precharge
➢ evaluation

Static CMOS inverter Pseudo-NMOS inverter Dynamic Logic inverter

Basic Operation
• Precharge
CLK = 0, the output node Out is precharged to VDD by the PMOS
transistor Mp and NMOS transistor Me is off, so that the pull-down
path is disabled
• Evaluation
CLK = 1, the precharge transistor Mp is off, and the evaluation
transistor Me is turned on. The output is conditionally discharged
based on the input values and the pull-down topology

CLK

Out
Note: In precharge, we don’t evaluate the o/p, it
is only meant for charging the load capacitance.

CL doesn’t get path to discharge

➢ Pre=0, i/p=1 → CLKP=ON, VP=ON, CLKN=OFF → O/P=VDD

➢ Eval=1, i/p=1, CLKP=OFF, VP=ON, CLKN=ON → O/P=0

➢ Pre=0, i/p=0 → CLKP=ON, VP=OFF, CLKN=OFF → O/P=VDD

➢ Eval=1, i/p=0, CLKP=OFF, VP=OFF, CLKN=ON → O/P=VDD

Example
• During precharge (CLK=0), the output is precharged to VDD
regardless of the input values since the evaluation device is
turned off.
• During evaluation (CLK=1), a conducting path is created
between Out and GND if (and only if) A·B+C is TRUE.
• Otherwise, the output remains at the precharged state of VDD.
• The following function is thus realized:

Out = CLK + (A  B + C)  CLK

Advantages:
➢ It has max voltage swing at o/p.
➢ It has only 1 pmos.
➢ It has faster switching speed.
➢ Circuit size is small.
➢ It has less capacitive loading compared to static CMOS.
Disadvantages:
➢ When o/p is logic '1', it stays in high impedance mode which is more effected by
noise.
➢ It requires precharging.
 Cascading of Dynamic Circuits

Note: In precharge, we don’t evaluate the o/p, it

is only meant for charging the load capacitance.

CL doesn’t find a path to discharge

➢ Pre=0, I/P=0 → CLKP1=ON, VP=OFF, CLKN1=OFF, CLKP2=ON, CLKN2=OFF →

O/P1=VDD, O/P2=VDD

➢ Eval=1, I/P =0 → CLKP1=OFF, VP=OFF, CLKN1=ON, CLKP2=OFF, CLKN2=ON →

O/P1=VDD, O/P2=0

➢ Pre=0, I/P =1 → CLKP1=ON, VP=ON, CLKN1=OFF, CLKP2=ON, CLKN2=OFF →

O/P1=VDD, O/P2=VDD

➢ Eval=1, I/P =1 → CLKP1=OFF, VP=ON, CLKN1=ON, CLKP2=OFF, CLKN2=ON →

O/P1=DISCHARGE, O/P2=UNDEFINED
The o/p is neither 1 or 0 i.e., undefined o/p

We get a false logic operation

Solution:

➢ Domino Logic CMOS

➢ NORA logic CMOS

➢ Retiming of clock
Domino Logic CMOS

Nmos= k+1+1=2
Pmos=1+1=2
Domino Logic is solving cascading but falling in the
problem of race around condition
➢ Pre=0, I/P=1 → CLKP1=ON, VP=ON, CLKN1=OFF, CLKP2=ON, CLKN2=OFF →
Vx1=VDD → CL1 charges to VDD → O/P1=0, Vx2=VDD → CL2 charges to VDD →
O/P2=0

➢ Eval=1, I/P =1 → CLKP1=OFF, VP=ON, CLKN1=ON, CLKP2=OFF, CLKN2=ON →

Vx1= CL1 starts to discharge=0→ O/P1=starts to charge=VDD, Vx2= CL1 starts to
discharge → O/P2=VDD

➢ Pre=0, I/P=0 → CLKP1=ON, VP=OFF, CLKN1=OFF, CLKP2=ON, CLKN2=OFF →

Vx1=VDD → CL1 charges to VDD → O/P1=0, Vx2=VDD → CL2 charges to VDD →
O/P2=0

➢ Pre=1, I/P=0 → CLKP1=OF, VP=OFF, CLKN1=ON, CLKP2=OFF, CLKN2=ON →

Vx1=VDD → CL1 charges to VDD → O/P1=0, Vx2=VDD → CL2 charges to VDD →
O/P2=0
 Pass Transistor Logic
➢The role of a pass transistor is to transfer an input signal, unaltered, to the
output node when the gate is on. When the gate is turned off, the output
enters the high-Z state and holds its previous value.
➢This type of logic gate has an input, an output, and a third terminal that
controls whether the device is on or off.
➢Used as an alternative to static CMOS.
➢Ratio-less logic
 B=control input
T1 T2 A=input
F=output

ഥ = 𝟎 → o/p=0
➢ When control i/p B=0, irrespective of A value, the o/p=0 → 𝑩
➢ When B=1, o/p=A → i/p=A
➢ In other words,
o B=1, T1=ON, T2=OFF
o B=0,T1=OFF,T2=ON
 T1 T2

➢ When control i/p B=1, irrespective of A value, the o/p=1

➢ When B=0, o/p=A → i/p=A
 ഥ → i/p = 𝑨
➢ When control i/p B=1, irrespective of A value, the o/p= 𝑨 ഥ
➢ When B=0, o/p=A → i/p=A
➢ When control i/p B=1, o/p=A → i/p=A
ഥ → i/p = 𝑨
➢ When B=0, irrespective of A value, the o/p= 𝑨 ഥ
2:1 MUX using pass transistor logic

S Z
0 A
1 B
4:1 MUX using pass transistor logic
 Transmission Gate Logic
➢ Deals with the voltage-drop problem
➢ Builds on the complementary properties of NMOS and PMOS transistors:
➢ NMOS devices pass a strong 0 but a weak 1
➢ PMOS transistors pass a strong 1 but a weak 0

➢ The transmission gate combines the best of both device flavors by placing a
NMOS device in parallel with a PMOS device
Circuit
➢ The control signals C and 𝐶ҧ are complementary

➢ It acts as a bidirectional switch controlled by the gate signal C

➢ When C =1, both MOSFETs are on, allowing the signal to pass through the gate
➢ When C = 0 places both transistors in cut-off, creating an open circuit between
nodes A and B Symbol
Examples

AND NAND

OR NOR
Examples

EX-OR 2:1 MUX

EX-NOR

S Z
0 A
1 B
4:1 MUX using pass transistor logic

𝑺𝟏

𝑺𝟎

𝑺𝟏

𝑺𝟎

𝑺𝟏
Boolean logic expression conversion to transmission gate: F=AB+BC+AC

A B C AB BC AC F
0 0 0 0 0 0 0
0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
C
0 1 1 0 1 0 1
1 0 0 0 0 0 0
C
1 0 1 0 0 1 1
1 1 0 1 0 0 1
1
1 1 1 1 1 1 1

A B F
Simplified
truth table: 0 0 0
0 1 C
1 0 C
1 1 1
 Dual Rail Domino Logic
➢ Dual-rail domino gates accept both true and complementary inputs and compute both
true and complementary outputs.
➢ • Dual-rail domino gates encode each signal with a pair of wires.
➢ • The input and output signal pairs are denoted with sig_h and sig_l, respectively.
Dual Rail Domino Logic

AND/NAND XOR/XNOR
 Complementary Pass Transistor Logic (CPL):
➢ In CPL, i/p’s are applied both in true and complement form, o/p’s are also evaluated in both true and
complement form, using pass transistor logic.
➢ Also known as Differential Pass Transistor Logic (DPL)

CPL-AND GATE:

ഥ
𝑭
Complementary Pass Transistor Logic (CPL):
CPL-OR GATE:

B
F
A

ഥ
𝑩
ഥ ഥ
𝑭
𝑨
Complementary Pass Transistor Logic (CPL):
CPL-XOR GATE:

ഥ
𝑨
F
A

ഥ
𝑭
ഥ
𝑨
Complementary Pass Transistor Logic (CPL):
ADVANTAGES:
•Don’t need extra inverters
•Still static
•Design is modular
• All gates use the same topology,
• Only the inputs are permuted.
•Simple XOR → attractive for structures like adders
•Fast (assuming small number of transistors in series)

DISADVANTAGES:
Additional routing overhead for complementary signals
Still have static power dissipation problems
Signal gradually degrades after passing through a number of transistors (weak 1)
Cascode Voltage Switch Logic (CVSL):
➢ Seeks benefit of ratioed ckt without static power consumption.
➢ Use both true and complementary i/p signals and compute both true and complementary o/p’s using NMOS
PD n/w’s.

CVSL-AND: CVSL-XOR:
Bi-CMOS Inverter Circuits:
➢ The very approach of BiCMOS is to exploit the advantageous characteristics of bipolar and
CMOS technologies.
➢ Hence in BiCMOS design, the rational approach is to use MOS switches to perform the
logic function and bipolar transistors to drive the output loads.
➢ The basic logic element here too is the inverter and a simple BiCMOS inverter circuit can be
imagined like the one shown in Fig. below.
 Bi-CMOS Inverter Circuits:
➢ The inverter circuit consists of two bipolar transistors T₁ and T₂, one nMOS transistor T₃ and one pMOS transistor T₄.
Both the MOS devices are enhancement mode devices. The functioning of the circuit is as follows:
a) With 𝑉𝑖𝑛 at logic 0 i.e. 0 volts (GND), 𝑇3 is off which keeps 𝑇1 non-conducting. However 𝑇4 is on and supplies base current
to 𝑇2 which conducts and acts as a current source to charge the load 𝐶𝐿 toward +5 volts (𝑉𝐷𝐷 .)The output 𝑉𝑜𝑢𝑡 goes to +5 V
less the base to emitter drop 𝑉𝐵𝐸 of 𝑇2 .
b) When 𝑉𝑖𝑛 =logic 1 i.e. +5 V (𝑉𝐷𝐷 ,)𝑇4 is off so that 𝑇2 will be non-conducting. But 𝑇3 is on and supplies current to base of
𝑇1 which conducts and acts as a current sink to the load 𝐶𝐿 which discharges through it to 0 volts (GND). The 𝑉𝑜𝑢𝑡 falls to 0
volts plus the saturation voltage 𝑉𝐶𝐸𝑠𝑎𝑡 between collector and emitter of 𝑇1 .
c) Charging and discharging of load 𝐶𝐿 is very fast because transistors 𝑇1 and 𝑇2 present low impedances when turned on
into saturation.
➢ The output logic levels will approximate the rail voltages since 𝑉𝐶𝐸𝑠𝑎𝑡 is
quite small and 𝑉𝐵𝐸 equals 0.7 volts approximately. The inverter offers a
low output impedance and a high input impedance. It occupies a
relatively small area but still has a high current drive capability. The
inverter circuit has high noise margins.
Bi-CMOS Inverter Circuits:
• However there is a constant D.C. path between the rails through T₃ and T₁ which allows a
significant static current flow whenever 𝑉𝑖𝑛 =logic 1. This is not a desirable arrangement. Also,
there is another problem, that there is no discharge path for current from the base of either npn
transistor when it is being turned off. This adversely affects the speed of action of the circuit.

• The problem of the D.C. path through T₁ and T₃ is eliminated in an improved inverter circuit
shown in Fig. 2.42. However the output voltage swing gets reduced because the output cannot
go below the base to emitter voltage 𝑉𝐵𝐸 of transistor T₁.
Bi-CMOS Inverter Circuits:
Bi-CMOS Inverter Circuits:
Bi-CMOS Inverter Circuits:
SEQUENTIAL CIRCUIT USING CMOS
SR latch using 2 input NAND CMOS logic
SEQUENTIAL CIRCUIT USING CMOS
SR latch using 2 input NOR CMOS logic
SEQUENTIAL CIRCUIT USING CMOS
JK FF using 2 input CMOS logic
PSEUDO NMOS ZP.U/ZP.D DERIVATION
Zpu=effective pull-up impedance of PMOS, Zpd=effective pull-down impedance of NMOS
Since current is inversely proportional to effective impedance,
1 1
𝐼𝑝 ∝ , 𝐼𝑛 ∝
𝑍𝑝𝑢 𝑍𝑝𝑑
and in MOS form,
𝑊𝑛 𝑊𝑝
𝛽𝑛 = 𝜇𝑛 𝐶𝑜𝑥 , 𝛽 = 𝜇𝑝 𝐶𝑜𝑥
𝐿𝑛 𝑝 𝐿𝑝
with
𝑍𝑝𝑢 𝛽𝑛
≈
𝑍𝑝𝑑 𝛽𝑝

If A= 𝑽𝒊𝒏 = 𝑽𝑶𝑯 ≈ 𝑽𝑫𝑫

Then:
•NMOS is ON
•PMOS is also ON
•output settles to 𝑉𝑂𝐿 ≈ 0, very low, so 𝑉𝐷𝑠𝑛 ~𝑙𝑜𝑤
•PMOS in saturation, NMOS in linear
PSEUDO NMOS ZP.U/ZP.D DERIVATION
At steady state,
𝐼𝑛 = 𝐼𝑝
At low output, NMOS is in linear region:
2
𝑉𝑂𝐿
𝐼𝑛 = 𝛽𝑛 𝑉𝐷𝐷 − 𝑉𝑇𝑛 𝑉𝑂𝐿 −
2
PMOS is in saturation:
𝛽𝑝 2
𝐼𝑝 = 𝑉 −∣ 𝑉𝑇𝑝 ∣
2 𝐷𝐷
Equating,
2 𝛽𝑝
𝑉𝑂𝐿 2
𝛽𝑛 𝑉𝐷𝐷 − 𝑉𝑇𝑛 𝑉𝑂𝐿 − = 𝑉 −∣ 𝑉𝑇𝑝 ∣
2 2 𝐷𝐷
Hence the pull-down ratio is
2
𝛽𝑛 𝑉𝐷𝐷 −∣ 𝑉𝑇𝑝 ∣
= 2
𝛽𝑝 2 𝑉𝐷𝐷 − 𝑉𝑇𝑛 𝑉𝑂𝐿 − 𝑉𝑂𝐿
or, in impedance form,
2
𝑍𝑝𝑢 𝑉𝐷𝐷 −∣ 𝑉𝑇𝑝 ∣
= 2
𝑍𝑝𝑑 2 𝑉𝐷𝐷 − 𝑉𝑇𝑛 𝑉𝑂𝐿 − 𝑉𝑂𝐿
This tells how much stronger the pull-down NMOS must be than the always-ON PMOS to obtain
the required low output.
ZP.U/ZP.D DERIVATION FOR PSEUDO NMOS DRIVEN BY ANOTHER PSEUDO NMOS

Inverter 1 Inverter 2

A=𝑽𝒊𝒏 = 𝑽𝑶𝑯 ≈ 𝑽𝑫𝑫 , B= 𝑽𝑶𝑳 ≈ 𝟎 B=𝑽𝒊𝒏 = 𝑽𝑶𝑳 ≈ 𝟎

Then: Then:
•NMOS is ON •NMOS is OFF(~weakly ON), 𝑽𝑫𝒔𝒏 ~𝑯𝒊𝒈𝒉
•PMOS is also ON •PMOS is also ON, 𝑽𝑺𝑫𝑷 = 𝑽𝑫𝑫 − 𝑽𝑶𝑯 ~𝑳𝒐𝒘
•output settles to 𝑉𝑂𝐿 ≈ 0, very low, so 𝑉𝐷𝑠𝑛 ~𝑙𝑜𝑤 •NMOS in saturation, PMOS in linear
•PMOS in saturation, NMOS in linear
ZP.U/ZP.D DERIVATION FOR PSEUDO NMOS DRIVEN BY ANOTHER PSEUDO NMOS

the NMOS is in saturation,

𝛽𝑛
𝐼𝑛 = 𝑉𝑂𝐿 − 𝑉𝑇𝑛 2 if 𝑉𝑂𝐿 > 𝑉𝑇𝑛
2
If 𝑉𝑂𝐿 < 𝑉𝑇𝑛 ,NMOS is OFF and ideally 𝑉𝑂𝐻 = 𝑉𝐷𝐷 .
For the PMOS, 𝑉𝑆𝐷,𝑝 = 𝑉𝐷𝐷 − 𝑉𝑂𝐻 ,so in linear region
𝑉𝐷𝐷 − 𝑉𝑂𝐻 2
𝐼𝑝 = 𝛽𝑝 𝑉𝐷𝐷 −∣ 𝑉𝑇𝑝 ∣ 𝑉𝐷𝐷 − 𝑉𝑂𝐻 −
2
Equating 𝐼𝑝 = 𝐼𝑛 ,
𝑉𝐷𝐷 − 𝑉𝑂𝐻 2 𝛽𝑛 2
𝛽𝑝 𝑉𝐷𝐷 −∣ 𝑉𝑇𝑝 ∣ 𝑉𝐷𝐷 − 𝑉𝑂𝐻 − = 𝑉 − 𝑉𝑇𝑛
2 2 𝑂𝐿
Hence the pull-up ratio is
𝛽𝑝 𝑉𝑂𝐿 − 𝑉𝑇𝑛 2
=
𝛽𝑛 2 𝑉𝐷𝐷 −∣ 𝑉𝑇𝑝 ∣ 𝑉𝐷𝐷 − 𝑉𝑂𝐻 − 𝑉𝐷𝐷 − 𝑉𝑂𝐻 2
or equivalently,
𝑍𝑝𝑢2 2 𝑉𝐷𝐷 −∣ 𝑉𝑇𝑝 ∣ 𝑉𝐷𝐷 − 𝑉𝑂𝐻 − 𝑉𝐷𝐷 − 𝑉𝑂𝐻 2
=
𝑍𝑝𝑑2 𝑉𝑂𝐿 − 𝑉𝑇𝑛 2

This is the condition for obtaining the required high output when the input “0” is actually 𝑉𝑂𝐿 ,not
0.
ZP.U/ZP.D DERIVATION FOR PSEUDO NMOS DRIVEN BY ANOTHER PSEUDO NMOS

2
𝑍𝑝𝑢1 𝑉𝐷𝐷 −∣𝑉𝑇𝑝 ∣
Inverter1, = 2
𝑍𝑝𝑑1 2 𝑉𝐷𝐷 −𝑉𝑇𝑛 𝑉𝑂𝐿 −𝑉𝑂𝐿

𝑍𝑝𝑢2 2 𝑉𝐷𝐷 −∣𝑉𝑇𝑝 ∣ 𝑉𝐷𝐷 −𝑉𝑂𝐻 − 𝑉𝐷𝐷 −𝑉𝑂𝐻 2

Inverter2, =
𝑍𝑝𝑑2 𝑉𝑂𝐿 −𝑉𝑇𝑛 2

Homework: Explain the significance of these ratios in determining the output logic levels and power dissipation.
Transistor sizing in CMOS logic gates
• Sizing is the problem of selecting the W/L values for the pull-up and
pulldown transistors to satisfy a set of design specifications
• Once a CMOS circuit has been generated, the only significant step
remaining in the design is to decide on W/L ratios for all devices.
• For the basic inverter design we denote
(W/L)p = 2 to 4 times of (W/L)n
• We do so because the mobility of electrons 𝜇𝑛 is 2 to 4 times that of
holes 𝜇𝑝 .
• Matching is used to equal transconductance parameters for the two
devices
(W/L)p = 𝜇𝑛 /𝜇𝑝 x (W/L)n

61
Transistor sizing in CMOS logic gates

• In series connection, their individual resistances get added up while the net
W/L ratio is equal to 1/n times that of the individual device
• In parallel connection, the equivalent W/L ratio is equal to ‘n’ times that of
the individual device (n= no. of transistors connected)
• Design rule: Select individual W/L ratios for all transistors in a logic gate
so that
➢ PDN should be able to provide capacitor discharge current at least equal
to NMOS transistor with W/L=n
➢ PUN should be able to provide capacitor charging current at least equal to
that of a PMOS transistor with W/L=p
• This will guarantee a worst-case gate delay equal to that of the basic inverter

62
 Transistor sizing in CMOS logic gates
Example: Four input NOR
• Here the worst case(the lowest current) for the PDN is
obtained only when one of the transistors is conducting.
• We therefore select the W/L of each NMOS transistor to be
equal to that of the NMOS of the basic inverter, namely n.
• For the PUN however, the worst-case situation is when all
the inputs are low and the four series PMOS transistors are
conducting.
• The equivalent W/L will be one-quarter of that of each
PMOS device, we should select the W/L ratio of each
PMOS transistor to be 4 times that of Qp of the basic
inverter, that is 4p

63
Static latches and registers:
SEQUENTIAL LOGIC Introduction
• Combinational logic circuits: output only depends on the current input values
• Sequential logic circuits: output depends on both the current and previous input values
• Sequential circuit remembers some of the past history of the system—it has memory
• All registers are under control of a single global clock
• Registers can be positive edge-triggered or negative edge-triggered

64
Static latches and registers:
SEQUENTIAL LOGIC
Latches and Flip-Flops
• Latches and Flip-Flops are basic building blocks of sequential circuits
• Receive a clock(CLK), and a data input (D), and produce an output (Q)
• A D latch is transparent when CLK = 1, Q follows D
• opaque when CLK = 0, Q retains its previous value and ignores changes in D.
• An edge-triggered flip-flop copies D to Q on the rising edge of CLK and remembers
its old value at other times.

65
Static latches and registers:
SEQUENTIAL LOGIC Latches
• D latch built from a 2-input multiplexer and two inverters
• The D latch is also known as a level-sensitive latch because the state of the output is
dependent on the level of the clock signal
• By inverting the control connections to the multiplexer, the latch becomes negative-
level-sensitive

symbol D latch positive-level-sensitive latch

66
Static latches and registers:
SEQUENTIAL LOGIC Flip-Flops
• Latches and Flip-Flops are basic building blocks of sequential circuits
• It is a combination of one negative-sensitive latch and one positive-sensitive latch
• The first latch stage is called the master and the second is called the slave
• Clock transition — 0-to-1 for a positive edge-triggered, and 1-to-0 for a negative
edge-triggered

symbol D flip-flop Positive edge triggered D flip flop 67

Static latches and registers:
Static Latches and Flip-Flops
The Bistability Principle:
• Bistable circuit- two stables states 1 and 0 ; uses positive feed back
• Two inverters connected in cascade
• With no triggering, the circuit remains in a single state and hence remembers a value.
• A trigger pulse must be applied to change the state of the circuit
• Another names for a bistable circuit is flip-flop and edge-triggered register

Two cascaded inverters

Voltage-transfer characteristics

68
Static latches and registers:
SEQUENTIAL LOGIC
Loop gain >
Static Latches and Flip-Flops 1
The Bistability Principle:
• Cross-coupled inverter pair is biased at point C; A and B are stable
operation points
• A small deviation from C, possibly caused by noise, is amplified
and regenerated around the circuit loop
• A small deviation 𝜹 is applied to Vi1,is amplified by the gain of the
inverter and again amplified when it applied to the second inverter.
• The bias point moves away from C until one of the operation points Loop gain <
A or B is reached. That means C is an unstable operation point 1
• The chance is indeed very small that the cross-coupled inverter pair
is biased at C and stays there
• Operation points with this property are termed metastable

69
Static latches and registers:
SEQUENTIAL LOGIC
Static Latches and Flip-Flops
SR Flip Flops
• SR(set-reset) flip-flop is similar to the cross-coupled inverter pair with NOR gates
replacing the inverters.
• The second input of the NOR gates is connected to the trigger inputs (S and R), that
make it possible to force the outputs Q and Q to a given state.

NOR-based NAND-based

Schematic diagram Logic symbol Characteristic table 70

 Static latches and registers:

Static Latches and Flip-Flops Clocked SR flip-flop —

a level-sensitive positive latch
SR Flip Flops
• It consists of a cross-coupled inverter pair, plus 4 extra transistors to drive
the flip-flop from one state to another and to provide clocked operation
• Q and 𝑄ത are set to 0 and 1, and a pulse is applied at node S,
• In the first phase of the transient, node 𝑄ത is being pulled down by
transistors M5 and M6.
• Since node Q is initially low, the PMOS device M2 is on while M1 is off.
• The transient response is hence determined by the pseudo-NMOS inverter
formed by (M5-M6) and M2.
• Once 𝑄ത reaches the switching threshold of the CMOS inverter M3-M4,
this inverter reacts and the positive feedback comes into action, turning M2
off and M1 on.
• This accelerates the pulling down of node 𝑄. ത

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 SEQUENTIAL LOGIC

Static Latches and Flip-Flops

Multiplexer-Based Latches

• Common technique to construct the laches is using

transmission gate multiplexers.

• Multiplexer based latches can provide similar functionality

to the SR latch

• In negative latch, the D input is selected when clock is low,

and the output is held (using feedback) when clock is high

• In positive latch, the D input is selected when clock is high,

and the output is held (using feedback) when clock is low.

Positive latch build using transmission gates

72
 Static Latches and Flip-Flops
Master-Slave Edge-Triggered Register Positive edge-triggered register based on a
master-slave configuration
• Consists of cascading a negative latch (master) with a positive latch (slave)

• On the low phase of the clock, the master stage is transparent, and the D is
passed to the master stage output, QM. During this, the slave stage is in the
hold mode, keeping its previous value using feedback.

• On the rising edge of the clock, the master slave stops sampling the input, and
the slave stage starts sampling.

• On the high phase of the clock, the slave stage samples the output of the
master stage (QM), while the master stage remains in a hold mode. Since QM is
constant during the high phase of the clock, the output Q makes only one
transition per cycle

• The value of Q is the value of D right before the rising edge of the clock,
achieving the positive edge-triggered effect

73
Static Latches and Flip-Flops
Master-Slave Edge-Triggered Register transistor-level implementation

Master-slave positive edge-triggered register using multiplexers

74
 Dynamic Latches and Flip-Flops

Introduction

• Complexity is the major disadvantage of the static gate

• In dynamic logic — charge stored on a capacitor can be used to represent a logic
• The absence of charge denotes a 0, and presence stands for a stored 1.
• A stored value kept for a limited amount of time, (range of milliseconds) due to charge leakage
in capacitor
• To preserve signal integrity, a periodic refresh of its value is necessary. Hence the name
dynamic storage
• Reading the value of the stored signal from a capacitor without disrupting the charge requires
the availability of a device with a high input impedance

75
 Dynamic Latches and Flip-Flops

Dynamic Transmission-Gate Edge-triggered Registers

• It is based on the master-slave concept

• When CLK = 0, the input data is sampled on storage node 1, During this period, the slave stage is in a hold
mode, with node 2 in a high-impedance state
• On the rising edge of clock, the transmission gate T2 turns on, and the value sampled on node 1 right before the
rising edge propagates to the output Q Node 2 now stores the inverted version of node 1
• During the high phase of the clock, node 1 is stable since the first transmission gate is turned off
• This implementation requires only 8 transistors

76
Dynamic Latches and Flip-Flops
Dynamic Transmission-Gate Edge-triggered Registers
Clock overlap:

• During the 0-0 overlap period, input-output path exists through the NMOS of T1 and the PMOS
of T2. This is known as a race condition
• The output Q can change on the falling edge if the overlap period is large- an undesirable effect
for a positive edge-triggered register
• During the 1-1 overlap region, input-output path exists through the PMOS of T1 and the NMOS
of T2.
• The 0-0 overlap period constraint is given as:
• The constraint for the 1-1 overlap is given as:
77
Dynamic Latches and Flip-Flops

The 𝐂 𝟐 MOS Register

• It based on a master-slave concept insensitive to
clock overlap as long as the rise and fall times of
the clock edges are sufficiently small
• operates in two phases
1. CLK = 0: The first tri-state driver is turned on, and
the master stage acts as an inverter. The master
stage is in evaluation mode, and the slave stage in
hold mode. Both transistors M7-M8 off, decoupling
the output from the input. The output Q retains its
previous value stored on the output capacitor CL2.
2. CLK = 1: The master stage section is in hold mode
(M3-M4 off), while the second section evaluates (M7-
M8 on). The value stored on CL1 propagates to the
output node through the slave stage which acts as an C 2 MOS master-slave
inverter. positive edge-triggered register
78
Dynamic Latches and Flip-Flops

The 𝐂 𝟐 MOS Register

C2MOS D-FF during overlap periods

(0-0) overlap (1-1) overlap

79
 Dynamic Latches and Flip-Flops

Dual-edge Registers
• Used to sample the input on both edges
• Edge-triggered registers, sample the input data on only one of the
clock edges (rising or falling)
• lower frequency clock (half of the original rate) distribution for
the same functional throughput, and power savings in the clock
distribution network are the advantages.
• It consists of two parallel master slave based edge-triggered
registers, whose outputs are multiplexed using the tri-state drivers.
• The slave latches operate in a complementary fashion — only one
of them is turned on during each phase of the clock.

C 2 MOS based dual-edge triggered register

80
Dynamic Latches and Flip-Flops

True Single-Phase Clocked Register (TSPCR)

True Single Phase Latches

• uses a single clock

• A register can be constructed by cascading positive and negative latches.
• The clock load is similar to a conventional transmission gate register, or
C2MOS register
• 12 transistors are required
81
Dynamic Latches and Flip-Flops

True Single-Phase Clocked Register (TSPCR)

• TSPC offers an additional advantage: the possibility of
embedding logic functionality into the latches
• This reduces the delay overhead associated with the Example: AND latch
latches.

Including logic into the latch

82
Dynamic Latches and Flip-Flops

True Single-Phase Clocked Register (TSPCR)

Simplified TSPC latch

Positive edge-triggered register TSPC

Positive Latch

Negative Latch

83
 Sense-Amplifier Based Flip Flops
• A sense amplifier structure is used to implement an edge-
triggered Register
• Sense-amplifier circuits accept small input signals and amplify
them to generate rail-to-rail swings
• uses a precharged front-end amplifier that samples the
differential input signal on the rising edge of the clock signal
• The outputs of front-end are fed into a NAND cross-coupled
SR FF that holds the data and guarantees that the differential
outputs switch only once per clock cycle
• The differential inputs in this implementation don’t have to
have rail-to-rail swing and hence this register can be used as a
receiver for a reduced swing differential bus

Positive edge-triggered
register based on sense-amplifier

84
 Sense-Amplifier Based Flip Flops

The need for the shorting transistor M4

85
NORA-CMOS
• The latch-based pipeline circuit can also be implemented using C 2 MOS latches
• A C2 MOS-based pipelined circuit is race-free as long as all the logic functions F
(implemented using static logic) between the latches are non-inverting

Pipelined datapath using 𝐂 𝟐 MOS latches

86
 NORA-CMOS

• During a (0-0) overlap between CLK and 𝐶𝐿𝐾, all C 𝟐 MOS

latches, simplify to pure pull-up networks
• F is replaced by a single, static CMOS inverter
• Similar considerations are valid for the (1-1) overlap
• Based on this concept, NORA-CMOS logic circuit was
conceived
• It combines C 𝟐 MOS pipeline registers and NORA dynamic
logic function blocks.
Potential race condition during (0-0)
• Each module consists of a block of combinational logic overlap in C𝟐 MOS-based design
(mixture of static and dynamic), followed by a C 𝟐 MOS latch.
• Logic and latch are clocked simultaneously in either
evaluation, or hold (precharge) mode.
• A block that is in evaluation during CLK = 1 is called a CLK-
module, while the inverse is called a 𝐶𝐿𝐾-module

87
NORA-CMOS

Examples of NORA CMOS Modules

Operation modes for NORA logic modules

88
Schmitt Trigger Circuit

• A Schmitt trigger properties:

1. It responds to a slowly changing input waveform with a fast
transition time at the output
2. The voltage-transfer characteristic of the device displays
different switching thresholds for positive- and negative-going
schematics symbol
input signals
• The difference between the two switching thresholds VM+ and
VM- is called hysteresis voltage
• Schmitt trigger turns a noisy or slowly varying input signal into a
clean digital output signal

Noise suppression using a Schmitt trigger voltage-transfer characteristic

89
Schmitt Trigger Circuit

CMOS Implementation
• The switching threshold of a CMOS inverter is determined by the (kn/kp) ratio between
the NMOS and PMOS transistors
• Increasing the ratio results in a reduction of the threshold, while decreasing it results in
an increase in VM.
Alternate CMOS Schmitt trigger
CMOS Schmitt trigger

90