1.

Introduction to 8051 Microcontroller

Microcontroller is a single chip microcomputer which consists of CPU, Memory, I/O ports,
timers and other peripherals. The difference between microprocessor and microcontroller is
microprocessor is a single integrated CPU whereas microcontroller is single chip microcomputer.
The world leaders of manufacturing of microprocessor and microcontroller are Intel, Motorola,
IBM, Cyrix etc. Here we have to focus on microcontroller 8051.

In 1981 Intel Corporation introduced an 8-bit microcontroller called [Link]

microcontroller had 128 bytes of RAM, 4K bytes of on-chip ROM, two timers, one serial port
and four ports (each 8bit wide) all on a single chip. It is an 8-bit processor means it can
process 8 bits of data at a time. It has total of four I/O ports, each 8-bit wide.

Features of 8051

Feature Quantity

ROM 4K bytes
RAM 128bytes
Timer 2
I/O pins 32
Serial Port 1
Interrupt sources 6

2. Architecture of 8051

Fig 4.1 shows a simplified architecture for the internal Hardware. Fig 4.2 shows an overview of
the internal hardware architecture of the 8051/8031 microcontrollers.

The CPU has the controlled and sequencing logic circuits with signals as in a microprocessor.

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The MCU has, besides the CPU, ROM, Interrupt control circuit, internal timing devices (timers
T0, T1), serial interface (SI), RAM and special function registers (SFRs). It has four ports P0,
P1, P2 and P3 as shown in Fig. 4.1. The overview block diagram of 8051 is depicted in Fig.4.2.

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Description of Sub units in the hardware architecture and meaning of the symbols

PC- Program Counter

A 16 bit register to hold the program memory address of the instruction being currently fetched.
Increments continuously to point to the next instruction, unless there is change in the program
flow path.

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DPTR- Data Pointer register
A 16-bit register to hold the external data memory address of the data being currently fetched or
to be fetched in indirect addressing mode.
A-Accumulator
An 8-bit register to save an operand for an ALU or data transfer operation and is also used to
accumulate result after an ALU operation.
B- B register
An 8-bit register to save a second operand for the ALU and also accumulate the result after ALU
operation for multiplication or division.
ALU- Arithmetic logic unit
A unit to perform an arithmetic and logical operation at an instance as per the instruction to be
executed and give result.
PSW- Processor Status Word
A register to save the bits of different flags.
P0- Port P0
An 8-bit port for the I/Os in a single chip mode and for the data bus-cum- lower order address in
the expanded mode.
P2- Port2
An 8-bit port for the I/Os in a single chip mode and for the higher order address in the expanded
mode
P1- Port1
An 8-bit port for the I/Os in a single chip mode and a few device operations related bits in certain
8051 family variants in the expanded mode.
P3- Port3
An 8-bit port for the I/Os in a single chip mode and the serial interface (SI) bits , timer T0 and T1
inputs, Interrupts INT0 and INT1 inputs , RD and WR for the memory read-write in the expanded
mode.
SI- Serial Interface Device
Serial device for full duplex UART serial I/O operations through the set of two pins of P3, RxD
and TxD and for the half duplex synchronous communication of the bits through the same set of
pins, DATA and CLOCK.
T0 and T1- Timers T0 and T1
Timing devices in 8051 family using four registers TH1, TH0, TL1, and TL0.
SFRs- Special Function Registers
All registers t h e SP, PSW, A, B, IE, IP, SCON, TCON, SMOD, SBUF, PCON, , TL0, TH0,
TL1, TH1 are called SFRs
ROM- Read only Program memory
Masked ROM EPROM or flash EEPROM of 4kB in 8051 classic family.
Internal RAM- Internal Random Access Memory

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For read and write the 128 B memory is indirectly and directly addressable in address space.
Register banks- Four set of registers
Four register banks each of 8 registers and these are also part of the internal RAM.
XTAL1 and XTAL2 – Pins to the Crystal
Pins to the crystal in the oscillator circuit, usually 12 MHz
EA - External Enable
To enable use of external memory addresses to external ROM.
RST- Reset Pin
Reset circuit input and also reset few output cycles to the external peripheral devices to let
processor reset and synchronize with devices.
INT 0 and INT 1- Interrupt pins
Active low two external interrupts.
VCC and GND- Voltage supply pi and ground pin
For 5 V supply and ground connections respectively.
PSEN - Program Store Enable
Active low when reading the external program memory bytes
RD -Read
Active low when reading the byte from external data memory.
WR - Write
Active low when writing the byte to external data memory

3. Pin Configuration

Fig 4.3 shows 40 pin signals in an 8051 series microcontroller. It shows the I/O pins, P0.0 to
P0.7, P1.0 to P1.7, P2.0 to P2.7 and P3.0 to P3.7. It shows other remaining 8 pins, VDD, VSS,
XTAL1 and XTAL2, RST, ALE, EA and PSEN .

Vcc - Pin 40 provides supply voltage to the chip. The voltage source is +5V

GND- Pin 20 is the ground.

XTAL1 and XTAL2- 8051 has an on-chip oscillator but requires an external clock to run it.
Most upon a quartz crystal oscillator is connected to inputs XTAL1 (pin 19 and XTAL@ (pin-
18) The quartz crystal oscillator connected also needs two capacitors of 30 pF. If frequency
source other than crystal oscillator such as TTL oscillator will be connected to XTAL1 and
XTAL2 is left unconnected.

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 Fig. 4.3 8051 Pin diagram

RST (I/P)- Pin 9 is the RESET pin and is active high (normally low). Upon applying high pulse
to this pin the microcontroller will reset and terminate all activities. This often referred to as
power on reset. Once it is activated the contents of all registers become zero except the content
of SP which is 07H.

EA (External Access) - This pin is connected to VCC for those have on-chip ROM otherwise
it is grounded incase 8031 and 8032. Because in case of 8031 and 8032 there is no on-chip
ROM.

PSEN (o/p) (Program Store Enable)- In case of 8031 based system in which an external ROM
holds the program code . To read the code this pin is connected to OE pin of ROM chip.

AlE (o/p) (address Latch enable)- When 8051is connected to external memory, both address
and data are transferred through port 0 pins. ALE signal is active high used to demultiplex
address/data bus.

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P0, P1, P2 and P3 are explained in port section.

4. Memory Organization

The 8051 micro controller has a total of 128 bytes of RAM. The 128 bytes of RAM inside the
8051 are assigned addresses 00H to 7FH and divided into three different groups as follows.

1. A total of 32 bytes from location s 00H to 1FH are set aside for register banks and the
stacks.
2. A total of 16 bytes from locations 20H to 2FH are set aside for bit addressable read/write
memory.
3. A total of 80 bytes from locations 30H to 7FH are used for read and write storage, or what is
normally called a scratch pad. These 80 locations of RAM are widely used for the purpose of
storing data and parameters by 8051 programmers.

Register banks in the 8051

As mentioned, a total of 32 bytes of RAM are set aside for the register banks an stack.
These 32 bytes are divided into 4 banks of registers in which each bank has 8 registers, R0-R7.
RAM locations from 0 to 7 are set aside for bank 0 of R0-R7 where R0 is RAM location 0 , R2
is location 2 and so on. The second bank of registers R0-R7 start RAM location 08 and goes to
location 1FH. The third bank of R0-R7 starts at memory location 10 H and goes to location
17H. finally RAM location 18H to 1FH are set aside for the fourth bank of R0-R7. The
following shows how 32 bytes are allocated into 4 banks.

Fig. 4.6 RAM allocation in the 8051 Fig. 4.7 RAM Allocation in the 8051

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External Program Memory

Fig.4.8 shows a layout of the external code memory addresses in the classic 8051 architecture.

1.
When the the EA =0 at RESET, the PC (MCU program counter ) starts from 0x0000
and accesses the external addresses from the memory. Memory addresses are between
0x0000 and 0xFFFF.
2.
When the EA =1 at RESET, the PC starts from 0x0000 for banks0 and 1 and accesses
the internal addresses and the 0x1000 onwards from the external addresses from the
memory.

Fig. 4.8 Code Memory (Program memory)

External Data Memory

Fig. 4.9 shows a layout of the external data (X-DATA) memory addresses in the classic 8051
architecture. It can be accessed through the indirect addressing mode used.

Fig. 4.9 Memory for X-Data in classic 8051

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5. Special Function Registers (SFR)

For a programmer, the SFRs are at the directly addressable space special registers. These can
be accessed by their names or by their addresses. The SFRs have addresses between 80H and
FFH. These addresses are above 80H, since the addresses 00 to 7FH are addresses of RAM
memory inside the [Link] all the address space of 80 to FF is used by the SFR. The unused
locations 80H to FFH are reserved and must not be used by the 8051 programmer. The meaning
of each symbol is enlisted in Table 4.1.

Table 4.1 Special Function Register (SFR) Address.

Symbol Name Address
ACC* Accumulator 0E0H
B* B-register 0F0H
PSW* Program Status Word 0D0H
SP Stack Pointer 81H
DPTR Data Pointer 2 bytes
DPL lower byte 82H
DPH higher byte 83H
P0* Port0 80H
P1* Port1 90H
P2* Port2 0A0H
P3* Port3 0B0H
IP* Interrupt Priority Control 0B8H
IE* Interrupt Enable Control 0A8H
TMOD Timer /counter mode control 89H
TCON* Timer/counter control 88H
T2CON* Timer/counter 2 control 0C8H
T2MOD Timer /counter mode control 0C9H
TH0 Timer/counter0 high byte 8CH
TL0 Timer/counter0 low byte 8AH
TH1 Timer/counter 1 high byte 8DH
TL1 Timer/counter 1 low byte 8BH
TH2 Timer/counter 2 high byte 0CDH
TL2 Timer/counter 2 low byte 0CCH
RCAP2H T/C2 capture register high 0CBH
byte
RCAP2L T/C2 capture register high 0CAH
byte
SCON* Serial control 98H
SBUF Serial data buffer 99H
PCON8 Power control 87H
* indicate Bit addressable

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8051 TIMERS AND COUNTERS

In this article, we focus on Timers/Counters of the 8051 micro controllers. The

8051 has two counters/timers which can be used either as timer to generate a time
delay or as counter to count events happening outside the microcontroller.

The 8051 has two timers: timer0 and timer1. They can be used either as timers or as
counters. Both timers are 16 bits wide. Since the 8051 has an 8-bit architecture,
each 16-bit is accessed as two separate registers of low byte and high byte. First,
we shall discuss about Timer0 registers.
Timer0 registers is 16 bits register and accessed as low byte and high byte. The
low byte is referred as a TL0 and the high byte is referred as TH0. These registers
can be accessed like any other registers.

Timer1 registers is also a 16 bits register and is split into two bytes, referred to as
TL1 and TH1.

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TMOD (timer mode) Register:
This is an 8-bit register which is used by both timers 0 and 1 to set the various
timer modes. In this TMOD register, lower 4 bits are set aside for timer0 and the
upper 4 bits are set aside for timer1. In each case, the lower 2 bits are used to set
the timer mode and upper 2 bits to specify the operation.

TMOD

In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means of starting
and stopping. Some timers do this by software, some by hardware, and some have
both software and hardware controls. The hardware way of starting and stopping
the timer by an external source is achieved by making GATE=1 in the TMOD
register. And if we change to GATE=0 then we do no need external hardware to
start and stop the timers.
The second bit is C/T bit and is used to decide whether a timer is used as a time
delay generator or an event counter. If this bit is 0 then it is used as a timer and if it
is 1 then it is used as a counter.
In upper or lower 4 bits, the last bits third and fourth are known as M1 and M0
respectively. These are used to select the timer mode.

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In Mode 0, the timer works as a 13-bit counter. The lower register TLx uses only 5
bits while the THx register uses 8 bits. When the count reaches its maximum value,
the timer overflows and sets the overflow flag. This mode is rarely used in modern
applications.

In Mode 1, the timer functions as a 16-bit timer using both THx and TLx registers.
The timer counts from 0000H to FFFFH and then overflows, setting the overflow
flag. Because of its large counting range, this mode is widely used for generating
delays in 8051 programs.

In Mode 2, the timer operates as an 8-bit timer with automatic reload capability.
When TLx overflows after reaching FFH, it automatically reloads the value stored
in THx and continues counting again. This mode is commonly used for generating
baud rate in serial communication.

In Mode 3, Timer-0 is divided into two independent 8-bit timers. TL0 acts as one
timer and TH0 acts as another timer. This allows the microcontroller to use an
additional timer, effectively giving three timers instead of two.

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 TCON REGISTER:

BIT Symbol Functions

7 TF1 Timer1 over flow flag. Set when timer rolls from all 1s to 0.
Cleared
When the processor vectors to execute interrupt service
routine
Located at program address 001Bh.
6 TR1 Timer 1 run control bit. Set to 1 by programmer to enable
timer to
count; Cleared to 0 by program to halt timer.
5 TF0 Timer 0 over flow flag. Same as TF1.
4 TR0 Timer 0 run control bit. Same as TR1.
3 IE1 External interrupt 1 Edge flag. Not related to timer
operations.
2 IT1 External interrupt1 signal type control bit. Set to 1 by
program to
Enable external interrupt 1 to be triggered by a falling edge
signal. Set
To 0 by program to enable a low-level signal on external
interrupt1 to
generate an interrupt.
1 IE0 External interrupt 0 Edge flag. Not related to timer
operations.
0 IT0 External interrupt 0 signal type control bit. Same as IT0.

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SERIAL PORT CONTROL REGISTER (SCON) OF 8051/8031
MICROCONTROLLER

Serial Communication in 8051 is used to send and receive data bit-

by-bit through a single communication line. It is mainly used to
communicate with devices like PC, modem, Bluetooth module, other
microcontrollers, etc.

SM0 SM1 Mode

0 0 Mode 0
0 1 Mode 1
1 0 Mode 2
1 1 Mode 3

SM0 and SM1:

This are used together to select the operating mode of the serial port.
Depending on the combination of these bits, the 8051 can operate in
four different modes such as shift register mode, 8-bit UART mode,
or 9-bit UART mode. Among these, Mode 1 is the most commonly

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used because it allows communication with devices like computers
using an 8-bit data frame.

SM2:
SM2 is used when multiple microcontrollers communicate on the
same serial line. When SM2 is set to 1, the receiver accepts data only
if the received 9th bit is 1, which usually indicates an address byte.
This allows the microcontroller to ignore messages that are not
intended for it.

REN (Receive Enable Bit):

Controls data reception.
REN = 1 → Receiver enabled
REN = 0 → Receiver disabled

REN stands for Receive Enable. This bit allows the microcontroller
to receive serial data through the RXD pin. When REN is set to 1, the
8051 can receive incoming serial data. If REN is cleared to 0, the
microcontroller will not receive any data.

TB8 (Transmit Bit 8)

Represents the 9th transmitted bit.
Used in Mode 2 and Mode 3.

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Used for address/data identification.

TB8 stores the ninth bit of data to be transmitted in serial modes that
support 9-bit communication. This bit is commonly used in
multiprocessor communication systems to indicate whether the
transmitted byte is an address byte or a data byte.

RB8 (Receive Bit 8)

Stores the 9th received bit.
Used in Mode 2 and Mode 3.
Helps identify address or data.
RB8 stores the ninth bit of the received data when the 8051 is
operating in 9-bit communication modes. This bit is useful in
multiprocessor communication because it helps determine whether
the received information is an address or actual data.

TI (Transmit Interrupt Flag)

Indicates transmission completion.
Set to 1 after data transmission.
Must be cleared by the program.
TI stands for Transmit Interrupt flag. This bit becomes 1 when the
transmission of a data byte from the serial port is completed. The
programmer must clear this bit in the program before sending the
next data byte.

RI (Receive Interrupt Flag)

Indicates data reception.
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Set to 1 when a byte is received.
Must be cleared by software.

RI stands for Receive Interrupt flag. It becomes 1 when the 8051

receives a complete byte of data through the serial port. After reading
the received data from the SBUF register, the program must clear the
RI flag to prepare for the next data reception.

- Applications of Serial Communication

Communication with PC
Bluetooth / WiFi modules
GPS modules
Microcontroller-to-microcontroller communication
Data logging systems

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INTERRUPTS:
A single microcontroller can serve several devices. There are two ways to do that: interrupts
or polling. In the Interrupt method, whenever any device needs its service, the device notifies
the microcontroller by sending an interrupt signal. Once the interrupt is accepted the
microcontroller serves the device by executing an interrupt service routine (ISR). In polling
method, the microcontroller continuously monitors the status of a give device, when the
condition is met it performs the service. This polling method is not efficient because it has to
monitor all times the status of devices in round-robin fashion and priority assignment is not
possible.

Interrupt Service Routine

For every interrupt, there must be an Interrupt service routine (ISR), Interrupt handler. For
every interrupt, there is a fixed location in memory that holds the address of its ISR. The
group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector
table.

Steps in executing an Interrupt

Once an interrupt is activated, microcontroller performs the following steps.

1. It finishes the instruction it is executing and save the address of the next instruction
(PC) on the stack.
2. It also saves the current status of all the interrupts internally.
3. It jumps to a fixed location in memory called the interrupt vector table that holds the
address of ISR.
4. The microcontroller gets the address of the ISR from the interrupt vector table and
jumps to it. It starts to execute the ISR until it reaches last instruction of subroutine
RETI (return from the interrupt).
5. Upon executing the RETI instruction, the microcontroller returns to the place
where it was interrupted. First it gets PC address from the stack by popping the top
two bytes of the stack into the PC

Six Interrupts of 8051

The six interrupts in the 8051 are allocated as follows

1. Reset- when the reset pin is activated, the 8051 jumps to address location 0000. This is

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power-up reset.

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 2. Two interrupts are set aside for the timers: one for timer 0 and one for timer 1. Memory
locations 000BH and 001BH in the interrupt vector table belongs to timer 0 and timer 1.
respectively.
3. Two interrupts are set aside for hardware external hardware interrupts, Pin numbers 12 (P3.2)
and 13(P3.3) in port 3 are for the external hardware interrupts INT0 and INT1, respectively.
These external interrupts are also referred to as EX1 and EX2. Memory location 0003H and
0013H in the interrupt vector table are assigned to INT0 and INT1 respectively.
4. Serial communication has a single interrupt that belongs to both receive and transfer. The
interrupt vector table location 0023H belongs to this interrupt.

Interrupt Vector Table for 8051

From the table it has been observed that only three bytes of ROM space is assigned to the reset pin.
They are ROM address locations 0,1 and 2.

Table 4.2 Interrupt vector addresses

Interrupt ROM
Location(Hex)
Reset 0000
External hardware interrupt (INT0) 0003
Timer 0 interrupt (TF0) 000B
External hardware interrupt (INT1) 0013
Timer 1 interrupt (TF1) 001B
Serial COM interrupt ( RI and TI) 0023

IE Register (Interrupt Enable):

 EA – global interrupt enable/disable:

o 0 – disables all interrupt requests.
o 1 – enables all individual interrupt requests.
 ES – enables or disables serial interrupt:
o 0 – UART system cannot generate an interrupt.
o 1 – UART system enables an interrupt.
 ET1 – bit enables or disables Timer 1 interrupt:
o 0 – Timer 1 cannot generate an interrupt.
o 1 – Timer 1 enables an interrupt.
 EX1 – bit enables or disables external 1 interrupt:

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o 0 – change of the pin INT0 logic state cannot generate an interrupt.

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 o 1 – enables an external interrupt on the pin INT0 state change.
 ET0 – bit enables or disables timer 0 interrupt:
o 0 – Timer 0 cannot generate an interrupt.
o 1 – enables timer 0 interrupt.
 EX0 – bit enables or disables external 0 interrupt:
o 0 – change of the INT1 pin logic state cannot generate an interrupt.
o 1 – enables an external interrupt on the pin INT1 state change.

Interrupt Priorities
It is not possible to forseen when an interrupt request will arrive. If several interrupts are
enabled, it may happen that while one of them is in progress, another one is
requested. In order that the microcontroller knows whether to continue operation or
meet a new interrupt request, there is a priority list instructing it what to do.
The priority list offers 3 levels of interrupt priority:
1. Reset! The absolute master. When a reset request arrives, everything is stopped and the
microcontroller restarts.
2. Interrupt priority 1 can be disabled by Reset only.
3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.
The IP Register (Interrupt Priority Register) specifies which one of existing interrupt
sources have higher and which one has lower priority. Interrupt priority is usually
specified at the beginning of the program. According to that, there are several
possibilities:
 If an interrupt of higher priority arrives while an interrupt is in progress, it will be
immediately stopped and the higher priority interrupt will be executed first.
 If two interrupt requests, at different priority levels, arrive at the same time then the higher
priority interrupt is serviced first.
 If the both interrupt requests, at the same priority level, occur one after another, the one which
came later has to wait until routine being in progress ends.
 If two interrupt requests of equal priority arrive at the same time then the interrupt to be
serviced is selected according to the following priority list:
1. External interrupt INT0
2. Timer 0 interrupt
3. External Interrupt INT1
4. Timer 1 interrupt
5. Serial Communication Interrupt

IP Register (Interrupt Priority)

The IP register bits specify the priority level of each interrupt (high or low priority).

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  PS – Serial Port Interrupt priority bit
o Priority 0
o Priority 1
 PT1 – Timer 1 interrupt priority
o Priority 0
o Priority 1
 PX1 – External Interrupt INT1 priority
o Priority 0
o Priority 1
 PT0 – Timer 0 Interrupt Priority
o Priority 0
o Priority 1
 PX0 – External Interrupt INT0 Priority
o Priority 0
o Priority 1

Handling Interrupt:
When an interrupt request arrives, the following occurs:
1. Instruction in progress is ended.
2. The address of the next instruction to execute is pushed on the stack.
3. Depending on which interrupt is requested, one of 5 vectors (addresses) is written to the
program counter in accordance to the table below:
4.
INTERRUPT SOURCE VECTOR (ADDRESS)

IE0 3h

TF0 Bh

TF1 1B h

RI, TI 23 h

All addresses are in hexadecimal format

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 5. These addresses store appropriate subroutines processing interrupts. Instead of
them, there are usually jump instructions specifying locations on which these
subroutines reside.
6. When an interrupt routine is executed, the address of the next instruction to execute is poped
from the stack to the program counter and interrupted program resumes operation from
where it left off.

From the moment an interrupt is enabled, the microcontroller is on alert all the time. When an
interrupt request arrives, the program execution is stopped, electronics recognizes the source and
the program “jumps” to the appropriate address (see the table above). This address usually stores
a jump instruction specifying the start of appropriate subroutine. Upon its execution, the program
resumes operation from where it left off.

Reset
Reset occurs when the RS pin is supplied with a positive pulse in duration of at least 2 machine
cycles (24 clock cycles of crystal oscillator). After that, the microcontroller generates an internal
reset signal which clears all SFRs, except SBUF registers, Stack Pointer and ports (the state of
the first two ports is not defined, while FF value is written to the ports configuring all their pins
as inputs). Depending on surrounding and purpose of device, the RS pin is usually connected to a
power-on reset push button or circuit or to both of them. Figure below illustrates one of the
simplest circuit providing safe power-on reset.
Basically, everything is very simple: after turning the power on, electrical capacitor is being charged
for several milliseconds throgh a resistor connected to the ground. The pin is driven high during this
process. When the capacitor is charged, power supply voltage is already stable and the pin remains
connected to the ground, thus providing normal operation of the microcontroller. Pressing the reset
button causes the capacitor to be temporarily discharged and the microcontroller is reset. When
released, the whole process is repeated…

6. Programmer’s Model

The CPU registers are used to store the data temporarily. The information may be data to
be processed or address pointing the data to be fetched. The majority of registers are 8 bits. The
8-bit registers are shown in the diagram from MSB (most significant bit) D7 to the LSB (least
significant bit) D0. The most widely used registers of 8051 are A (accumulator), B, R0, R1, R2,
R3, R4, R5, R6, R7, DPTR (data pointer), and PC (program counter). All these registers are 8
bits except DPTR and the program counter. The accumulator is used to hold one operand before
execution and hold the result after execution. The program counter points to the address of next
instruction to be fetched. It is an auto increment register. As the size of program counter is 16 bits.
8051 can access the program addresses from 0000H-FFFFH. When 8051 is powered-up the
program counter contents will be 0000H. This means that it expects the first opcode to be stored

24
at ROM address 0000H. For this reason, in the 8051 system, the first opcode must be burned
memory location 0000H of program ROM since this is where it looks for the first instruction
when it is booted.

Fig. 4.22 Programmer’s model Fig. 4.23 PSW register

PSW (program status word register)

The program status word register (PSW) is an 8-bit register. It is also referred as Flag
register. Although this register is size of 8-bits, only 6bits are used by 8051. Two unused bits are
user definable flags. Other 4 bits are called as conditional flags such as CY (carry), AC
(auxiliary carry), P(parity) and OV(overflow).In this register the bits PSW.3 and PSW.4 are
designated as RS0 and RS1 and used to select the banks. PSW.5 and PSW.1 bits are general
purpose status flags and can be used by the programmer for any purpose.

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7. Operand addressing

An addressing mode is a method of specifying the data source or destination in an

instruction. There are 5 types of addressing modes is supported by 8051.

1. Register
2. Immediate
3. Direct (memory related)
4. Register Indirect (memory related)
5. Index register addressing

Register addressing mode

This addressing mode involves the use of registers to hold the data to be manipulated.

Examples:

MOV A, R0 ; Copy the contents of R0 int A

ADD A, R7 ; Add the contents of R7 to contents of A and the result is stored in A

Immediate addressing mode

In this addressing mode immediate data is specified in instruction as a source operand.

Examples:

MOV B, #40H ; load 40H into B

register MOV DPTR, #2000H; load 2000H into DPTR

Direct addressing mode

As we know the on-chip RAM of 8051 is 128 byte, it can be accessed through memory address
from 00H to FF H. The allocations of 128 bytes are as follows.

1. RAM location 00H-1FH are assigned to register banks and stack

2. RAM location 20H-2FH is set aside as bit-addressable space to save single bit data.
3. RAM location 30H-7F is available as place to save bite-sized data.

Although the entire 128 bytes of RAM can be accessed through direct addressing mode, it is
most often used to access RAM location 30H-7FH. This is due to fact that register banks are
accessed through their names.

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Examples:

MOV R4, 70H ; move the contents of RAM location 70H to R4.

MOV 56H, A ; save the content of A in RAM location 56H

PUSH 05 ; push R5 onto the stack

Register indirect addressing mode

In this mode the address (of 8bits) is indirectly specified in the instruction by the contents
of pointer. This addressing mode so called because the source operand is from the address
specified indirectly by another register in the instruction. The limitation is that only R0 and R1
register can be used in 8051 for indirect addressing. SFRs are directly accessible.

Examples

MOV R1, #55H ; load pointer R1=55H

MOV A, @R1 ; the content of pointer is transferred to A

Index registers addressing

Suppose we need to access external data RAM and external code space of on-chip ROM
16 bit address must be required. In this case we have to use DPTR. This mode is widely used in
accessing data elements of look-up table entries in the program ROM space of 8051.

Examples;

MOV DPTR, #0200H ; load DPTR with 0200

CLR A ; clear accumulator

MOVC A,@A+DPTR ; Move the content 0200 location into A

8. Instruction set
The instruction set of 8051 can be classified into following group.

1. Data Transfer Instructions

2. Arithmetic Instructions
3. Logic Instructions
4. Boolean Variable manipulation Instructions
5. Program flow control (Processor and Machine control) Instructions
6. Interrupt flow Control instruction

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 12.1 Data Transfer Instruction

Three types of the data transfer can be done by move instruction. First type is transfer
within the internal RAM and SFRs, second type is transfer using code memory area (CODE) and
the third is using the external data memory X-DATA).

MOV instruction

A MOV instruction means move (copy) the bits from one source to a destination.

Table 4.4 MOV instructions within the registers, internal RAM and SFRs in 8051
Instruction Action Addressing Length in cycles
(Mnemonic) bytes
MOV A, Rn Move Rn into A Register 1
MOV Rn, A Move into Rn from A Register 1
MOV A, #data Move immediate 8-bit data into A Immediate 2
MOV Rn, #data Move into Rn the data. immediate 2
MOV A, direct Move byte at the direct address into A Direct 2
MOV Rn, direct Move from direct address into Rn Direct 2 2
MOV direct, A Move byte to the direct address form A Direct 2 1
MOV direct, Rn Move a byte to the direct address from Rn Direct 2 2
M OV direct, direct Move byte to the direct address from the direct Direct 3 2
address
MOV direct, #data Move immediate data byte to the direct address Immediate 2

MOV a,@Ri Move into A the byte from the address pointed by Indirect 2
Ri
MOV @Ri, A Move A into address pointed by Ri Indirect 1 1
MOV direct, @Ri Move into direct address from address indirect 1
pointed by Ri
MOV @Ri, direct Move from the direct address to the address poined Indirect 2
by ri
MOV @Ri, #data Move data ino address pointed by Ri immediate 2 2
MOV DPTR, data16 Mov e16 bit dat immediate 3 2

MOVC-type Instruction

It moves the 8-bit code from one source at the program memory (internal and external) to the register A
destination.

Table 4.5 MOVC Instructions for transfer from the program memory area address code or
constant to accumulator in 8051
Instruction Action Addressing Length in Cycles
bytes
MOVC A, @A+DPTR Moves the code or constant into A the byte from Indirect
the program memory address pointed

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 by hypothetical addition of DPTR with the A
itself.
MOVC A, @A+PC Move the code or constant into A the byte Indirect 1 2
from the program memory address pointed
by hypothetical addition of PC with the A
itself

MOX-type Instructions

A MOVX instruction means move (copy) the 8-bit data into A and from A using the external
data memory address using DPTR or Ri as the pointer

Table 4.6 MOVX instruction

Instruction Action Addressing Length in Cycles
bytes
MOVX A, @DPTR Move the external data byte Indirect 1 2
(X-DATA) into A from the
data memory address pointed
by DPTR
MOVX @DPTR,A Move into the external data Indirect 1 2
memory from A to the
address pointed by DPTR
MOVX A,@Ri Move the external data byte Indirect 1 2
into a from the memory
address pointed by Ri
MOVX @Ri, A Move into the external data Indirect 1 2
memory from A to the
memory address pointed by
Ri

Table 4.7 PUSH and POP instructions for using the Stack Area employing SP
Instruction Action Addressing Length in Cycles
bytes
PUSH direct Move byte from a direct Direct 2 2
internal RAM or SFR into the
stack after first incrementing
the stack pointer by 1
POP direct Move byte to a direct internal Direct 2 2
RAM or SFR into the stack
and then decrement the stack
pointer by 1.

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XCH-type instructions

An XCH instruction is for exchanging the A register with a source using the register (direct or
indirect addresing0 mode.

Table 4.8 XCH and XCHD instruction

Instruction Action Addressing Length in cycles
bytes
XCH A@Ri Exchange byte at A with the Indirect 1 2
address pointed by Ri
XCH A,Rn Exchange byte at A with the Register 1 2
register Rn
XCH A, direct Exchange byte at A with the byte Direct 1 1
at a direct address.
XCHD A,@Ri Exchange lower hex-digits of the Indirect 1 2
bytes at A with the address pointed
by Ri

12.2 Arithmetic Instruction

These instructions include 8 bit addition, subtraction, increment, decrement, multiply and
division instruction.

Table 4.9 Arithmetic ADD, SUB,MUL, DIV, INC and DEC instruction s in 8051
Instruction Action Addressing Flags Length Cycles
affected (bytes)
ADD A,Rn Add Rn into A Register C,AC,OV 1 1
ADD A, direct Add the byte at the direct address Direct C,AC,OV 2 1
into A
ADD A, @Ri Add the byte from the address Indirect C,AC,OV 1 1
pointed by the Ri into A
ADD A, #data Add immediate data byte to the A Immediate C,AC,OV 2 1
ADDC A, Rn Add CF(carry) bit and Rn into A Register C,AC,OV 1 1
ADDC A, direct Add CF bit and byte at the direct Direct C,AC,OV 2 1
address ito A
ADDC A @Ri Add CF bit and the byte from the Indirect C,AC,OV 1 1
address pointed by the Ri
ADDC A, #data Add CF bit and immediate data Immediate C,AC,OV 2 1
byte to the A
SBBB A,Rn Subtract borrow at CF bit and Rn Rgister C,AC,OV 1 1
into A
SBBB A, direct Subtract borrow at CF bit and byte Direct C,AC,OV 2 1
at the direct address into A

SBBB A, @Ri Subtract borrow at C bit and byte at Indirect C,AC,OV 1 1

the byte from the address pointed

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 by the Ri into A
SBBB A, #data Subtract borrow at CF bit and Immediate C,AC,OV 2 1
immediate data byte into A
INC A Increment Register None 1 1
INC Rn Increment Rn Register None 1 1
INC direct Increment byte at the direct address Direct None 2 1
INC @Ri Increment the byte at the address Indirect None 1 1
pointed by Ri
DEC A Decrement A Register None 1 1
DEC Rn Decrement Rn Register None 1 1
DEC direct Decrement byte at the direct Direct None 2 1
address
DEC @Ri Decrement the byte at the address Indirect None 1 1
pointed by the Ri
MUL AB Multiply A and B Result MSB in B Register OV 1 4
and LSB in A
DIV AB Divide A (Numerator) and Register OV 1 4
B( denominator) Remainder
in B Quotient in A
DAA Decimal adjust accumulator Register C 1 1

12.3 Logical Instruction

Table gives features of 8-bit AND, OR and XOR instruction. These instructions have 4
addressing modes such as register, immediate, direct and indirect.

Table 4.10 ANL, ORL XRL instruction

Instruction Action Addressing Length in Cycles
bytes
ANL A, Rn AND Rn into A Register 1 1
ANL A, direct AND byte at the direct address Direct 2 1
into A
ANL A, @Ri AND into the byte from the Indirect 1 1
address pointed by the Ri
ANL A, #data AND immediate data byte into A immediate 2 1
ANL direct, A AND A into byte at the direct Direct 2 1
address
ANL direct, #data AND immediate byte into byte at Direct 3 2
the direct address
ORL A, Rn OR Rn into A Register 1 1
ORL A, direct OR byte at the direct address into Direct 2 1
A
ORL A, @Ri OR into the byte from the address Indirect 1 1
pointed by Ri
ORL A, #data OR immediate data byte to the A immediate 2 1
ORL direct, A OR A into byte at the direct Direct 2 1
address
ORL direct,#data OR immediate byte into byte at the Direct 3 2

31
 direct address
XRL A, Rn XOR Rn into A Register 1 1
XRL A, direct XOR byte at the direct address Direct 2 1
into A
XRL A, @Ri XOR the byte at the address Indirect 1 1
pointed by Ri into A
XRL A, #data XOR immediate data byte to the A immediate 2 1
XRL direct, A XOR A into byte at the direct Direct 2 1
address
XRL direct, #data XOR immediate byte into byte at Direct 3 2
the direct address

12.4 Boolean Variable manipulation Instructions

These are also called as Boolean processing instruction.

Table 4.11 MOV, CLR, CPL,SETB,ANL, and ORL Boolean Processing Instruction
Instruction Action Addressing Length Cycles
(bytes)
MOV C, bit Move bit into CF Direct bit addressing 2 1
MOV bit, C Move CF into the bit Direct bit addressing 2 2
CLR C Clear CF PSW Register CF bit 1 1
addressing
CLR bit Clear bit Direct bit addressing 2 1
CPL C Complement CF PSW Register CF bit 1 1
addressing
CPL bit Complement bit Direct bit addressing 2 1
SETB C Set CF=1 PSW Register CF bit 1 1
addressing
SETB bit Set bit =1 Direct bit addressing 2 1
ANL C,bit AND between CF and bit, place the Direct bit addressing 2 2
result in CF
ANL C, bit AND between CF and , place the Direct bit addressing 2 2
result in C
ORL C,bit OR between CF and bit, place the Direct bit addressing 2 2
result in C
ORL C, bit OR between CF and bit , place the Direct bit addressing 2 2
result in C

12.5 Control Transfer Instruction

In the main program other sub programs may be called to perform a particular task. When a sub
program is called the processor will jump to a new address where this program is available and

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it has to accomplish program flow control transfer with help of JUMP and CALL instruction
when some condition met.

Table 4.12 Delay-Cycle (NOP) instruction ( No operation)

Instruction Action Addressing Length in Cycles
bytes
NOP No operation, PC gets the address of 1 1
next instruction on incrementing at
NOP.

Long, Absolute and Short Jump

8051 has three jump instructions: Long- it jumps to 16-bit address, Absolute- it jumps within 2 K
bytes and Short- it jumps to address within 128 bytes above or below the present address.

Table 4.13 Long, absolute and short jump instructions

Instruction Action Addressing Length Cycles
in bytes
LJMP addr16 Jump to the next address given by Direct 16 bit 3 2
two bytes in the instruction address
AJMP addr11 Jump to the next address Direct 11-bit 2 2
address
SJMP rel Jump in the range between -128 Direct 8-bit 2 2
and +127 from the address of
next instruction
JMP @A+DPTR Jump in the next address given by Indirect 16-bit
addition of 8-bits of A with 16- relative
bits of DPTR addreess

Table 4.14 Conditional Short Relative Jumps

Instruction Action Addressing Length Cycles
in bytes
JNZ rel Jump to a relative address if a is Relative(offset) 2 2
not zero
JZ rel Jump to a relative address if A is Relative(offset) 2 2
zero
JNC rel Jump to a relative address if CF is Relative(offset) 2 2
not 1
JC rel Jump to a relative address if CF=1 Relative(offset) 2 2
JB bit, rel Jump to a relative address if Relative(offset) 2 2
addressed bit 1 (bit not set)
JNB bit,rel Jump to a relative address if Relative(offset) 2 2
addressed bit 0 (bit not set)
JBC bit, rel Jump to a relative address if Relative(offset) 2 2
addressed bit 1(bit set) and reset

33
 carry ( make CF=0)

Decrement and Conditional jump on Zero

Table 4.15 Instruction for decrement and then jump in program-loops in 8051
Instruction Action Addressing Length Cycles
in bytes
DJNZ Rn, Rel Decrement Rn and jump if Rn is Relative (offset) 2 2
still not zero.
DJNZ direct, Rel Decrement byte at the direct and Relative (offset) 2 2
jump if byte is still not zero

Jump after comparison

Table 4.16 Compare then conditional jump after comparison

Instruction Action Addressing Flag Length Cycles
affected in bytes
CJNE A, #data, rel Compare A and Relative C 3 2
immediate data and (offset)
jump if both are not
equal.
CJNE Rn, #data, rel Compare Rn and Relative C 3 2
immediate data and (offset
jump if both are not
equal.
CJNE A, direct, rel Compare the bytes at Relative C 3 2
A and direct and (offset
jump if both are not
equal
CJNE @Ri, #data, rel Compare byte from Relative C 3 2
the address pointed (offset)
by Ri and immediate
data and jump if
both are not equal

Call to a Routine

`Table 4.17 Long, absolute call and return instruction

Instruction Action Addressing Length Cycles

in bytes
LCALL addr16 Call to the next address given by two Direct 16- 3 2
bytes in the instruction bit address
ACALL addr11 Call the next address given by 11 bits in Direct 11 2 2

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 the instruction. bit address
RET Return to PC the saved PCL and PCH Stack 1 2
from the stack. address

12.6 Interrupt Control Flow (RETI instruction)

Table 4.18 RETI instruction

Instruction Action Addressing Length In bytes cycles
RETI Return into PC the Stack adddress 1 2
saved PCL and

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