CSC 203 –Digital Design
COURSE PARTICULARS
Course Code: CSC 203
Course Title: Digital Design
No. of Units: 3
Course Duration: Two hours of theory and 3 hours of practical per week for 13 weeks.
Status: Compulsory
Course Email Address: csc203@[Link]
Course Webpage: [Link]
Prerequisite: NONE
COURSE INSTRUCTORS
Prof. S.O. Falaki
Dept. of Computer Science,
The Federal University of Technology, Akure, Nigeria.
Phone: +2348034034202
Email: osfalaki@[Link]
Dr. A.O. Adetunmbi
Dept. of Computer Science,
The Federal University of Technology, Akure, Nigeria.
Phone: +08039617525
Email: aoadetunmbi@[Link]
Mr. E.A. Ibidunmoye
Dept. of Computer Science,
The Federal University of Technology, Akure, Nigeria.
Phone: +08066851683
Email: eaibidunmoye@[Link]
and
Mr. B.S. Ige
Dept. of Computer Science,
The Federal University of Technology, Akure, Nigeria.
Phone: 08067113906
Email: bsige@[Link]
1
COURSE DESCRIPTION
This course provides an introduction to the design of computer components. Students will learn
the necessary mathematical background to carry out logic design. Students will design and
implement simple combinational and sequential circuits.
COURSE OBJECTIVES
The specific objectives of this course are to learn:
- Basics of Information and Digital abstractions – number systems and codes,
- CMOS technology and Boolean algebra;
- Combinational, sequential and register transfer logic,
- Hardware Descriptive language, Arithmetic/logic unit, Memories,
- Basics of computer organization, Input-output and Microprocessors.
-
COURSE LEARNING OUTCOMES / COMPETENCIES
Upon completion of CSC 203, students will be able to:
1). perform arithmetic operations in many number systems
2). Characterize the logic function of combinational devices using CMOS, ROM, or PLA
technologies.
3). Explain synthesis issues for combinational devices using CMOS, ROM, or PLA
technologies from their functional specification.
4). Explain synthesis of acyclic circuits from combinational components.
5). Calculate performance characteristics of acyclic circuits with combinational components.
6). Explain and calculate performance characteristics of single-clock sequential circuits.
7). Design, debug, and test combinational circuits of the complexity of an arithmetic logic
unit.
8). Design, debug, and test a controller for a finite-state machine.
9). Pipeline a combinational circuit for improved throughput.
10). Understand issues affecting microprocessor instruction set design.
11). Complete and debug the design of a simple CPU with a given RISC-based instruction set.
12). Measure the memory access performance of a processor, and tune cache design
parameters to improve performance.
13). Design and conduct experiments, as well as to analyze and interpret data,
14). Design a system, component, or process to meet desired needs within realistic
constraints,
15). Identify, formulate, and solve engineering problems,
GRADING SYSTEM FOR THE COURSE
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This course will be graded as follows:
Assignments 10%
Practical 25%
Test(s) 15%
Final Examination 50%
TOTAL 100%
GENERAL INSTRUCTIONS
Attendance: It is expected that every student will be in class for lectures and also participate in
all practical exercises. Attendance records will be kept and used to determine each person’s
qualification to sit for the final examination. In case of illness or other unavoidable cause of
absence, the student must communicate as soon as possible with any of the instructors, indicating
the reason for the absence.
Academic Integrity: Violations of academic integrity, including dishonesty in assignments,
examinations, or other academic performances are prohibited. You are not allowed to make
copies of another person’s work and submit it as your own; that is plagiarism. All cases of
academic dishonesty will be reported to the University Management for appropriate sanctions in
accordance with the guidelines for handling students’ misconduct as spelt out in the Students’
Handbook.
Assignments and Group Work: Students are expected to submit assignments as scheduled.
Failure to submit an assignment, as at when due, will earn you zero for that assignment. Only
under extenuating circumstances, for which a student has notified any of the instructors in
advance, will late submission of assignments be permitted.
Code of Conduct in Lecture Rooms and Laboratories: Students should turn off their cell phones
during lectures. Students are prohibited from engaging in other activities (such as texting,
watching videos, etc.) during lectures. Food and drinks are not permitted in the laboratories.
LUGGAGE, FOOD OR DRINKS Luggage, food or drinks are not allowed in the laboratory. On
entering the lab., there are lockers on the right hand side where all your luggage can be safely
kept. Do not bring your laptops to the Laboratory during lab. hours.
READING LIST
Fundamentals of Logic Design, 6th edition, Charles H. Rota Jr and Larry L. Kenny, Cengage
Learning, 2010
Fundamentals of Digital Logic and Microcomputer Design, 5th edition, M. Rafiquzzaman, John
Wiley and Sons, Inc. (2004).
3
Digital Systems: Principles and Applications, Pearson Education (11th ed.) Ronald J. Tocci,
Neal S. Widmer and Gregory L. Moss, 2011
Design Integrated Circuit: A design Perspective, Pearson Education (2nd Edition). Jan M.
Rabaey. Free softcopy available online.
Practical programming: An Introduction to Computer Science using Python, Pragmatic
Bookshelf, by Jennifer Campbell, Paul Gries, Jason Montogo and Grey Willson (2009).
[Link]
VHDL Tutorial (2009) Peter J. Ashedent. Softcopy available online
Falaki S.O. Lecture Materials on Digital Design
COURSE OUTLINE
Lectures # Topic
1 Course overview and objectives,
Basis of information, number systems and codes
2 Digital Arithmetic Operations
CMOS technology; gate design, timing
3 Logic gates, Boolean Algebra
Hardware description language
4 Canonical forms: synthesis , simplification
Verilog hardware description language,
combinational logic in Verilog – testbenches
5 Sequential Logic Circuits:
Flip flops, registers , clocks
Sequential circuits using HDL
6 Digital Arithmetic circuits
Logical Operations with VHDL
7 Counters and Registers
Simple VHDL implementation of counters
4
8 Finite state Machines , synchronization,
metastability
VHDL implementation
9 Finite state Machines cont.
QUIZ
10 Memory Basics and Timing
11 Analog Building Blocks
12 Models of Computation, Programmable Logic
Device Architecture
Verilog for Digital System Design
13 Simple design Project Discussions
14 Wrapup Lecture
Laboratory Schedule
Lab. # Activity
Lab1 Demonstrating the operation and characteristics of a
TTL logic gate (NAND gate-7400) and
implementing the three basic logic functions using
NAND gate.
Lab2 Demonstrating the operation and characteristics of a
CMOS logic gate (NOR gate-4001) and
implementing the three basic logic functions using
NOR gate and using verilog.
Lab3 TTL and CMOS, NAND, NOR, and XOR gates are
used to implement any logic functions and
implementing the Boolean algebra to reducing logic
circuits to their minimum configuration.
Lab4 Implementing and investigating the operation of a 2-
bit full adder, 4-bit full adder, and 4-bit full
subtractors from basic combinational 74LS logic and
wired using Verilog on Xilinx Sparta 3E FPGA
board
Lab5 Testing the operation of 74x138 decoder, and using it
as demultiplexer. Implement the Boolean functions
using 74x138 decode and 74151 multiplexer.
5
Lab6 Demonstrating the operations and characteristics of
D-type flip-flop and JK-type flip-flop. Verify that the
flip-flop is a bistable multivibrator (has two stable
state).And it has two complementary output states.
Lab 7 Demonstrating the operations and characteristics of a
binary counter (up counter /down counter).
Lab 8 Design Project commenced
Group of students will assign a Problem to solve
which involves the application of materials or
content of this course.