COMPUTER ORGANIZATION &
ARCHITECTURE
COMPREHENSIVE EXAM NOTES
As per IMP Topics | ESE Aligned | All Units Covered
UNIT 1: RISC vs CISC
Definitions
Term Full Form Definition
RISC Reduced Instruction Set Processor with small, highly
Computer optimized instruction set.
Instructions execute in one
clock cycle.
CISC Complex Instruction Set Processor with large
Computer instruction set. One instruction
can perform multiple low-level
operations.
Detailed Comparison Table
Feature RISC CISC
Instruction size Fixed (32 bits) Variable (1 to 15 bytes)
Number of instructions Few (~100 or less) Many (200+)
Addressing modes Few (3-5) Many (12-24)
Memory access Only Load/Store instructions Many instructions can access
memory
Register count Large (32-128 registers) Small (8-16 registers)
Control unit Hardwired Microprogrammed
Execution time One instruction per cycle Multiple cycles per instruction
Pipelining Easy and efficient Difficult due to variable length
Programming Compiler dependent Assembly friendly
Power consumption Lower Higher
RISC Specifications
● Fixed instruction length (32 bits)
● Load/Store architecture — only Load/Store instructions access memory
● Large register file (32-128 registers)
● Simple addressing modes: Register, Immediate, Index, Relative
● Hardwired control unit — faster execution
● Separate instruction and data caches
CISC Specifications
● Variable instruction length (1–15 bytes)
● Memory-to-memory operations possible
● Small register set (8-16 registers)
● Complex addressing modes: Direct, Indirect, Indexed, Base+Offset, Auto-
increment/decrement
● Microprogrammed control unit — easier to modify
● Fewer registers, more stack usage
Applications
RISC Applications CISC Applications
Smartphones (ARM processors) Desktop PCs (Intel/AMD x86)
Tablets and embedded devices Laptops and servers
IoT devices Mainframes
Raspberry Pi Legacy systems
Workstations (SPARC, MIPS) Gaming consoles (x86-based)
Why RISC is Better for Pipelining (Exam Answer)
● Fixed instruction length → predictable fetch stage
● Few addressing modes → no side effects
● Load/Store architecture → memory access is isolated
● Register-to-register operations → fewer data hazards
UNIT 2: CONTROL UNIT DESIGN
Hardwired Control Unit
Definition: Control signals are generated by combinational logic circuits (gates, flip-flops,
decoders). There is no memory involved — everything is wired directly.
Hardwired Control Unit — Block Diagram
┌─────────────┐
│ Instr. Reg │ (IR)
└──────┬──────┘
┌─────────────┐
│ Instruction │
│ Decoder │
└──────┬──────┘
┌─────────────────────────────┐
│ Step Counter (T1, T2, T3) │
└──────────────┬──────────────┘
┌───────────────┐
│ Encoder Logic│
└──────┬────────┘
┌─────────────┐ ┌──────────────┐
│ Control │←────│ Condition │
│ Signals │ │ Codes (Flags)│
└─────────────┘ └──────────────┘
Advantages of Hardwired CU
● Very fast — no memory access delay
● Optimized for simple instruction sets (RISC)
● Lower chip area requirements
Disadvantages of Hardwired CU
● Complex to design and modify — requires rewiring
● Difficult to add new instructions post-design
● Costly for large or complex instruction sets
● Inflexible — not suitable for CISC architectures
Microprogrammed Control Unit
Definition: Control signals are stored as microinstructions in a special memory called the
Control Store (CS). Each machine instruction maps to a sequence of microinstructions.
Microprogrammed Control Unit — Block Diagram
┌─────────────┐
│ Instr. Reg │ (IR)
└──────┬──────┘
┌────────────────────┐
│ Starting Address │
│ Generator (SAG) │
└──────┬─────────────┘
┌──────────────┐ ┌──────────────┐
│ Micro PC │──────│ Next Address │
│ (µPC) │ │ Logic │
└──────┬───────┘ └──────────────┘
┌──────────────┐
│ Control Store│
│ (ROM/RAM) │
└──────┬───────┘
┌──────────────┐
│ Micro Instr │
│ Register │
│ (µIR) │
└──────┬───────┘
┌──────────────┐
│ Decoding │
│ Logic │
└──────┬───────┘
┌──────────────┐
│ Control │
│ Signals │
└──────────────┘
Advantages of Microprogrammed CU
● Easy to design, debug, and modify
● Flexible — new instructions can be added by updating Control Store
● Supports complex instruction sets (CISC)
● Systematic design process — structured approach
Disadvantages of Microprogrammed CU
● Slower — requires additional memory access time for Control Store
● Additional hardware cost for control memory
● Requires extra chip area for ROM/RAM
Horizontal vs Vertical Microprogramming
Feature Horizontal Vertical
Encoding Minimal (1 bit per control Highly encoded (multiple
signal) signals per field)
Word length Long Short
Parallelism High (many ops per cycle) Low
Speed Faster Slower
Control store size Larger Smaller
Decoder complexity Simple Complex
Flexibility Very high Limited
When to use When speed is critical When memory is constrained
Exam Key: Horizontal microinstruction format is suitable when higher operating
speed is required.
UNIT 3: MEMORY — CACHE & VIRTUAL MEMORY
Principle of Locality of Reference
Definition: Programs tend to access memory locations repeatedly or near recently accessed
locations. This principle is the foundation for cache memory design.
Type Definition Example
Temporal Locality Recently accessed location will Loop counters, frequently used
be accessed again soon variables
Spatial Locality Nearby memory locations will Arrays, sequential code
be accessed soon execution
Cache Memory Performance Formula
t_avg = h × t_cache + (1 - h) × t_main
Where:
h = Hit Ratio (fraction of accesses found in cache)
t_cache = Cache access time
t_main = Main memory access time
Cache Mapping Techniques
Given: Block Size = 16B, Cache = 4KB, Main Memory = 512KB
Main memory = 512 KB = 2^19 → 19-bit address
Block size = 16 B = 2^4 → 4-bit offset
Cache blocks = 4KB / 16B = 256 blocks
MM blocks = 512KB / 16B = 32768 blocks
1. Direct Mapping
Address Format:
| Tag (11 bits) | Block Index (8 bits) | Offset (4 bits) |
Rule: Memory block j maps to Cache block (j mod 256)
Advantage: Simple and fast lookup
Disadvantage: Cache conflicts possible (thrashing)
2. Fully Associative Mapping
Address Format:
| Tag (15 bits) | Offset (4 bits) |
Rule: Any memory block can go to ANY cache block
Advantage: No conflicts, maximum flexibility
Disadvantage: Complex and expensive hardware (parallel comparison)
3. Set-Associative Mapping (2-way)
Sets = 256 / 2 = 128 sets
Address Format:
| Tag (12 bits) | Set Index (7 bits) | Offset (4 bits) |
Rule: Block maps to a set, can occupy any line within that set
Advantage: Balance between direct and fully associative
Page Replacement Algorithms (Frame Size = 3)
Reference String: 2, 3, 3, 1, 5, 2, 4, 5, 3, 2, 5, 2
Algorithm Strategy Hits Key Property
FIFO Replace oldest page in 4 Simple, may suffer
memory from Belady's
anomaly
LRU Replace page not used 4 Practical and
for longest time commonly used
Optimal Replace page not 6 Best possible —
needed for longest theoretical benchmark
future time
Virtual Memory & Address Translation
Virtual Address → | VPN (Virtual Page Number) | Offset |
Page Table
Physical Address ← | PFN (Page Frame Number) | Offset |
TLB (Translation Lookaside Buffer):
→ Cache for page table entries
→ Speeds up virtual-to-physical address translation
→ TLB Hit: translation found in TLB (fast)
→ TLB Miss: consult page table in RAM (slow)
Page Fault:
→ When VPN not in physical RAM
→ OS loads page from disk (swap space)
→ Very slow — involves disk I/O
UNIT 4: BUSES — PCI, SCSI, USB
Universal Serial Bus (USB)
Feature USB 1.0/1.1 USB 2.0 USB 3.0/3.1
Speed 12 Mbps (full), 1.5 480 Mbps 5 Gbps / 10 Gbps
Mbps (low)
Signaling Single-ended Differential Differential
Hot pluggable Yes Yes Yes
Cable length 5m (max) 5m 3m
Key Features of USB
● Plug-and-play — devices auto-detected
● Hot pluggable — connect/disconnect without reboot
● Tree topology with hubs (up to 127 devices)
● Polling-based communication controlled by host
● Isochronous support for real-time audio/video
USB Handshaking Signals
Signal Full Form Description
SOF Start of Frame Sent every 1ms to synchronize
devices
ACK Acknowledgment Data received successfully
NAK Negative Acknowledgment Data not received, request
retry
STALL Stall Error condition, device cannot
respond
PCI (Peripheral Component Interconnect)
Feature PCI 2.x PCI-X PCI Express (PCIe)
Width 32/64 bits 64 bits Serial lanes (x1, x4, x8,
x16)
Speed 33/66 MHz 133 MHz 2.5 GT/s to 32 GT/s
Bandwidth 133–533 MB/s 1.06 GB/s ~1 GB/s per lane
(PCIe 3.0)
Topology Shared bus Shared bus Point-to-point switch
Key Features of PCI
● Plug-and-play using configuration space registers
● Bus master capable — any device can take control
● Synchronous bus — all devices share a clock
● Three independent address spaces: Memory, I/O, Configuration
PCI Handshaking Signals
Signal Description
FRAME# Indicates start and duration of transaction
IRDY# Initiator Ready — master is ready to transfer
TRDY# Target Ready — slave is ready to receive/send
DEVSEL# Device Selected — target claims the address
IDSEL# Initialization Device Select — used during
configuration
SCSI (Small Computer System Interface)
Feature SCSI-1 SCSI-2 (Fast) SCSI-3 (Ultra) SAS
Width 8 bits 8/16 bits 16 bits Serial
Speed 5 MB/s 10-20 MB/s 40 MB/s 3-12 Gb/s
Cable length 6m 3m 1.5m 10m
Key Features of SCSI
● Multiple devices on one bus (up to 16 including host)
● Disconnect/reconnect capability for bus efficiency
● Tagged Command Queuing (TCQ) — reorders commands for performance
● Primarily used for disk drives and storage peripherals
SCSI Handshaking Signals
Signal Description
REQ Request — target requests a data transfer
ACK Acknowledge — initiator acknowledges the
request
BSY Busy — bus is currently in use
SEL Select — used to select a target device
Comparison: PCI vs SCSI vs USB
Feature PCI SCSI USB
Primary use Internal expansion Disk drives & storage External peripherals
cards
Topology Shared bus Shared bus Tree with hubs
Hot pluggable No No Yes
Max devices 4-6 slots Up to 16 Up to 127
Data rate Up to 1 GB/s+ (PCIe) Up to 12 Gb/s (SAS) Up to 10 Gb/s (USB
3.1)
Communication Bus master Initiator/Target Polling/Messaging
UNIT 5: FLYNN'S TAXONOMY
Overview
Flynn's Taxonomy classifies computer architectures based on the number of concurrent
instruction streams and data streams. Proposed by Michael J. Flynn in 1966.
Flynn's Classification Diagram
FLYNN'S TAXONOMY
┌─────────────────┼─────────────────┐
↓ ↓ ↓
SISD SIMD MISD
(Single Instr, (Single Instr, (Multiple Instr,
Single Data) Multiple Data) Single Data)
| | |
Traditional Vector/GPU Fault-tolerant
CPU (PC) Cray Systems (Rare)
MIMD
(Multiple Instr,
Multiple Data)
/ \
Shared Distributed
Memory Memory
(SMP) (Clusters)
Detailed Classification Table
Type Instructions Data Description Example
SISD Single Single Traditional Single-core CPU,
sequential classic PC
computer — von
Neumann model
SIMD Single Multiple Same operation Vector
on multiple data processors, GPUs,
elements Cray
simultaneously supercomputers
MISD Multiple Single Different Fault-tolerant
operations on flight control
same data stream
(theoretical/fault
-tolerant)
MIMD Multiple Multiple Fully parallel, Multi-core CPUs,
independent clusters,
processing units supercomputers
MIMD Subcategories
Type Memory Communicatio Scalability Example
n
Shared Memory Global shared Through memory Limited SMP, multi-core
(UMA) desktop PC
Distributed Local per node Message passing Very high Supercomputers,
Memory (MPI) cloud clusters
UNIT 6: PIPELINING
Concept
Pipelining is a technique where multiple instructions are overlapped in execution. Each
instruction is divided into stages (Fetch, Decode, Execute, Write-back) and multiple
instructions are processed simultaneously — each at a different stage.
Space-Time Diagram
Sequential Execution (Non-pipelined, k=4 stages)
Time → 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I1: F D E W
I2: F D E W
I3: F D E W
I4: F D E W
Total = 16 cycles for 4 instructions
Pipelined Execution (k=4 stages)
Time → 1 2 3 4 5 6 7
I1: F D E W
I2: F D E W
I3: F D E W
I4: F D E W
Total = 7 cycles for 4 instructions
(k + n - 1 = 4 + 4 - 1 = 7)
Pipeline Performance Formulas
Parameter Non-pipelined Pipelined
Total time (n instr, k stages) n×k×T k × T + (n-1) × T = (k + n - 1) ×
T
Throughput 1 / (k × T) 1 / T (ideal)
Speedup — k / (1 + (k-1)/n) ≈ k (for large
n)
Efficiency — Speedup / k × 100%
Worked Example (n=4, k=4, T=1ns)
Type Formula Result
Sequential time 4 × 4 × 1ns 16 ns
Pipelined time (4 + 4 - 1) × 1ns 7 ns
Speedup 16 / 7 2.28×
Efficiency 2.28 / 4 × 100% 57%
Pipeline Hazards
1. Structural Hazard
Occurs when two instructions need the same hardware resource at the same time.
● Example: Both fetch and data access need memory simultaneously
● Solution: Use separate instruction cache and data cache (Harvard architecture)
2. Data Hazard (RAW — Read After Write)
I1: ADD R1, R2, R3 ← writes to R1 in cycle 4
I2: SUB R4, R1, R5 ← needs R1 in cycle 3 (hazard!)
Timing Diagram with Stall:
Cycle: 1 2 3 4 5 6 7
I1: F D E W
I2: F D stall E W
I3: F stall D E W
● Solution — Operand Forwarding: Bypass ALU output directly to input of next
instruction without waiting for register write-back.
3. Control Hazard (Branch Hazard)
Branch instructions cause the pipeline to not know which instruction to fetch next until the
branch is resolved.
Cycle: 1 2 3 4 5 6
I1: F D E W
I2(Br): F D E W
I3: F (discard — wrong path)
Ik: F D E W ← actual target
Branch penalty = 2 cycles (in 4-stage pipeline)
Solutions for Control Hazard
● Branch Prediction (Static/Dynamic): Predict taken or not-taken; fetch accordingly
● Branch Folding: Buffer instructions in an instruction queue
● Delayed Branch: Compiler fills the delay slot after branch with useful instruction
UNIT 7: QUANTUM COMPUTING
Definition
Quantum computing uses quantum mechanical phenomena — superposition, entanglement,
and interference — to perform computations that are exponentially faster than classical
computers for specific problem types.
Key Concepts
Concept Explanation
Qubit Quantum bit. Unlike a classical bit (0 or 1), a
qubit can exist in a superposition of both 0 and
1 simultaneously.
Superposition Qubits exist in multiple states at once. A system
of n qubits can represent 2^n states
simultaneously.
Entanglement Two qubits can be correlated such that the state
of one instantly affects the other, regardless of
distance.
Quantum Gate Operations on qubits (e.g., Hadamard creates
superposition, CNOT for entanglement, Pauli-X
for bit flip).
Measurement Observing a qubit collapses its superposition to
a classical 0 or 1 value.
Advantages of Quantum Computing
● Exponential speedup for certain problem categories
● Shor's Algorithm: Factors large numbers in polynomial time — breaks RSA encryption
● Grover's Algorithm: Database search in O(√N) vs classical O(N)
● Efficient for optimization, molecular simulation, and machine learning
Disadvantages of Quantum Computing
● Decoherence: Qubits lose quantum state due to environmental interference
● Error correction is extremely difficult and resource-intensive
● Requires near-absolute zero temperature (−273°C) for operation
● Very expensive and complex hardware infrastructure
● Not suitable for general-purpose computing tasks
Applications
Application Area Description
Cryptography Breaking RSA (Shor) and creating quantum-safe
encryption
Drug Discovery Molecular simulation for pharmaceutical
research
Optimization Logistics, scheduling, financial modeling
Artificial Intelligence Quantum machine learning algorithms
Weather Forecasting Rapid simulation of complex atmospheric
models
UNIT 8: NEUROMORPHIC COMPUTING
Definition
Neuromorphic computing mimics the structure and function of the human brain's neural
networks using electronic circuits. It uses Spiking Neural Networks (SNNs) to replicate
biological neuron behavior.
Key Concepts
Concept Explanation
Spiking Neural Networks (SNN) Neurons communicate via electrical spikes
(pulses), like biological neurons
Event-driven Computation only occurs when a spike event
happens — not on a clock cycle
Memristors Resistive memory devices that mimic synaptic
connections — remember past electrical
history
No global clock Asynchronous operation, unlike von Neumann's
clocked architecture
Collocated memory & processing Memory and computation are co-located, like
biological brains — no memory bottleneck
Advantages of Neuromorphic Computing
● Extremely low power consumption (micro to milliwatt range)
● Massive parallelism — natural by design
● Real-time processing capabilities without latency overhead
● Fault-tolerant — like a biological brain, damage doesn't stop function
● Scales efficiently without proportional power increase
Disadvantages of Neuromorphic Computing
● Still in research and early development stage
● Lack of standard programming models and tools
● Requires specialized and expensive hardware
● Difficult to train and program compared to conventional systems
● Limited commercial availability — mainly IBM TrueNorth, Intel Loihi
Applications
Application Area Description
Pattern Recognition Real-time recognition of complex patterns
Computer Vision Low-power object detection and tracking
Robotics Real-time sensory-motor control
Edge AI / IoT Ultra-low-power AI inference at the edge
Autonomous Systems Self-driving cars, drones, prosthetics
Quantum Computing vs Neuromorphic Computing
Feature Quantum Computing Neuromorphic Computing
Inspiration Physics (quantum mechanics) Biology (human brain)
Basic unit Qubit Spiking neuron
State representation Superposition (0 and 1) Membrane potential (analog)
Computation model Quantum gates & circuits Spike events & synaptic
weights
Power Very low compute, but huge Ultra-low (μW to mW)
cooling overhead
Main challenge Decoherence & error Programming models &
correction training
Commercial status Early (IBM Q, Google Research stage (Intel Loihi,
Sycamore) IBM TrueNorth)
QUICK REVISION SHEET
RISC vs CISC
Feature RISC CISC
Instruction size Fixed (32-bit) Variable (1-15 bytes)
Control unit Hardwired Microprogrammed
Pipelining Easy Difficult
Register count Many (32-128) Few (8-16)
Applications ARM, MIPS, SPARC x86 (Intel/AMD)
Control Unit
Feature Hardwired Microprogrammed
Speed Fast Slow
Flexibility Low High
Used in RISC CISC
Design Complex circuits Simple (modifiable ROM)
Pipeline Formulas
Sequential time = n × k × T
Pipeline time = (k + n - 1) × T
Speedup = Sequential time / Pipeline time
Efficiency = Speedup / k × 100%
t_avg (cache) = h × t_cache + (1-h) × t_main
Flynn's Taxonomy — Quick Reference
Type Instruction Data Example
SISD Single Single Traditional CPU
SIMD Single Multiple GPU / Vector
processor
MISD Multiple Single Fault-tolerant (rare)
MIMD Multiple Multiple Multi-core / Clusters
USB Speed Comparison
Version Speed
USB 1.1 12 Mbps (full speed)
USB 2.0 480 Mbps (Hi-Speed)
USB 3.0 5 Gbps (SuperSpeed)
USB 3.1 10 Gbps (SuperSpeed+)
Quantum vs Neuromorphic — Quick Reference
Quantum Neuromorphic
Unit Qubit Spiking Neuron
Key concept Superposition, Entanglement Spikes, Memristors
Power use High (cooling required) Ultra-low (μW)
Challenge Decoherence Programming
END OF COA NOTES — ALL THE BEST FOR YOUR EXAM!