ELC 112: Principles of Digital Electronics
Question Paper Analysis — Mapped to Syllabus Chapters | Papers: P5126 & PA-999
Chapter 1: Number Systems & Digital Codes 7 hrs
P5126 Q1a: Binary subtraction — (1)2 - (1)2 - (1)2
Q1 short answer
P5126 Q1d: Full form of ASCII
Q1 short answer
P5126 Q2a-i: Rules for binary addition; perform (1100.010)2 + (10.1110) + (1010)2
Q2(a)(i) [3 marks]
P5126 Q3b-i: Convert (1011101)2 to Gray code
Q3(b)(i) [4 marks]
P5126 Q3b-ii: Convert (110101)2 to BCD
Q3(b)(ii) [4 marks]
P5126 Q5a: Short note on Hexadecimal number system
Q5 [2.5 marks]
P5126 Q5d: Gray code — definition and applications
Q5 [2.5 marks]
P5126 Q5f: Concept of parity bits and their uses
Q5 [2.5 marks]
PA-999 Q1c: Convert (23)10 to BCD
Q1 short answer
PA-999 Q1d: Base of Decimal number system
Q1 short answer
PA-999 Q1f: What is Non-weighted code?
Q1 short answer
PA-999 Q2a-ii: (45)10 - (25)10 using 2's complement
Q2(a)(ii) [3 marks]
PA-999 Q3a-iii: Subtract (10110)2 from (63)10, result in binary
Q3(a)(iii) [3 marks]
PA-999 Q4a-iii: Convert (101101)2 to hex, (111)10 to binary, (123)10 to hex
Q4(a)(iii) [3 marks]
PA-999 Q5c: Short note on ASCII
Q5 [2.5 marks]
PA-999 Q5d: Gray code — definition and applications
Q5 [2.5 marks]
PA-999 Q5f: Short note on weighted code
Q5 [2.5 marks]
Chapter 2: Logic Gates 3 hrs
P5126 Q1b: Identify the gate from given symbol — OR / NOR / AND?
Q1 short answer
P5126 Q5b: Short note on universal gates (NAND, NOR)
Q5 [2.5 marks]
P5126 Q5e: EX-OR gate as controlled inverter
Q5 [2.5 marks]
PA-999 Q1b: Draw symbol and truth table for AND logic gate
Q1 short answer
PA-999 Q5b: Design AND, OR & NOT logic using NOR gate only
Q5 [2.5 marks]
PA-999 Q5e: Explain Ex-OR gate as controlled inverter
Q5 [2.5 marks]
Chapter 3: Logic Families 4 hrs
PA-999 Q1a: Define propagation delay
Q1 short answer
PA-999 Q5d: Enlist any five parameters of logic family
Q5 [2.5 marks]
Chapter 4: Boolean Algebra 5 hrs
P5126 Q1e: A-bar + B-bar = ? (Boolean identity)
Q1 short answer
P5126 Q2a-ii: Simplify M = X'Y'Z + X'YZ' + XY'Z' + XYZ' using Boolean algebra
Q2(a)(ii) [3 marks]
P5126 Q3a-i: Convert Y=(A'+B')(B'+C)(A'+C) to standard POS form
Q3(a)(i) [3 marks]
P5126 Q4b: Draw logic diagram for Y = A'B'C'D' + (A+C') + BD and write truth table
Q4(b) [4 marks]
PA-999 Q2a-i: State and prove De Morgan's Theorem
Q2(a)(i) [3 marks]
PA-999 Q2a-iii: Convert A'B' + BC' + A'C to standard SOP form
Q2(a)(iii) [3 marks]
PA-999 Q3a-ii: Simplify Y = A'B'C' + A'BC' + AB'C' + ABC' using Boolean laws
Q3(a)(ii) [3 marks]
Chapter 5: Karnaugh Maps 5 hrs
P5126 Q4a-i: Simplify A = X'Y'Z + X'Y'Z' + XY'Z' + X'YZ' + X'YZ using K-map
Q4(a)(i) [3 marks]
PA-999 Q4a-i: Simplify Y = A'B'C + A'B'C' + AB'C' + A'BC' + A'BC using K-map
Q4(a)(i) [3 marks]
PA-999 Q4b: Design Binary-to-Gray Converter using Karnaugh map technique
Q4(b) [4 marks]
Chapter 6: Combinational Circuits 5 hrs
P5126 Q1c: Multiplexer with 60 inputs — find number of control lines
Q1 short answer
P5126 Q1f: State the function of IC 7447
Q1 short answer
P5126 Q2b: Logic diagram and working of 4-bit universal adder-subtractor
Q2(b) [4 marks]
P5126 Q3a-ii: Logic diagram for 3-bit adder with truth table
Q3(a)(ii) [3 marks]
P5126 Q4a-ii: Logic circuit for BCD to 7-segment; logic levels for digit '3' on common anode display
Q4(a)(ii) [3 marks]
P5126 Q5c: Short note on IC 74138 (3-to-8 decoder)
Q5 [2.5 marks]
PA-999 Q1e: Select lines required for 1:8 Demultiplexer
Q1 short answer
PA-999 Q2b: Draw and explain 4-bit universal Adder/Subtractor
Q2(b) [4 marks]
PA-999 Q3a-i: Draw and explain one-bit digital comparator
Q3(a)(i) [3 marks]
PA-999 Q3b: Draw and explain logic diagram of 1:4 Demultiplexer
Q3(b) [4 marks]
PA-999 Q4a-ii: Explain Full Adder with neat logic diagram and truth table
Q4(a)(ii) [3 marks]
PA-999 Q5a: Truth table of BCD to 7-Segment Decoder and its block diagram
Q5 [2.5 marks]