Lab Manual

CMOS Digital Integrated Circuit Laboratory (3EC05)

Coordinator
Dr. Ronak .R. Vashi

BIRLA VISHVAKARMA MAHAVIDYALAYA

VALLABH VIDHYANAGAR
 Certificate

This is to certify that Aarya Sharma of Third year (5th Semester). ID No. 22EC426 has

completed his term work in the subject CMOS Digital Integrated Circuits Laboratory

(3EC05) satisfactorily in the department of Electronics and Communication at the end of

month November-2024.

Course Coordinator Lab-Coordinator

Dr. Robinson Paul Dr. Ronak Vashi

 INDEX

SR. AIM PAGE DATE SIGN

NO. NO.

1. Introduction to layout design software- Microwind. 5

2. To Study MOSIS (MOS Implementation System) layout Design 8

Rules.
3. To Study and implement n-MOS transistor and its V-I 13
characteristic using Microwind.
4. To Study and implement p-MOS transistor and its V-I 16
characteristic using Microwind.
5. To Study and implement CMOS Inverter using Microwind. 19

6. To Study and implement NAND, AND gate using Microwind. 22

7. To Study and implement NOR, OR gate using Microwind. 26

8. To Study and implement XNOR gate using Microwind. 30

9. To Study and implement XOR gate using Microwind. 33

10. Introduction to DSCH Software and Verilog. 37

11. To Study and implement 2:1 MUX CMOS layout using DSCH and 42
Verilog.
12. To Study and implement Half-Adder CMOS layout using DSCH 47
and Verilog.
13. To Study and implement CMOS Ring Oscillator CMOS layout 50
using DSCH and Verilog.
14. To Study and implement Full Adder CMOS layout using DSCH 55
and
Verilog.
15. To Study and implement Two-bit Comparator CMOS layout using 60
DSCH and Verilog.
16. To Study and implement Edge Triggered D-Flip Flop CMOS 65
layout using DSCH and Verilog.
 PRACTICAL: 1
AIM: Introduction to layout design software- Microwind.
APPARATUS: Microwind 3.1 Software.
THEORY:
MICROWIND software comes from Toulouse, France, offering innovative and shorter
learning curve tool for CMOS layout designs. It's used by thousands of budding
engineers and teachers across the globe.
It is a tool for designing and simulating circuits at layout level. The tool features full
editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics,
2D cross section, 3D process viewer), and an analog simulator.
Microwind3.1 unifies schematic entry, pattern-based simulator, SPICE extraction of
schematic, Verilog extractor, layout compilation, on layout mix-signal circuit simulation,
cross sectional & 3D viewer, netlist extraction, BSIM4 tutorial on MOS devices and
sign-off correlation to deliver unmatched design performance and designer productivity.
It is truly integrated EDA software encompassing IC designs from concept to completion,
enabling chip designers to design beyond their imagination. It integrates traditionally
separated front-end and back-end chip design into one flow, accelerating the design cycle
and reduces design complexities.
It tightly integrates mixed-signal implementation with digital implementation, circuit
simulation, transistor-level extraction and verification – providing an innovative
education initiative to help individuals to develop the skills needed for design positions
in virtually every domain of IC industry.

5
MOS layout:

We use MICROWIND3.1 to draw the MOS layout and simulate its behavior. Go to the
directory in which the software has been copied (By default MICROWIND3.1). Double-
click on the MicroWind3.1 icon. The display window includes four main windows: the
main menu, the layout display window, the icon menu, and the layer palette. The layout
window features a grid, scaled in lambda (l) units. The lambda unit is fixed to half of the
minimum available lithography of the technology. The default technology is a CMOS 6-
metal layers 0.25µm technology, consequently lambda is 0.125 µm.
The palette is in the lower right corner of the screen. A red colour indicates the current
layer. Initially the selected layer in the palette is polysilicon. By using the following
procedure, you can create a manual design of the n-channel MOS.

This paragraph concerns the dynamic simulation of the MOS to exhibit its switching
properties. The most convenient way to operate the MOS is to apply a clock to the gate,
another to the source and to observe the drain. The summary of available properties that
can be added to the layout is reported below:

6
Static MOS Characteristics:

Click on the MOS characteristics icon. The screen shown in Figure appears. It represents
the Id/Vd static characteristics of the nMOS device.

CONCLUSION:
We have studied the introduction to Microwind.

7
 PRACTICAL: 2

AIM: To Study MOSIS (MOS Implementation System) layout Design Rules.

APPARATUS: Microwind 3.1 Software.
THEORY:
Layout design rules:
For complex processes, it becomes difficult to understand the intricacies of fabrication
process and interpret different phot masks.
They act as interface between circuit designer and process engineer.
The table below illustrates the correspondence between technology and value of lambda.

Layout design rules: Well rules

• N-well is deeper mounted than any other transistor implants. Clearance between
nwell edges and n+ diffusion should be good enough.

• This clearance is usually determined by the oxide transition time across the well
boundary.
• The other rule is grounding n-well, providing sufficient number of well taps.
This will prevent significant voltage drops due to well current.
8
Layout design rules: Transistor rules
Transistor is designed with at least for masks:

• active mask – defines where p- or n-diffusion type or gates will be placed;

• n-implant mask – defines areas where n-type diffusion is required; n-type
diffusion in p-wells define nMOS transistors; p-type diffusion in n-wells defines
pMOS transistors;

• p-implant mask – defines where p-type diffusion is required; p-type diffusion in

nwells define n-type contacts.; p-type diffusion in p-wells define p-well contacts
• polysilicon mask – crossing of polysilicon and diffusion mask defines the gates
of transistor.
• Polysilicon mask should cover active mask and extend beyond that area,
otherwise transistor will be shorted with the diffusion path between source and
drain. Crossing of polysilicon and active mask create gate of transistors.
Polysilicon and active masks that does not form a transistor should be kept
separately.

Layout design rules: Contacts rules

Types of contacts:
✦ metal to p-active (p-diffusion)
✦ metal to n-active (n-diffusion)
✦ metal to polysilicon
✦ metal to well or substrate
r401 Contact width 2λ r402 Between two contacts
5λ r403 Extra diffusion over contact 2λ r404 Extra
poly over contact 2λ r405 Extra metal over contact
2λr406 Distance between contact and poly gate 3λ
r407 Extra poly2 over contact 2λ

9
Metal rules
Metal spacing can be different depending on the metal line. But there is certain width
applied to small and thick wires. So, if there is a need of wider wires, they can be made
of several small wires connected together. Spacing rules can be applied to a long parallel
wires. Metal 1 r501 Metal width 2λ r502 Between two metals 2λ r510 Minimum surface
16λ2

Metal 2 rp01 Pad width: 10µm rp02 Between two pads 100µm rp03 opening in
passivation vs via 5µm rp04 opening in passivation vs metals: 5µm rp05 Between pad
and unrelated active area: 20µm

Via (vertical interconnect access) rules Modern planar technology allows stacked vias.

r601 Via width 2λ r602 Between two Via 5λ r603 Between Via and contact 0λ r604 Extra
metal over via 2λ r605 Extra metal2 over via: 2λ Diffusion r201 Minimum N+ and P+
diffusion width 4 λ r202 Between two P+ and N+ diffusions 4 λ r203 Extra n-well after
10
P+ diffusion: 6 λ r204: Between N+ diffusion and n- well 6 λ r205 Border of well after
N+ polarization 2 λ r206 Between N+ and P+ polarization 0 λ r207 Border of n-well for
P+ polarization 6 λ r210 Minimum diffusion area 24 λ 2

Polysilicon r301 Polysilicon Width 2 λ r302 Polysilicon gate on diffusion 2 λ r303

Polysilicon gate on diffusion for high voltage MOS 4 λ r304 Between two polysilicon
boxes 3 λ r305 Polysilicon Vs. other diffusion 2 λ r306 Diffusion after polysilicon 4 λ
r307 Extra gate after polysilicon 3 λ r310 Minimum surface 8 λ 2

11
2nd Polysilicon Design Rules r311 Polysilicon2 with 2 λ r312 Polysilicon gate on diffusion
2 λ r320 Polysilicon2 minimum surface 8 λ2

Other structures
Usually, ready chip is marked with scribe lines, where it should be cut. Manufacturer define
the construction of the scribe line.

Alignment mark is placed on the mask to align one mask to another.

Critical dimension test structures are measured after processing to check proper etching of
narrow polysilicon or metal lines.

Vernier structures are used to check alignment between layers.

MOSIS scalable design rules:

MOSIS CMOS design rules are -scalable. MOSIS CMOS design rules also include
SCMOS, SUBM and DEEP rules variations. For example, for SUBM rule λ=0.3 µm.

CONCLUSION:
Thus, we have studied MOS Implementation system layout design rules.

12
 PRACTICAL: 3

AIM: To study and implement n-MOS transistor and its V-I characteristics using
Microwind.
APPARATUS: Microwind 3.1 Software.
THEORY:
N-type metal-oxide-semiconductor logic uses n-type (-) MOSFETs (metal-oxide-
semiconductor field-effect transistors) to implement logic gates and other digital circuits.
These nMOS transistors operate by creating an inversion layer in a p-type transistor body.
This inversion layer, called the n-channel, can conduct electrons between n-type "source"
and "drain" terminals. The n-channel is created by applying voltage to the third terminal,
called the gate.

NMOS:

• Cut off region Vgs< Vt

• Linear region Vgs>=Vt Vds<Vgs -Vt
• Saturation region Vgs>=Vt Vds>= Vgs – Vt

Layout design of nMOS:

13
Waveform of nMOS (Level1):

Waveform of nMOS (Level 3):

14
Waveform of nMOS (BSIM4):

CONCLUSION:

We implemented n-MOS transistor and its V-I characteristics using Microwind.

15
 PRACTICAL: 4

AIM: To study and implement p-MOS transistor and its V-I characteristics using
Microwind.
APPARATUS: Microwind 3.1 Software.
THEORY:
P-type metal-oxide-semiconductor logic, PMOS or pMOS, is a type of digital circuit
constructed using metal-oxide-semiconductor field effect transistors (MOSFET) with a
ptype semiconductor source and drain printed on a bulk n-type "well". When activated,
by lowering the voltage on the gate, the resulting circuit allows the conduction of electron
holes between the source and drain, turning the circuit "on".PMOS transistors operate by
creating an inversion layer in an n-type transistor body. This inversion layer, called the
p-channel, can conduct holes between p-type "source" and "drain" terminals.

PMOS:

• Cut off region Vgs< Vt

• Linear region Vgs>=Vt Vds<Vgs -Vt
• Saturation region Vgs>=Vt Vds>= Vgs – Vt

Layout design of pMOS:

16
Waveform of pMOS(Level1):

Waveform of pMOS(Level3):

17
Waveform of pMOS ( BSIM4 ) :

CONCLUSION:
We implemented p-MOS transistor and its V-I characteristics using Microwind.

18
 PRACTICAL: 5

AIM: To Study and implement CMOS Inverter using Microwind.

APPARATUS: Microwind 3.1 Software.
THEORY:
The inverter is universally accepted as the most basic logic gate doing a Boolean
operation on a single input variable. Fig.1 depicts the symbol, truth table and a general
structure of a CMOS inverter. As shown, the simple structure consists of a combination
of a pMOS transistor at the top and a nMOS transistor at thebottom.

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–

semiconductor. The words "complementary-symmetry" refer to the fact that the typical
digital design style with CMOS uses complementary and symmetrical pairs of p-type
and ntype metal oxide semiconductor field effect transistors (MOSFETs) for logic
functions. Two important characteristics of CMOS devices are high noise immunity and
low static power consumption. Significant power is only drawn while the transistors in
the CMOS device are switching between on and off states. Consequently, CMOS devices
do not produce as much waste heat as other forms of logic, for example transistor-
transistor logic (TTL) or NMOS logic, which uses all n- channel devices without p-
channel devices.
The CMOS inverter has two important advantages over the other inverter configurations.
The first and perhaps the most important advantage is that the steady-state power
dissipation of the CMOS inverter circuit is virtually negligible, except for small power
dissipation due to leakage currents. In all other inverter structures examined so far, a
nonzero steady-state current is drawn from the power source when the driver transistor
is turned on, which results in a significant DC power consumption. The other advantages
of the CMOS configuration are that the voltage transfer characteristic (VTC) exhibits a
full output voltage swing between 0 V and VDD, and that the VTC transition is usually
very sharp.

19
WORKING OF CMOS INVERTER:
1. Cut-off region
2. Linear region
3. Saturation region

The transistor is said to be in cut-off region when Vgs< Vt. Vgs is the voltage applied at
gate with respect to source and Vt is the threshold voltage below which the transistor
does not work. So for transistor to work Vgs - Vt should be greater than zero always.

The transistor is in linear region when Vgs - Vt >Vds where Vds is the voltage at drain
with respect to source.

The transistor is said to be in saturation region when Vgs - Vt <Vds.

TRUTH TABLE:

Vin(A) T1(nMOS) T2(pMOS) Vout(Q)

0 Off On 1
1 Off Off 0

PROCEDURE:
1. To implement CMOS inverter in Microwind3.1 we follow the steps shown below.
2. First, we create a pMOS at the top and nMOS at the bottom.
3. Then we connect them as shown in the diagram.
4. Then we give Vdd to pMOS and ground ton MOS.
5. Then we give input to gate and take output on the other side.

20
LAYOUT DESIGN OF CMOS

WAVEFORM:

CONCLUSION:
We create the CMOS inverter by following the steps as given

21
 PRACTICAL: 6
AIM: To Study and implement NAND, AND gate using Microwind.
APPARATUS: Microwind 3.1 Software.
THEORY:
• NAND

The NAND gate is a special type of logic gate in the digital logic circuit. The NAND
gate is the universal gate. It means all the basic gates such as AND, OR, and NOT gate
can be constructed using a NAND gate. The NAND gate is the combination of the NOT-
AND gate. The output state of the NAND gate will be low only when all the inputs are
high. Simply, this gate returns the complement result of the AND gate.

The logic or Boolean expression for the NAND gate is the complement of logical
multiplication of inputs denoted by a full stop or a single dot as

(A.B)'=Y

The NAND (Not – AND) gate has an output that is normally at logic level “1” and only
goes “LOW” to logic level “0” when all of its inputs are at logic level “1”. The Logic
NAND Gate is the reverse or “Complementary” form of the ANDgate.

The logic or Boolean expression given for a logic NAND gate is that for Logical
Addition, which is the opposite to the AND gate, and which it performs on the complements
of the inputs. The Boolean expression for a logic NAND gate is denoted by a single dot or

22
full stop symbol, ( . ) with a line or Overline, ( ‾‾ ) over the expression to signify the NOT or
logical negation of the NAND gate giving us the Boolean expression of: A.B =Q.
Then we can define the operation of a 2-input digital logic NAND gate as
being: “If either A or B are NOT true, then Q is true”

TRUTH TABLE OF NAND:

A B (A.B)’
0 0 1
0 1 1
1 0 1
1 1 0

• AND

An AND gate is a logic gate having two or more inputs and a single output. An AND
gate operates on logical multiplication rules. In this gate, if either of the inputs is low (0),
then the output is also low. If all of the inputs are high (1), then the output will also be
high. An AND gate can have any number of inputs, although 2 input and 3 input AND
gates are the most common.

23
The output state of a digital logic AND gate only returns “LOW” again when ANY of its
inputs are at a logic level “0”. In other words, for a logic AND gate, any LOW input will
give a LOW output.
The logic or Boolean expression given for a digital logic AND gate is that for Logical
Multiplication which is denoted by a single dot or full stop symbol, ( . ) giving us the
Boolean expression of: A.B = Q.
Then we can define the operation of a digital 2-input logic AND gate as being: “If
both A and B are true, then Q is true”

TRUTH TABLE OF AND:

A B A.B
0 0 0
0 1 0
1 0 0
1 1 1

PROCEDURE:

1. To implement CMOS NAND & AND in Microwind3.1 we follow the steps shown
below.
2. First of all we create a pMOS at the top and nMOS at the bottom.
3. Then we connect them as shown in the diagram.
4. Then we give Vdd to pMOS and ground ton MOS.
5. Then we give input clock A and B.
6. Then we give input to gate and take output on the other side.

24
LAYOUT DESIGN OF NAND & AND GATE:

WAVEFORMS OF AND & NAND GATE:

CONCLUSION:
We create the NAND & AND gate by following the steps as given.

25
 PRACTICAL: 7

AIM: To Study and implement NOR, OR gate using Microwind.

APPARATUS: Microwind 3.1 Software.

THEORY:

• NOR GATE
In CMOS design, the NOR gate consists of two nMOS in parallel connected to two pMOS
in series. The schematic diagram of the CMOS NOR cell is reported below. The nMOS
in parallel tie the output to the ground if either A or B are at 1. When both A and B are at
0, the nMOS path is cut, but the two pMOS devices in series tie the output to the supply
Vdd.

The logic or Boolean expression given for a logic NOR gate is that for Logical
Multiplication which it performs on the complements of the inputs. The Boolean
expression for a logic NOR gate is denoted by a plus sign, (+) with a line or Overline, (‾‾)
over the expression to signify the NOT or logical negation of the NOR gate giving us the
Boolean expression of: A+B = Q then we can define the operation of a 2-input digital
logic NOR gate as being:

“If both A and B are NOT true, then Q is true”

26
TRUTH TABLE OF NOR:

• OR GATE:

As for the AND gate, the OR gate is the sum of a NOR gate and an inverter. The
implementation of the OR2 gate in CMOS layout requires 6 transistors. An arrangement
may be found to obtain continuous diffusions on n-MOS regions and pMOS regions

An OR gate is a logic gate that performs logical OR operation. A logical OR operation

has a high output (1) if one or both the inputs to the gate are high (1). If neither input is
high, a low output (0) results. Just like an AND gate, an OR gate may have any number
of input probes but only one output probe.

The function of a logical OR gate effectively finds the maximum between two binary
digits, just as the complementary AND function finds the minimum.

27
PROCEDURE:
1. To implement CMOS inverter in Microwind 3.1 we follow the stepsbelow.
2. First of all we create a pMOS at the top and nMOS at the bottom.
3. Then we connect them as shown in thediagram.
4. Then we give Vdd to pMOS and ground tonMOS.
5. Then we give input to gate and take output on the otherside.

TRUTH TABLE OF OR:

A B (A+B)
0 0 0
0 1 1
1 0 1
1 1 1

LAYOUT DESIGN OF OR GATE:

28
LAYOUT DESIGN OF NOR GATE:

WAVEFORMS OF NOR & OR GATE:

CONCLUSION:
We create the CMOS NOR and OR GATE by following the steps as given.
29
 PRACTICAL: 8

AIM: To study and implement XNOR gate using Microwind.

APPARATUS: Microwind 3.1 Software.

THEORY:
XNOR gate also known as Exclusive-NOR or Exclusive-Negative OR gate is “A logic
gate which produces High state “1” only when there is an even number of High state “1”
inputs”. For 2-input gate, it can be interpreted as when both of the inputs are same, then
the output is High state and when the inputs are different, then the output is Low state
“0”.
XNOR gate can have two or more than two inputs but it has only one output. This gate is
also used for equality.

TRUTH TABLE OF XNOR:

A B A’B’+AB

0 0 1

0 1 0

1 0 0

1 1 1

30
PROCEDURE:
To implement XNOR in Microwind3.1 we follow the steps shown below.
1. First place a p+ diffusion from the palette.
2. Then place n+ diffusion right below the p+ diffusion.
3. Then put n-well across P+ diffusion (To differentiate between PMOS and nMOS).
4. We will put four polysilicon layers as shown in fig. Below (Because four inputs are to
be taken).
5. Connect the P contact, N contact and polysilicon contact wherever necessary (Shown
in figure below).
6. Connect Vdd+ and Vss-(ground) wherever necessary (Shown in figure below).
7. Connect clock sources at all the 4 polysilicon contact sources (Shown in figure below).
8. The four input should be such that there will be two different inputs X and Y and the
other two will be the complementary of these two inputs ~X and ~Y.

LAYOUT DESIGN OF XNOR:

31
WAVEFORM:

CONCLUSION:
We follow the steps given and create XNOR gate in Microwind 3.1.

32
 PRACTICAL: 9

AIM: To study and implement XOR gate using Microwind.

APPARATUS: DSCH Software and Microwind 3.1 Software
THEORY:
An Exclusive-OR gate ONLY goes “HIGH” when its two input terminals are at
“DIFFERENT” logic levels with respect to each other.
The Exclusive-OR Gate function, or Ex-OR for short, is achieved by combining standard
logic gates together to form more complex gate functions that are used extensively in
building arithmetic logic circuits, computational logic comparators and error detection
circuits.
The two-input “Exclusive-OR” gate is basically a modulo two adders, since it gives the
sum of two binary numbers and as a result are more complex in design than other basic
types of logic gate. The truth table, logic symbol and implementation of a 2-input
Exclusive-OR gate is shown below.

Symbol Truth Table

A B Q

0 0 0

1 0 1

0 1 1
2-input Ex-OR Gate 1 1 0

Boolean Expression Q = A ⊕ B

Figure: 2-input XOR Gate

The truth table above shows that the output of an Exclusive-OR gate ONLY goes
“HIGH” when both of its two input terminals are at “DIFFERENT” logic levels with
respect to each other.

33
 It gives us the following Boolean expression of:
Q = (A ⊕ B) = 𝐴𝐴 + 𝐴𝐵 + 𝐵𝐴 + 𝐵𝐵 (𝐵𝐵 = 𝐴𝐴= 0)
Q = (A ⊕ B) = 𝐴𝐵 + 𝐵𝐴

One of the main disadvantages of implementing the Ex-OR function above is that it
contains three different types logic gates OR, NAND and finally AND within its design.
One easier way of producing the Ex- OR function from a single gate is to use our old
favorite the NAND gate as shown below. Ex-OR Function Realization using NAND
gates

Exclusive-OR Gates are used mainly to build circuits that perform arithmetic operations
and calculations especially Adders and Half-Adders as they can provide a “carry-bit”
function or as a controlled inverter, where one input passes the binary data and the other
input is supplied with a control signal.

34
The Exclusive-OR logic function is a very useful circuit that can be used in many different
types of computational circuits. Although not a basic logic gate in its own right, its usefulness
and versatility has turned it into a standard logical function complete with its own Boolean
expression, operator and symbol. The Exclusive-OR Gate is widely available as a standard
quad two-input 74LS86 TTL gate or the 4030B CMOS package.
The Boolean expression for an Exclusive-OR function is a plus sign, (+) within a circle (Ο).
This exclusive- OR symbol also represents the mathematical “direct sum of sub objects”
expression, with the resulting symbol for an Exclusive-OR function being given as: (⊕)
Logic Circuit of XOR Gate in DSCH:

A=0, B=0 =>Q=0 A=1,B=0 =>Q=1

A=1, B=1 =>Q=0 A=0,B=1=>Q=1

35
 Layout design of XOR Gate in Microwind:

WAVEFORM:

CONCLUSION:
Hence, we have studied and implemented XOR gate in DSCH and Microwind

36
 PRACTICAL: 10
AIM: Introduction to DSCH Software and Verilog.
APPARATUS: DSCH Software THEORY:
DSCH stands for Design Schematic Editor Tool. The DSCH program is logic editor
and simulator. The DSCH3 program is a logic editor and simulator. DSCH3 is used to
validate the architecture of the logic circuit before the microelectronics design is
started. DSCH3 provides a user-friendly environment for logic [Link] using
DSCH we can design in three types - Gate Level Design, Chip Level Design,CMOS
Level Design. DSCH also features the symbols, models and assembly support for 8051
& 16F84 [Link] can create logic circuits for interfacing with these
controllers and verify software programs using DSCH.A key innovative feature is the
possibility to estimate the power consumption of the circuit.
Installation :
● Click "Download DSCH3 (ZIP file)". In your PC, create manually a
directory (Suggested: c:\program files\dsch3). Store the [Link] file
in this directory.
● Extract all files with WinZip in c:\program files\dsch2.

● Test: double click in [Link]. Load "[Link]". Click "Simulate".

Figure: Home Screen of DSCH3

37
Verilog HDL is one of the two most common Hardware Description Languages (HDL)
used
by integrated circuit (IC) designers. The other one is VHDL. HDL’s allows the design
to be simulated earlier in the design cycle in order to correct errors or experiment with
different architectures. Designs described in HDL are technology-independent, easy to
design and debug, and are usually more readable than schematics, particularly for large
circuits.
Verilog can be used to describe designs at four levels of abstraction:
(i) Algorithmic level (much like c code with if, case and loop statements).
(ii) Register transfer level (RTL uses registers connected by Boolean equations).
(iii)Gate level (interconnected AND, NOR etc.).
(iv) Switch level (the switches are MOS transistors inside gates).

The language also defines constructs that can be used to control the input and output of
simulation. More recently Verilog is used as an input for synthesis programs which will
generate a gate-level description (a netlist) for the circuit. Some Verilog constructs are
not synthesizable. Also, the way the code is written will greatly affect the size and
speed of the synthesized circuit.
Most readers will want to synthesize their circuits, so non synthesizable constructs
should be used only for test benches. These are program modules used to generate I/O
needed to simulate the rest of the design. The words “not synthesizable” will be used
for examples and constructs as needed that do not synthesize.
Verilog has four levels of modelling:
• The gate level.
• The Data-Flow level.
• The Behavioral or procedural level.

38
. Figure: Menu bar Description

39
Palette:
Highlights
● User-friendly environment for rapid design of logic circuits.
● Supports hierarchical logic design.
● The technique allows injection of single stuck-at fault at the nodes of the circuit.
● Improved interface between DSCH and Winspice.
● Handles both conventional pattern-based logic simulation and intuitive on-screen
mouse driven simulation.
● Generates a VERILOG description of the schematic for layout conversion.
● Immediate access to symbol properties (Delay, fanout).
● Model and assembly support for 8051 and PIC 16F84 microcontrollers.
● Sub-micron, deep-submicron, nanoscale technology support.
● Supported by huge symbol library.
● Built-in extractor which generates a SPICE netlist from the schematic
diagram (Compatible with PSPICETM and WinSpiceTM).

CONCLUSION:
Hence, we have introduced DSCH Software and learnt its functions and we have also
studied about Verilog.

40
 PRACTICAL: 11

AIM: To study and implement 2:1 MUX CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software THEORY:
A multiplexer (or mux) is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2^n inputs
has n select lines, which are used to select which input line to send to the output.
Multiplexers are mainly used to increase the amount of data that can be sent over the
network within a certain amount of time and bandwidth. A multiplexer is also called a
data selector. Multiplexers can also be used to implement Boolean functions of multiple
variables.
The input A of this 2:1 mux circuit constructed from standard NAND gates acts to
control which input ( I₀ and I₁ ) gets passed to the output at Q. From the truth table above,
we can see that when the data select input, A is LOW at logic 0, input I₁ passes its data
through the NAND gate mux circuit to the output, while input I₀ is blocked. When the
data select A is HIGH at logic 1, the reverse happens and now input I₀ passes data to
the output Q while input I₁ is blocked.
So, by the application of either a logic “0” or a logic “1” at A we can select the appropriate
input I₀ or I₁ with the circuit acting a bit like a single pole double throw switch.
As we only have one control line then we can only switch 2 inputs and in this simple
example, the 2-input multiplexer connects one of two 1-bit sources to a common output,
producing a 2-to-1 line multiplexer. We can confirm this in the following Boolean
expression.
Q = (A.I₀ )’I₁ +A’I₀ I₁ +AI₀ I₁ ’+A I₀ I₁
Inputs Output

A I₁ I₀ Q
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Procedure:
41
 ● Open DSCH software and implement the circuit using gates present on the
pallet.
● Stimulate the circuit and verify the truth table of 2:1 MUX.

● Save the file with .SCH extension.

● Go to Files>Make Verilog file, to make Verilog file of the 2:1 MUX circuit
in DSCH software.
● Another file with same name but with .v extension will be saved.

● Open Microwind 3.1 software click on Compile>Compile Verilog File.

● Select the file with .v extension.

● A Verilog code will be generated, compile the code.

● If no error is shown then click on Back to editor.

● CMOS layout of 2:1 MUX will be generated.

● Click on RUN and the output waveforms will be generated.

Logic Circuit of 2:1 MUX in DSCH:

Figure: MUX using NAND and NOT gate

42
 Verilog code:
module ckt( I1,I0,A,out);
input I1,I0,A;
output out;
wire w3,w5,w7,;
nand #(13) nand2_1(w5,w3,I0);
nand #(13) nand2_2(w7,I1,A);
nand #(13) nand2_3(out,w7,w5);
not #(10) inv_4(w3,A);
endmodule

// Simulation parameters in Verilog Format

always
#1000 I1=~I1;
#2000 I0=~I0;
#4000 A=~A;

// Simulation parameters
// I1 CLK 10 10
// I0 CLK 20 20
// A CLK 40 40

43
Layout design of 2:1 MUX in Microwind

44
 Waveform of 2:1 MUX:

CONCLUSION:
Hence, we construct the 2:1 Mux in DSCH Software and also verify its truth table, and
by the help of the Verilog code that is made in DSCH is directly used in the Microwind
3.1 and verifies the output waveform with the truth table.

45
 PRACTICAL: 12

AIM: To study and implement Half-Adder CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software THEORY:
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and
carry (C). The carry signal represents an overflow into the next digit of a multi-digit
addition. The value of the sum in decimal system is 2C + S. The simplest half-adder
design, pictured on the right, incorporates an XOR gate for S and an AND gate for C.
With the addition of an OR gate to combine their carry outputs, two half adders can be
combined to make a full adder. The half adder adds two input bits and generates a carry
and sum, which are the two outputs of a half adder. The input variables of a half adder
are called the augend and addend bits. The output variables are the sum and carry.
It gives us the following Boolean expression of:
SUM = (A⊕ B) = A.B’ + A’. B

CARRY = A.B
Truth Table to Half Adder

46
Logic Circuit of Half Adder in DSCH:

Logic Circuit of Half Adder in DSCH:

A=0, B=0 =>SUM=0, A=1,B=0 =>SUM=1,CARRY=0

CARRY=0

A=1, B=1 =>SUM=0, A=0,B=1=>SUM=1,CARRY=0

CARRY=1

47
Layout design of Half Adder in Microwind:

Wave Form of Half Adder in Microwind:

CONCLUSION:
Hence, we have generated a circuit which follows the truth table of Half Adder.

48
 PRACTICAL: 13
AIM: To study and implement CMOS Ring Oscillator CMOS layout using DSCH and
Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software THEORY:
Consider the cascade connection of three identical CMOS inverters where the output node
of the third inverter is connected to the input node of the first inverter. As such, the three
inverters form a voltage feedback loop. It can be found by simple inspection that this
circuit does not have a stable operating point. In fact, a closed loop cascade connection of
any odd number of inverters will display astable behavior such a circuit will oscillate once
any of the inverter input or output voltages deviate from the unstable operating point, Vth.
Therefore, the circuit is called a ring oscillator.
It can be seen from Fig. that each inverter triggers the next inverter in the cascade
connection, and the last inverter again triggers the first, thus sustaining the oscillation.
Because a single inverter computes the logical NOT of its input, it can be shown that the
last output of a chain of an odd number of inverters is the logical NOT of the first input.
The final output is asserted a finite amount of time after the first input is asserted and the
feedback of the last output to the input causes oscillation.
A circular chain composed of an even number of inverters cannot be used as a ring
oscillator. The last output in this case is the same as the input. However, this configuration
of inverter feedback can be used as a storage element and it is the basic building block of
static random access memory or SRAM.
In this three-stage circuit, the oscillation period T of any of the inverter output voltages
can be expressed as the sum of six propagation delay times (in the waveform). we can
also express the oscillation period T in terms of the average propagation delay Tp, as
Tp = τphl1 + τplh1 + τphl2 + τplh2 + τphl3 + τplh3
Generalizing this relationship for an arbitrary odd number (n) of cascade-

connected inverters, we obtain f= 1= 𝑖

𝑇 2.𝑛.𝑇𝑝
Thus, the oscillation frequency (f) is found to be a very simple function of the average
propagation delay of an inverter stage.

49
Thus, the oscillation frequency (f) is found to be a very simple function of the average
propagation delay of an inverter stage.
● Open DSCH software and implement the circuit using gates present on the pallet.
● Stimulate the circuit and verify the truth table of Ring Oscillator.
● Save the file with .SCH extension.
● Go to Files=>Make Verilog file, to make Verilog file of the Ring Oscillator circuit
in DSCH software.
● Another file with same name but with .v extension will be saved.
● Open Microwind 3.1 software click on Compile=>Compile Verilog File.
● Select the file with .v extension.
● A Verilog code will be generated, compile the code.

● If no error is shown then click on Back to editor.

● CMOS layout of Ring Oscillator will be generated.
● Click on RUN and the output waveforms will be generated.
Architecture of Ring Oscillator in DSCH:
Verilog code

// DSCH3
// 09-09-2024 11:33:11
// C:\@@53$!(\DSCH\RingOscillator\[Link]

module example( O3,O2,O1);

50
output O3,O2,O1;
wire ;
not #(17) inv_1(O2,O1);
not #(17) inv_2(O1,O3);
not #(17) inv_3(O3,O2);
endmodule
// Simulation parameters in Verilog Format
// Simulation parameters
Layout design of Ring Oscillator in Microwind:

51
Waveform of Ring oscillator:

CONCLUSION:
Hence, we successfully studied and implemented implement CMOS Ring Oscillator
CMOS layout using DSCH and Verilog and observed its output in Microwind3.1 We saw
the astable behavior when odd numbers of inverters are connected into a cascade circuit.

52
 PRACTICAL: 14

AIM: To study and implement Full-Adder CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software THEORY:
An Adder is a digital circuit that performs addition of numbers. In many computers and
other kinds of processors adders are used in the arithmetic logic units or ALU. They are
also utilized in other parts of the processor, where they are used to calculate addresses,
table indices, increment and decrement operators, and similar operations.
Full-adder has three inputs and two outputs. The first two inputs are A and B and the third
input is an input carry designated as CIN. When a full adder logic is designed, we will be
able to string eight of them together to create a byte-wide adder and cascade the carry bit
from one adder to the next.
The output carry is designated as CARRY and the normal output is designated as SUM.
Truth Table to Full Adder:

INPUTS OUTPUTS

A B CIN Carry Sum

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

53
Procedure:

● Open DSCH software and implement the circuit using gates present on the pallet.

● Stimulate the circuit and verify the truth table of Full Adder.

● Save the file with .SCH extension.

● Go to Files=>Make Verilog file, to make Verilog file of the Full Adder circuit in
DSCH software.
● Another file with same name but with .v extension will be saved.

● Open Microwind 3.1 software click on Compile=>Compile Verilog File.

● Select the file with .v extension.

● A Verilog code will be generated, compile the code.

● If no error is shown then click on Back to editor.

● CMOS layout of Full Adder will be generated.

● Click on RUN and the output waveforms will be generated.

Logic Circuit of Full Adder in DSCH:

54
Verilog code: module
fullAdder(
C,B,A,Carry,Sum); input
C,B,A;utput Carry,Sum; wire
w5,w8,w9; xor #(23)
xor2_1(w5,A,B); xor #(16)

xor2_2(Sum,w5,C); and #(16)

and2_3(w8,B,A); and #(16)

and2_4(w9,w5,C); or #(16)
or2_5(Carry,w8,w9);
endmodule
// Simulation parameters in Verilog Format
always #1000 C= ~ C; #2000 B= ~ B; #4000
A= ~ A;
// Simulation parameters
// C CLK 10 10
// B CLK 20 20
// A CLK 40 40

55
Layout design of Full Adder in Microwind:

56
Waveform of Full Adder:

CONCLUSION:
Hence, we have generated a circuit which follows the truth table of Full Adder

57
 PRACTICAL: 15

AIM: To study and implement 2-bit Comparator CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software THEORY:
A 2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The figure
below shows the block diagram of a two- bit comparator which has four inputs and three
outputs.
The first number A is designated as A = A1A0 and the second number is designated as B
= B1B0. This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B)
and L (L= 1 if A<B).

Truth Table to Comparator:

58
The k-map simplification for the above truth table is as follows.

From the above k-map simplification, each output can be expressed as:

By using above obtained Boolean equation for each output, the logic diagram can be
implemented by using four NOT gates, seven AND gates, two OR gates and two Ex-NOR
gates.
The figure below shows the logic diagram of a 2-bit comparator using basic logic gates.
It is also possible to construct this comparator by cascading of two 1-bit comparators.

59
Procedure:
● Make a logic diagram as shown above in DSCH software.
● Save the file.
● Go to FILE > “Make Verilog File” and generate the Verilog file.
● Open Microwind Software.
● Go to COMPILE > “Compile Verilog File” and select the same Verilog file generated
using DSCH and generate CMOS layout.
● Now RUN it to generate the corresponding waveform.

Verilog code:
module 2bit_comp( B0,A1,A0,B1,AiB,AsB,AeB);
input B0,A1,A0,B1;
output AiB,AsB,AeB;
wire w3,w5,w7,w9,w12,w13,w14,w15;
wire w16,w17,w19,w20;
not #(17) inv_1(w3,A1);
not #(17) inv_2(w5,A0);
not #(17) inv_3(w7,B1);
not #(17) inv_4(w9,B0);
and #(16) and3_5(w12,A0,w9,w7);
or #(19) or3_6(AsB,w13,w12,w14);
and #(16) and3_7(w14,A1,A0,w9);
and #(16) and2_8(w13,w7,A1);
or #(19) or3_9(AiB,w15,w16,w17);
and #(16) and3_10(w15,w5,B1,B0);
and #(16) and3_11(w16,w3,w5,B0);
and #(16) and2_12(w17,B1,w3);
and #(16) and2_13(AeB,w19,w20);
xnor #(16) xnor2_14(w20,A1,B1);
xnor #(16) xnor2_15(w19,A0,B0);
endmodule

// Simulation parameters in Verilog Format

always
#1000 B0=~B0;
#2000 A1=~A1;
#4000 A0=~A0;
#8000 B1=~B1;
60
// Simulation parameters
// B0 CLK 10 10
// A1 CLK 20 20
// A0 CLK 40 40
// B1 CLK 80 80
// Simulation parameters in Verilog Format
always #1000 A1=~A1;
#2000 A0=~A0;
#4000 B1=~B1;
#8000 B0=~B0;
// Simulation parameters
// A1 CLK 10 10
// A0 CLK 20 20
// B1 CLK 40 40
// B0 CLK 80 80

Logic Circuit of 2-bit Comparator in DSCH:

61
Layout design of 2-bit Comparator in Microwind:

Waveform of 2-bit Comparator:

CONCLUSION:
Hence, we studied about the working of 2-bit Comparator using DSCH and Microwind 3.1
software.

62
 PRACTICAL: 16
AIM: To study and implement edge triggered D-flip flop CMOS layout using DSCH and
verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software THEORY:
The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to
prevent the S and R inputs from being at the same logic level.
One of the main disadvantages of the basic SR NAND Gate Bi-stable circuit is that the
in determinate input condition of SET = “0” and RESET = “0” is forbidden.
This state will force both outputs to be at logic “1”, over-riding the feedback latching
action and whichever input goes to logic level “1” first will lose control, while the other
input still at logic “0” controls the resulting state of the latch. But in order to prevent this
from happening an inverter can be connected between the “SET” and the “RESET” inputs
to produce another type of flip flop circuit known as a Data Latch, Delay flip flop, D-
type Bi- stable, D-type Flip Flop or just simply a D Flip Flop as it is more generally
called.
The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that
ensures that inputs S and R are never equal to one at the same time. The D-type flip flop
are constructed from a gated SR flip- flop with an inverter added between the S and the R
inputs to allow for a single D (data) input.
Then this single data input, labelled “D” and is used in place of the “Set” signal, and the
inverter is used to generate the complementary “Reset” input thereby making a level
sensitive D-type flip-flop from a level- sensitive SR-latch as now S = D and R = not D.
The circuit for edge triggered flipflop is as follows,

Truth Table to edge triggered D-flip flop:

63
Procedure:
● Open DSCH software and implement the circuit using gates present on the pallet.

● Stimulate the circuit and verify the truth table of D Flip-Flop.

● Save the file with .SCH extension.

● Go to Files=>Make Verilog file, to make Verilog file of the D Flip-Flop circuit in

DSCH software.
● Another file with same name but with .v extension will be saved.

● Open Microwind 3.1 software click on Compile=>Compile Verilog File.

● Select the file with .v extension.

● A Verilog code will be generated, compile the code.

● If no error is shown then click on Back to editor.

● CMOS layout of D Flip-Flop will be generated.

● Click on RUN and the output waveforms will be generated.

64
Logic Circuit of D Flip Flop in DSCH:

in2=D, out1=Q, out2=Q

Verilog code:
module d_ff( D,CLK,invQ,Q);
input D,CLK;
output invQ,Q;
wire w2,w5,w7,w8,;
nand #(20) nand2_1(invQ,w2,Q);
nand #(20) nand3_2(w2,w5,CLK,w7);
nand #(13) nand2_3(w8,w5,w7);
nand #(20) nand2_4(w7,D,w2);
nand #(20) nand2_5(Q,invQ,w5);
nand #(27) nand2_6(w5,CLK,w8);
endmodule
// Simulation parameters in Verilog Format
always
#1000 D=~D;
#2000 CLK=~CLK;
// Simulation parameters
// D CLK 10 10
// CLK CLK 20 20
65
 Layout design of D Flip Flop in Microwind:

Waveform of D Flip Flop:

CONCLUSION: Hence, we studied about the working of D flip flop using DSCH and
Microwind 3.1 software.
66