SRAM 6T CELL: STATIC NOISE MARGIN ANALYSIS
(130 nm)
Project Report
Presented by
Abhinay Chowhan Sabawat (23116004)
Ashhad Ali (23116018)
Ganga Karuvail (23116037)
VIth Semester
Submitted To,
Dr. Chitrakant Sahu,
for the subject of VLSI Design
Department of Electronics and Communications
National Institute of Technology Raipur
April 2026
Introduction
The 6-transistor (6T) SRAM cell is the standard topology for on-chip memory in CMOS processes. It consists of a
cross-coupled inverter pair (M1–M4) forming a bi-stable latch, and two NMOS access transistors (M5, M6)
controlled by the word line (WL). Supply voltage VDD = 1.3 V; technology: 130 nm CMOS.
This project presents the design, simulation, and Static Noise Margin (SNM) analysis of a 6T SRAM cell
implemented in 130 nm CMOS technology. The SNM is a key metric that quantifies the stability of the cell in
three operational modes:
• Hold Mode — the cell retains data when word line is de-asserted
• Read Mode — the cell is accessed for a read operation (most critical)
• Write Mode — a new value is written into the cell
The SNM is extracted using the butterfly curve method: plotting the voltage transfer characteristics (VTC) of both
inverters in the cross-coupled latch simultaneously. The side length of the largest square that fits inside each eye
of the butterfly curve equals the SNM.
The 6T SRAM cell consists of six transistors arranged as follows:
1. Cross-coupled inverter pair (M1–M2 NMOS and M3–M4 PMOS): forms the bi-stable storage latch storing
complementary data at nodes Q and Q_bar.
2. Two access transistors (M5 and M6, NMOS): connect the bit lines (BIT/BIT_bar) to the storage nodes
when the word line (WORD) is asserted high.
Supply voltage VDD = 1.3 V. The bit lines are driven by an NMOS access transistor on each side. An inverter
buffer (A1) provides the complementary BIT signal (RIGHT) from the BIT input (LEFT).
1. Hold State
Condition: WL = 0 V. Access transistors M5, M6 are OFF. Cell is fully isolated from bit lines — the latch retains
state freely.
Figure 1: Hold State Schematic (WORD = 0 V, BIT = 1.3 V)
Figure 2: Hold State Butterfly Curve — V(Q) [green], V(Q_bar) [blue]
Calculation
From Figure 2, with access transistors OFF, the two VTCs are undisturbed inverter characteristics.
• Curves intersect (metastable point) at Vₜₑₛₜ ≈ +0.05 V, where V(Q) ≈ V(Q_bar) ≈ 0.32 V.
• Each eye is symmetric. The smaller lobe is bounded vertically by 0 V (floor) and 0.32 V (crossing) →
height ≈ 0.32 V.
• Corresponding horizontal span ≈ 0.32 V.
SNM(Hold) = side of inscribed square ≈ 0.32 V (320 mV)
SNM(Hold) / VDD = 320 / 1300 ≈ 24.6 %
2. Read State
Condition: WL = 1.3 V. Both bit lines pre-charged to VDD = 1.3 V. Access transistors ON — cell is accessed.
M5 and M1 form a voltage divider that raises the "0"-side storage node, reducing the butterfly eye. This is the
read disturbance effect and sets the minimum SNM.
Figure 3: Read State Schematic (WORD = 1.3 V, BIT = 1.3 V)
Figure 4: Read State Results — V(Q) [green], V(Q_bar) [blue], I(Vtest) [red]
Calculation
From Figure 4, the access transistor forms a resistive divider with pull-down M1:
• V(Q) floor (read disturbance) ≈ 0.40 V — cannot reach 0 V because access transistor M5 is ON and BL =
VDD.
• Curves intersect at Vₜₑₛₜ ≈ +0.65 V, where V(Q) ≈ V(Q_bar) ≈ 0.65 V.
• Squeezed eye height = crossing − floor = 0.65 − 0.40 = 0.25 V; corresponding width ≈ 0.25 V.
• Peak I(Vtest) ≈ +11 μA at the transition, confirming cell current flow during read.
SNM(Read) = 0.25 V (250 mV)
SNM(Read) / VDD = 250 / 1300 ≈ 19.2 % (minimum SNM of the cell)
3. Write State
Condition: WL = 1.3 V. BIT = 0 V, BIT_bar = 1.3 V (writing logic "0" to Q). Access transistor M5 actively pulls
Q toward 0 V against the restoring pull-up PMOS M3. A positive Write SNM (> 0) confirms the cell is writable.
Figure 5: Write State Schematic (WORD = 1.3 V, BIT = 0 V)
Figure 6: Write State Results — V(Q) [green], V(Q_bar) [blue], I(Vtest) [red]
Calculation
From Figure 6, BIT = 0 V pulls Q strongly low, creating an asymmetric butterfly:
• Metastable crossing shifts left to Vₜₑₛₜ ≈ −0.40 V, where V(Q) ≈ V(Q_bar) ≈ 0.35 V.
• V(Q) floor ≈ 0 V (BIT = 0 V pulls Q to ground through M5).
• Write lobe height = 0.35 − 0.00 = 0.35 V; corresponding width ≈ 0.35 V.
• I(Vtest) is negative throughout (current flows Q → Q_bar through Vtest), peaking at −11 μA — confirming
write current direction.
SNM(Write) = 0.35 V (350 mV)
SNM(Write) / VDD = 350 / 1300 ≈ 26.9 %
Summary
The table below summarises the SNM results for all three modes:
Mode SNM (mV) SNM / VDD Remark
Hold 320 mV 24.6 % Symmetric butterfly; largest margin
Read 250 mV 19.2 % Smallest margin; read disturbance
Write 350 mV 26.9 % Cell writable; asymmetric butterfly
SNM hierarchy: Read SNM < Hold SNM < Write SNM — this is the expected and desired ordering for a well-
designed 6T SRAM cell.
Read SNM is the worst-case and dictates cell stability. At 250 mV (19.2 % of VDD), it is well above the
minimum threshold of ~10 % × VDD, confirming robust operation at 130 nm, VDD = 1.3 V.
A positive Write SNM (350 mV) confirms that the access transistors are strong enough to overpower the pull-up
devices and flip the stored state during a write operation.