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CDC RDC Explained

CDC (Clock Domain Crossing) involves data transfer between domains with different clock signals, which can lead to issues like metastability and data corruption, and solutions include double flip-flop synchronizers and handshake protocols. RDC (Reset Domain Crossing) addresses signals between blocks with different reset signals, where improper handling can cause functional failures, with solutions like reset synchronizers and glitch-free reset trees. Both concepts require careful design and verification to ensure reliable operation in digital systems.

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11 views3 pages

CDC RDC Explained

CDC (Clock Domain Crossing) involves data transfer between domains with different clock signals, which can lead to issues like metastability and data corruption, and solutions include double flip-flop synchronizers and handshake protocols. RDC (Reset Domain Crossing) addresses signals between blocks with different reset signals, where improper handling can cause functional failures, with solutions like reset synchronizers and glitch-free reset trees. Both concepts require careful design and verification to ensure reliable operation in digital systems.

Uploaded by

prawin Drifter
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) - Complete Explanation

1. CDC – Clock Domain Crossing

Definition: CDC refers to the transfer of data between two domains that operate on different clock
signals, which may be asynchronous or have different frequencies/phases.

Why it matters: Incorrect handling of CDC can result in metastability, glitches, or data corruption.

Common Problems:

• Setup/Hold violations
• Metastability
• Data loss or duplication

Solutions:

1. Double Flip-Flop Synchronizer - for single-bit signals.


2. Handshake Protocol - for safe multi-bit transfers.
3. Asynchronous FIFO - for burst/multi-bit data.
4. Gray Code Counters - used in FIFOs to avoid glitches.

Example (Verilog - Double FF Synchronizer):

reg sync_ff1, sync_ff2;


always @(posedge clk_b) begin
sync_ff1 <= async_signal;
sync_ff2 <= sync_ff1;
end

Tools:

• Synopsys VC CDC
• SpyGlass CDC
• Cadence JasperGold
• Questa CDC

2. RDC – Reset Domain Crossing

Definition: RDC deals with signals moving between blocks or domains controlled by different reset
signals, even if they share the same clock.

1
Why it matters: Unsynchronized or glitchy reset signals can lead to functional failures, especially during
reset deassertion.

Common Problems:

• Glitches during reset release


• Improper sequencing
• Partial resets

Solutions:

1. Reset Synchronizer - synchronizes asynchronous resets to the local clock domain.


2. Glitch-Free Reset Trees - structured and consistent reset signal propagation.
3. Hierarchical Reset Strategy - managed distribution of reset signals.

Example (Verilog - Reset Synchronizer):

reg rst_sync1, rst_sync2;


always @(posedge clk) begin
rst_sync1 <= ~async_reset_n;
rst_sync2 <= rst_sync1;
end
assign synced_reset = ~rst_sync2;

CDC vs RDC - Comparison

Feature CDC (Clock Domain Crossing) RDC (Reset Domain Crossing)

Involves Multiple clock domains Multiple reset domains

Risk Metastability, data loss Glitches, improper reset handling

Key Tools FIFOs, handshakes, synchronizers Reset synchronizers, linting tools

Common Fixes Multi-FF sync, FIFO, gray codes Reset trees, FF sync, structured reset

Design Tools VC CDC, JasperGold, SpyGlass Lint/formal RDC tools

Design Tips:

• Always synchronize any signal crossing clock or reset boundaries.


• For multi-bit data, use FIFO or handshake, not just flip-flops.
• Always simulate and verify CDC and RDC paths with proper tools.
• Treat reset signals with the same importance as clocks.

2
Need Visual Diagrams or More Examples? Feel free to ask for:

• CDC/RDC block diagrams


• FIFO implementation templates
• Cheat sheet for interviews

Prepared by ChatGPT | July 2025

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