Computer Organization and Architecture

Chapters 1–5 | Question Bank: 5 Theory Questions + 50 Objective Questions

SECTION A — Theory Questions (5)

Answer ALL questions. Each question requires a detailed written response. Cite relevant concepts from
Chapters 1–5.

Q1. Distinguish between Computer Architecture and Computer Organization. Using the
IBM System/370 as an example, explain how a family of computers can share the same
architecture but differ in organization. Why is this distinction important from a software
compatibility standpoint?
Answer Guide: Key points: Architecture = programmer-visible attributes (ISA, data types, I/O mechanisms).
Organization = operational units and their interconnections (hardware details transparent to programmer).
IBM S/370 ran the same software across models with different speeds/costs. Protects software investment.
Architectural compatibility allows programs to run on any model in the family.

Q2. Explain Moore's Law and discuss its implications for modern processor design. What
physical phenomena are causing Moore's Law to slow down, and what architectural
strategies have been adopted to continue improving performance despite these
limitations?
Answer Guide: Key points: Moore's Law – transistor count doubles ~every 2 years. Implications: faster,
cheaper, smaller chips. Physical limits: quantum tunneling (electrons leak through thin gates), RC delay,
heat dissipation/power density. Architectural responses: multicore processors, out-of-order execution,
SMT/Hyper-Threading, larger caches, GPU/MIC accelerators.

Q3. Describe the Von Neumann architecture and explain the complete instruction cycle
(fetch-decode-execute). Include in your answer the roles of the MAR, MBR, PC, and IR
registers, and explain how interrupts affect the normal instruction cycle.
Answer Guide: Key points: Von Neumann = single memory for data and instructions; addressable by
location; sequential execution. Fetch: PC → MAR; memory → MBR → IR; PC incremented. Decode: IR
interpreted. Execute: action performed. MAR = address register; MBR = data buffer; PC = next instruction
address; IR = current instruction. Interrupts suspend current program, save state, execute ISR, restore state.
Classes: program, timer, I/O, hardware failure.

Q4. Compare and contrast the three cache mapping techniques: Direct Mapping, Fully
Associative Mapping, and Set-Associative Mapping. For each, describe the address
structure, the mapping algorithm, the advantages and disadvantages, and give the formula
for tag size.
Answer Guide: Key points — Direct: block → single fixed cache line (line = block mod m); simple/fast
lookup; conflict misses; tag = (s-r) bits. Associative: block → any cache line; check all tags in parallel; no
conflict misses; expensive hardware; tag = s bits. Set-Associative: block → fixed set, any line within set
(k-way); compromise; tag = (s-d) bits. LRU is the standard replacement algorithm for associative techniques.

Q5. Explain the concept of the memory hierarchy in computer systems. Discuss how
DRAM and SRAM differ in terms of construction, performance, cost, and typical usage.
Additionally, describe DDR SDRAM and explain the three techniques it uses to achieve
higher data rates than standard SDRAM.
Answer Guide: Key points — Hierarchy: Registers > L1 > L2/L3 > Main Memory > Secondary Storage;
exploits locality. DRAM: capacitor-based, needs refresh, denser, cheaper, slower → main memory. SRAM:
flip-flop-based, no refresh, faster, more expensive → cache. DDR: (1) transfers on both rising and falling
clock edges; (2) higher bus clock rate; (3) internal buffering/prefetching. Result: doubles bandwidth
 compared to single-data-rate SDRAM.

SECTION B — Objective Questions (50)

Circle the letter of the best answer for each question. Correct answers are indicated after each question.

Q1. Which term refers to the attributes of a computer system visible to a programmer?
A. Computer Organization
B. Computer Architecture
C. Computer Structure
D. Computer Function
✓ Answer: B

Q2. The IBM System/370 demonstrated that different computer models could share the
same _____ while differing in organization.
A. Operating system
B. Hardware components
C. Architecture (ISA)
D. Cache structure
✓ Answer: C

Q3. Which is NOT one of the four basic functions a computer can perform?
A. Data processing
B. Data storage
C. Data compilation
D. Data movement
✓ Answer: C

Q4. The four main structural components of a computer are CPU, Main Memory, I/O, and:
A. ALU
B. System Interconnection
C. Cache
D. Registers
✓ Answer: B

Q5. Which component of the CPU performs arithmetic and logical operations?
A. Control Unit
B. Registers
C. ALU
D. CPU Interconnection
✓ Answer: C

Q6. In a multicore system, the term 'core' refers to:

A. The entire processor chip
B. The system bus
C. An individual processing unit on the chip
D. The cache hierarchy
✓ Answer: C
Q7. Cache memory is positioned between the processor and main memory to:
A. Store the operating system
B. Increase power efficiency
C. Speed up memory access using locality
D. Replace registers
✓ Answer: C

Q8. The stored-program concept is attributed to which mathematician?

A. Alan Turing
B. Gordon Moore
C. John von Neumann
D. Gene Amdahl
✓ Answer: C

Q9. Which generation of computers first used transistors?

A. First generation
B. Second generation
C. Third generation
D. Fourth generation
✓ Answer: B

Q10. The invention of the integrated circuit occurred in:

A. 1947
B. 1952
C. 1958
D. 1964
✓ Answer: C

Q11. Moore's Law states that the number of transistors on a chip approximately doubles
every:
A. Six months
B. One year
C. Two years
D. Five years
✓ Answer: C

Q12. The IBM System/360, announced in 1964, was significant because it was:
A. The first transistor-based computer
B. The first planned family of compatible computers
C. The first computer with cache memory
D. The first multicore processor
✓ Answer: B

Q13. Amdahl's Law is used to predict:

A. Cache hit ratio
B. Maximum speedup from parallelism
C. Power consumption of a chip
D. Memory access time
✓ Answer: B
Q14. In Amdahl's Law, if 80% of a program is parallelizable and run on 4 processors, the
speedup is approximately:
A. 4.0
B. 2.5
C. 3.2
D. 1.6
✓ Answer: B

Q15. Little's Law is expressed as L = λW. What does λ represent?

A. Average number of items in the system
B. Average time in the system
C. Average arrival rate
D. Average service time
✓ Answer: C

Q16. Which technique issues multiple instructions simultaneously in a single clock cycle?
A. Pipelining
B. Superscalar execution
C. Branch prediction
D. Out-of-order execution
✓ Answer: B

Q17. RC delay in processors is caused by shrinking interconnect wires because:

A. Resistance decreases as wires shrink
B. Resistance and capacitance both increase as wires shrink
C. Voltage increases with density
D. Clock frequency decreases
✓ Answer: B

Q18. Which processing unit was originally designed for graphics but is now used for
general parallel computing?
A. MIC
B. DSP
C. GPU
D. FPU
✓ Answer: C

Q19. Simultaneous Multithreading (SMT) is considered a hybrid technique because it

combines:
A. RISC and CISC
B. Superscalar and hardware multithreading
C. Pipelining and caching
D. Static and dynamic branch prediction
✓ Answer: B

Q20. The main cause of the performance gap between processors and main memory is
called:
A. RC delay
B. Memory latency / memory wall
C. Power density problem
 D. Thermal throttling
✓ Answer: B

Q21. Which of the following is NOT a technique used to improve microprocessor speed?
A. Branch prediction
B. Increasing word size to 64 bits
C. Pipelining
D. Out-of-order execution
✓ Answer: B

Q22. MIC (Many Integrated Core) differs from a standard multicore processor in that it
contains:
A. Fewer, more powerful cores
B. A very large number of homogeneous general-purpose cores
C. Only GPU cores
D. Heterogeneous cores of different types
✓ Answer: B

Q23. In the Von Neumann architecture, the Program Counter (PC) holds:
A. The current instruction being executed
B. The address of the next instruction to fetch
C. The result of the last ALU operation
D. The memory address of the stack
✓ Answer: B

Q24. The Memory Address Register (MAR) is used to:

A. Hold data read from or written to memory
B. Hold the address of the memory location to be accessed
C. Store the current instruction
D. Count clock cycles
✓ Answer: B

Q25. Direct Memory Access (DMA) is beneficial because it:

A. Increases processor clock speed
B. Allows I/O transfers without constant CPU involvement
C. Replaces the need for main memory
D. Eliminates the need for interrupts
✓ Answer: B

Q26. Which class of interrupt is triggered by a timer expiring?

A. Program interrupt
B. I/O interrupt
C. Timer interrupt
D. Hardware failure interrupt
✓ Answer: C

Q27. The width of the data bus is important because it determines:

A. Maximum clock frequency
B. Number of bits transferred per cycle
C. Maximum number of I/O devices
 D. Size of the instruction set
✓ Answer: B

Q28. The address bus width determines:

A. The maximum number of I/O operations per second
B. The number of data bits per transfer
C. The maximum addressable memory capacity
D. The speed of cache access
✓ Answer: C

Q29. The control bus carries:

A. Only data between CPU and memory
B. Command and timing signals to coordinate bus usage
C. Only memory addresses
D. Interrupt vectors
✓ Answer: B

Q30. QPI (Quick Path Interconnect) uses which data transfer method?
A. Parallel shared bus
B. Serial shared bus
C. Packetized point-to-point transfer
D. Token ring protocol
✓ Answer: C

Q31. In QPI, a 'flit' consists of a 72-bit payload plus an 8-bit:

A. Header
B. CRC (Cyclic Redundancy Check)
C. Address field
D. Priority flag
✓ Answer: B

Q32. Which QPI layer is responsible for cache coherency?

A. Physical Layer
B. Link Layer
C. Routing Layer
D. Protocol Layer
✓ Answer: D

Q33. Which cache mapping function is the simplest but suffers most from conflict misses?
A. Associative mapping
B. Set-associative mapping
C. Direct mapping
D. Random mapping
✓ Answer: C

Q34. In direct mapping, the cache line for a memory block is determined by:
A. The most recently used algorithm
B. block number modulo number of cache lines
C. A hash of the data contents
D. The size of the data block
 ✓ Answer: B

Q35. Fully associative mapping allows a memory block to be placed in:

A. Only one specific cache line
B. Any line within a specific set
C. Any line in the entire cache
D. Only the first available cache line
✓ Answer: C

Q36. The LRU replacement algorithm replaces the cache line that:
A. Was the most recently used
B. Was used least frequently overall
C. Has been in cache the longest without being referenced
D. Was loaded first into the cache
✓ Answer: C

Q37. A Victim Cache is typically placed between:

A. CPU registers and L1 cache
B. L1 direct-mapped cache and the next memory level
C. L2 and L3 cache
D. Main memory and secondary storage
✓ Answer: B

Q38. In a set-associative cache with k=2 (2-way), each set contains:

A. One cache line
B. Two cache lines
C. k² cache lines
D. A variable number of cache lines
✓ Answer: B

Q39. Virtual memory allows programs to:

A. Access cache without the OS
B. Address memory logically, independent of physical memory size
C. Run without a CPU
D. Directly access disk storage as RAM
✓ Answer: B

Q40. The Memory Management Unit (MMU) is responsible for:

A. Managing cache replacement
B. Translating virtual addresses to physical addresses
C. Controlling DMA transfers
D. Scheduling processes
✓ Answer: B

Q41. In direct mapping, the tag size is given by:

A. s bits
B. r bits
C. (s – r) bits
D. (s + r) bits
✓ Answer: C
Q42. Which replacement algorithm is the most popular due to its simplicity and
effectiveness?
A. FIFO
B. Random
C. LFU
D. LRU
✓ Answer: D

Q43. DRAM stores bits as charge on capacitors and requires periodic refreshing because:
A. Capacitors are unreliable
B. Charge leaks away over time
C. Flip-flops reset automatically
D. The bus clock erases data
✓ Answer: B

Q44. SRAM is preferred for cache memory rather than main memory because it is:
A. Denser and cheaper
B. Non-volatile
C. Faster and does not need refresh
D. More energy efficient
✓ Answer: C

Q45. Which memory type is non-volatile, written at fabrication time, and cannot be altered?
A. DRAM
B. SRAM
C. ROM
D. PROM
✓ Answer: C

Q46. PROM differs from ROM in that:

A. It can be erased with UV light
B. It can be written once by the user after fabrication
C. It is volatile
D. It uses capacitors for storage
✓ Answer: B

Q47. DDR SDRAM achieves higher bandwidth than standard SDRAM primarily by:
A. Using a wider data bus
B. Transferring data on both rising and falling clock edges
C. Running at a lower voltage
D. Increasing capacitor size
✓ Answer: B

Q48. Flash memory uses how many transistors per bit?

A. Four
B. Two
C. Three
D. One
✓ Answer: D
Q49. A 'hard failure' in memory is characterized by:
A. Temporary bit flip from alpha particles
B. Permanent physical defect causing stuck or erratic bits
C. A soft error corrected by Hamming code
D. Power supply fluctuation
✓ Answer: B

Q50. Interleaved memory improves performance by:

A. Using faster SRAM for all memory
B. Allowing multiple memory banks to be accessed simultaneously
C. Reducing the number of cache levels needed
D. Connecting memory directly to the CPU without a bus
✓ Answer: B

End of Question Bank — Chapters 1–5 | COA 10th Ed. (Stallings)