ATE–Scan Interface Control Unit: Deep Analysis

Executive Summary: The interface between Automatic Test Equipment (ATE) and on-chip scan chains is
crucial for production testing of digital ICs. This includes standard JTAG (IEEE-1149.x) boundary-scan or
custom scan protocols, timing and synchronization of the test clock, data signals (TCK/TMS/TDI/TDO or
equivalents), and control logic (TAP controllers or custom FSMs) on-chip. Key considerations are ATE pin
limitations, vector memory, timing accuracy, and power constraints during test. Test-data volume and
throughput are constrained by the ATE’s available scan channels and memory 1 , so on-chip compression,
multi-site testing, or off-load schemes are often employed. Error detection/recovery, power control (low
shift activity), and ATE-specific requirements (vector formats like WGL/STIL, pin-electronics settings, timing
formats) must also be addressed. The control unit’s Verilog RTL (e.g. TAP controller FSM) orchestrates the
scan sequence. Open-source examples include JTAG TAP cores (e.g. FreeCores) and scan-chain wrappers
(e.g. [scan_wrapper]). Vendor application notes (e.g. Advantest) and patents (e.g. FPGA-offload test boards
1 ) document practical constraints (single-channel ATEs, limited memory) and solutions. We compare

relevant papers/projects (below) and provide example state-machine and block diagrams. Assumptions (if
not specified) include a generic mid-range ATE (e.g. Advantest V93000) with limited channels, scan chains of
typical length (thousands of bits), and moderate throughput requirements.

Protocols and Signals

ATE–scan interfaces typically use the IEEE-1149.x JTAG signals: TCK (test clock), TMS (mode select), TDI (test-
data in) and TDO (test-data out), with optional reset TRST 2 . This test access port (TAP) drives on-chip
boundary-scan or core-scan cells. In many SoCs, a standard JTAG TAP controller handles these signals. In
simpler custom designs, one can multiplex fewer I/O pins into many scan chains using a wrapper or
sequencer (see Scan Chains and Wrappers below).

• JTAG TAP Controller (1149.1): Implements an FSM (see below) that sequences through Test-Logic-
Reset, Run-Test/Idle, Select-IR/DR, Capture, Shift, Update, etc. based on TMS at each TCK rising edge 2 .
The TAP selects data or instruction registers for shifting test vectors in/out. This standard interface
was originally for boundary-scan but is widely extended to on-chip test (MBIST, IOBIST, etc.) 2 .
• Custom Scan Protocols: Some chips use proprietary scan schemes (e.g. loading multiple scan
chains in parallel or special “scan-in” instructions) to reduce pin count. For example, advanced
compression logic may allow a ScanIn instruction to load all core scan registers in a single shifted
frame 3 . Other designs simply use multiple data inputs or separate capture modes. The control
unit must decode any such custom instructions and sequence the chains appropriately.

Protocols differ mainly in how many pins and clocks are used. For boundary-scan/JTAG, one TDI/TDO pair
can cover many chains serially; with compression, a single I/O pair may service 10–100 smaller scan chains
4 . In contrast, a “plain” scan would need one I/O pair per chain. A key ATE constraint is thus the pin

count: reducing ATE pads often means inserting on-chip multiplexing/decompression. Notably, Tenentes &
Kavousianos report a “very low pin-count interface: only one tester channel is needed to download the
compressed test data” 5 .

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Timing, Synchronization, and Clocking
The ATE provides the test clock (TCK) and latches data on its edges. Scan shift operations are synchronous to
TCK, but capture phases may require multiple clocks (for launch-capture cycles) between loads. Critical
timing aspects include:
- Clock Frequency: Typical ATE TCK rates range from a few MHz up to ~10s of MHz. The on-chip control unit
must synchronize to TCK and ensure setup/hold for scan cells. Designers often assume the worst-case ATE
clock for timing closure.
- Synchronization: The TAP FSM (or custom FSM) uses TMS and TRST to move between states. No extra
handshake is usually needed beyond the TMS sequence. However, advanced schemes might use repeat or
hold commands: e.g. many ATEs support a “repeat” command to resend the last bit, which compression
algorithms exploit to minimize vector memory 6 7 . The control unit need only handle that implicitly by
expecting repeated bits.
- Vector Formats: ATE patterns are often specified in standard formats (e.g. WGL, STIL), then compiled into
tester binaries. Our scope is the chip-side, but note that the on-chip logic must align with the ATE’s timing
resolution. In some cases, microcodes or delays (T-setups, hold times) are provided in the vector file 8 .
The control unit typically treats the incoming bits as bitstreams without self-timing, relying on ATE to meet
timing.

ATEs also have pin electronics (source drivers, sense amps) that can limit slew rate or drive strength; a low-
power scan design (like [12]) tends to produce fewer simultaneous switching bits to ease ATE drive load.

State Machines and Control Logic

stateDiagram
[*] --> Test_Logic_Reset
Test_Logic_Reset --> Run_Test_Idle: TMS=0
Test_Logic_Reset --> Test_Logic_Reset: TMS=1
Run_Test_Idle --> Select_DR_Scan: TMS=1
Run_Test_Idle --> Run_Test_Idle: TMS=0
Select_DR_Scan --> Capture_DR: TMS=0
Select_DR_Scan --> Select_IR_Scan: TMS=1
Capture_DR --> Shift_DR: TMS=0
Capture_DR --> Exit1_DR: TMS=1
Shift_DR --> Shift_DR: TMS=0
Shift_DR --> Exit1_DR: TMS=1
Exit1_DR --> Pause_DR: TMS=0
Exit1_DR --> Update_DR: TMS=1
Pause_DR --> Pause_DR: TMS=0
Pause_DR --> Exit2_DR: TMS=1
Exit2_DR --> Update_DR: TMS=0
Exit2_DR --> Shift_DR: TMS=0
Update_DR --> Run_Test_Idle: TMS=0
Update_DR --> Select_DR_Scan: TMS=1
Select_IR_Scan --> Capture_IR: TMS=0
Select_IR_Scan --> Test_Logic_Reset: TMS=1

2
 Capture_IR --> Shift_IR: TMS=0
Capture_IR --> Exit1_IR: TMS=1
Shift_IR --> Shift_IR: TMS=0
Shift_IR --> Exit1_IR: TMS=1
Exit1_IR --> Pause_IR: TMS=0
Exit1_IR --> Update_IR: TMS=1
Pause_IR --> Pause_IR: TMS=0
Pause_IR --> Exit2_IR: TMS=1
Exit2_IR --> Update_IR: TMS=0
Exit2_IR --> Shift_IR: TMS=0
Update_IR --> Run_Test_Idle: TMS=0
Update_IR --> Select_DR_Scan: TMS=1

The above is a typical IEEE-1149.1 TAP FSM (fully JTAG-compliant 2 ). On-chip, this logic is implemented in
Verilog as a collection of flip-flops and combinational logic (see table below for examples). In custom
protocols, a simpler FSM might only include “reset, load, shift, capture, unload” states. For example, in
secure-scan architectures the authors include a Control Unit FSM that manages LFSR seeds and when to
update obfuscation keys 9 . This control unit typically comprises counters and small registers, triggered by
external commands (like a “start scan” input) or by the TAP state machine.

Verilog Examples: Open-source TAP controllers exist (e.g. FreeCores jtag) that illustrate the FSM logic. For
instance, tap_top.v in FreeCores asserts TDO, TDO_EN, and update signals on TCK edges to implement
the 16-state JTAG TAP 10 11 . Custom wrappers (e.g. for a single long scan chain) can use a state bit or
counter to handle “capture” vs “shift” vs “update” cycles. Simulation can be done by driving TDI/TMS from a
Verilog testbench or even co-simulating with ATE pattern files (see [55] for an emulation approach, though it
is a hardware emulation paper, not specifically ATE).

Test Data Volume, Compression, and Throughput

Large designs generate massive scan test vectors, but ATE memory is limited. For example, a high-end
tester (e.g. Verigy V93000) may have only ~8 scan channels per device and a few hundred Mb/channel 1 .
This bottleneck drives on-chip compression (decoders) and low-pin interfaces.

• Compression Techniques: Many schemes (Huffman, run-length, LFSR reseeding) reduce the data
sent. Tenentes et al. use a combined statistical + linear scheme, which they claim outperforms
existing methods on IP cores 12 13 . Crucially, their design “does not require synchronization
between the ATE and the CUT” and fits in very few scan shifts 5 .

• ATE Repeat Command: Modern ATEs support a “repeat last bit” instruction to save memory. Test-
compression algorithms exploit this (see [17]) to reduce pattern volume. If a long run of 0/1 occurs,
the ATE can simply repeat the bit without reloading it. The control logic must accommodate repeated
bits, but otherwise the TAP just shifts them normally (no special new pin needed) 6 7 .

• Throughput: Test time ≈ (number of scan cycles × shift period). The test-time is dominated by the
largest scan-chain length and number of patterns 14 . Using compression or partial-scan can reduce
cycles per pattern. Multi-site testing (simultaneous devices) is possible only if each device fits in the
available channels/memory. The cited patent highlights that with >4 chains, only one DUT per ATE

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 can be tested at a time 1 , so compression or FPGA off-load was proposed to enable multi-site (see
[5]).

• Scan-In/Scan-Out Timing: ATEs allow control of clock spacing. For example, in boundary-scan, each
bit (TDI) is presented on TCK rising edges, and the chip’s scan cells latch on the same edge. The
control unit need only ensure data stability before the clock. Capture pulses (launch/capture for
transition faults) can be a double cycle or separate instruction. The Verilog FSM asserts
capture_dr , then after a number of TCK cycles asserts update_dr to move to functional mode
15 16 . The FSM code (see e.g. FreeCores) explicitly sets capture_dr , shift_dr , update_dr
outputs which can be used to gate scan clock or data paths.

Scan Chains, Wrappers, and Boundary-Scan vs Custom

Boundary Scan (IEEE 1149.x)

Boundary-scan chains connect I/O pins and a few internal signals via a standard TAP. The ATE only sees the
chip edges, so all internal flip-flops are invisible except through scan registers. The advantage is a
standardized interface; the disadvantage is often slower test (long chains) and limited control of internal
scan cells. ATE vector formats (STIL, SVF, etc.) describe how to shift into the boundary-scan register. The
Advantest note explains that a standard TAP has 5 pins (TCK, TMS, TDI, TDO, TRST) 2 and can be extended
with Scan-Test Modes to reconfigure scan chains (e.g. concatenate all chains for debug) 17 .

Custom Scan Wrappers (IEEE 1500, etc.)

In SoCs, IP cores may have their own scan wrappers (IEEE-1500) or shared test buses. These on-chip
wrappers often mimic JTAG but allow multiple “inner” scan chains. In practice, a common pattern is: a TAP
selects an instruction (e.g. EXTEST, SAMPLE), then a test clock shifts data through a chosen chain (or chains).
If the wrapper implements a 1500 bus, then additional signals (TMSC, etc.) might be used (not detailed
here). Our focus is on the control logic: the TAP must decode a TEST or BYPASS instruction to select which
core’s scan chain is active. This is typically done by additional state machine logic gated on the TAP states.

Block Diagram (Scan Wrapper Example):

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Figure: Example scan chain wrapper (from [49]): two scan flip-flops feed latch registers and a DUT (green), under
control of scan_en , clk , and latch . Data on inputs (“data_o”) shifts through the grey scan flops into blue
latch elements, then into the DUT. Output (“data_i”) is shifted back out after the capture cycle. This simple design
illustrates using scan chains instead of multiplexed I/O 18 .

The above scan_wrapper design (Apache-2.0 open-source code) “uses scan chain flipflops and latches to
first latch in data, and then capture the output” 18 . The grey blocks are shift-register flops clocked by TCK,
and blue blocks hold data to feed the DUT. A control FSM ( scan_controller ) toggles scan_en and
latch to first load inputs, then drive the DUT, then unload outputs. Such wrappers are synthesized in
Verilog (e.g. see scan_wrapper.v in the repo 18 ) and could be inserted around any IP.

Testbench and Simulation Strategies

Simulation of scan interfaces is typically done by writing a Verilog testbench that drives TMS/TDI/TCK (or the
scan_en/clk for custom designs). For boundary-scan, one can use a BSDL-based sequence (often exported
as STIL/SVF) and apply it as vectors. The Fault toolchain (open source) even supports a Tap insertion that
lets users simulate JTAG sequences on a netlist 19 . In hardware emulation, frameworks like SCE-MI (seen in
[55]) send test packets between host and DUT, effectively treating scan operations as co-simulation.

Debugging often requires a “scan-dump” mode: e.g. Markus Seuring notes a mode that concatenates all
chains into one long chain for easy visibility 17 . In simulation, one might insert hooks to output the content
of scan cells after an operation.

Power and I/O Constraints

During scan shifting, many flip-flops toggle; this can cause high IR-drop or exceed the switching limits of
test pins. To mitigate:
- Low Shift Activity: Some compression/decompression schemes (e.g. [26]) are “low-power scan-based”
designs that minimize bit toggles. Tenentes et al. specifically aim for “very low shift switching activity” to

5
improve yield 20 . Another patent recommends evenly spacing shift pulses.
- Clock Gating: Often, the test clock to inactive chains can be gated off to save dynamic power. The TAP’s
run_test_idle vs shift_dr signals determine whether shifting occurs 21 22 .
- IO Voltage Levels: Some ATEs allow different drive strengths or pull-ups. The scan cells typically expect
standard CMOS levels. Care must be taken if the ATE drives at slightly different voltages (level shifting in the
interface wrapper may be needed).

Power constraints also shape scan architecture: extremely long chains (or high-speed scan clocks) might
exceed ATE or chip limits, so designers balance chain length and number of chains vs frequency.

ATE-Specific Requirements
ATEs have particular requirements on the test patterns and timing:
- Vector Formats: As mentioned, tests are usually authored in a high-level format (WGL, STIL, SVF, STAPL)
then converted. The interface control unit must essentially accept a stream of bits with unknown “meaning”
– the meaning is carried in how the TAP FSM interprets states, not in the bit values themselves.
Nonetheless, designers ensure the FSM transitions match the expected vector protocol from ATPG tools 8 .
- Pin Electronics: The ATE pins (channels) used for scan may need to be configured as digital input/output
with certain drive/slew. For high-pin-count patterns, the ATE must tri-state or drive each bit. The control
logic often uses an output-enable pin (e.g. TDO_OE ) as in [24] to gate TDO only when in Shift state.
- Timing Accuracy: ATE specifications for timing (setup/hold on TDI, maximum skew, etc.) constrain the on-
chip design. For example, the control unit should meet the worst-case clock-to-output delay so that the ATE
captures TDO correctly. Some ATEs allow “data alignment” adjustments; designers must verify timing during
synthesis.

• ATE Control Lines: Besides the basic TAP signals, some testers provide global hardware enable lines
(e.g. reset_n) that can reset the chip to test mode. The interface logic should use TRST/TLR
sequences to ensure a known starting state.

Implementation and Reuse Considerations

• Verilog RTL: The TAP controller and wrapper logic are synthesizable RTL. Standard cell synthesis
(ASIC) or FPGA implementation is straightforward. For example, FreeCores’ tap_top.v compiles in
both Xilinx and ASIC libraries. Designers should check area overhead: JTAG TAP is small (<100 gates),
but compressors/decompressors can be large. Tenentes reports a small XOR-based decompressor
and minimal FSM overhead 12 .
• FPGA Implementation: Some test boards use an FPGA as a “scan load board” 1 . In that case, an
FPGA implements the control logic and possibly generates the scan clocks for multiple DUTs in
parallel. The on-chip interface might then be simplified (e.g. a single latch for an incoming pattern).
If implementing on an FPGA, one can use on-chip PLLs for TCK or replicate channels.
• Licensing and Reuse: Open-source cores (Apache 2.0 or LGPL) can be embedded. For instance, the
open Fault toolchain is Apache-licensed 19 . The FreeCores TAP is LGPL (older OpenCores style). The
“scan_wrapper” is Apache-2.0. Using these can jump-start design. Patents should be checked if
commercial (e.g. US8127187 may affect FPGA load boards). Vendor IP (e.g. Cadence or Synopsys
compression blocks) are usually proprietary.

6
 • Testbench: To validate, one builds a scan testbench that drives TDI/TMS/TCK per STIL or SVF pattern
files. Fault’s JTAG insertion can auto-generate such patterns and compare DUT outputs to expected
ones (via stuck-at simulation). This helps verify the control FSM and wrapper.

Patent and Application Notes

A U.S. patent (US 8,127,187 B2, 2012) addresses similar issues: it describes using an FPGA-based “load
board” to overcome ATE limits 1 . The idea is to buffer or decompress patterns off-chip, so that the chip
under test sees a simpler interface. The patent notes key ATE limits: e.g. an ATE channel often has <8 scan
lines and <256Mb memory per channel, capping test throughput 1 . It also sketches a control unit on the
FPGA that sequences TCK/TDI and handles handshaking with the ATE.

Advantest’s application note (Markus Seuring, 2011) provides background on scan testing. It defines the
JTAG TAP pins (TCK, TDI, TMS, TDO, TRST) and their roles 2 . It also notes that scan compression lets one
ATE I/O serve many chains (10–100×) 4 , greatly reducing test time. This aligns with academic proposals:
e.g. Tenentes et al. aim for a single-channel interface 5 .

Tables: Summary of Key References and Projects

Code/
Authors / Key
Title / Project Year Venue/Type Verilog Relevance
Source Contribution
Availability

Unified
Test-Data
compression
Volume and
combining Multi-core SoC
Scan-Power
V. Tenentes, symbol+linear; testing with
Reduction with ICCAD (None;
X. 2011 single tester narrow ATE
Low ATE Conference algorithmic)
Kavousianos channel; very interface; low-
Interface for
low shift power pin solution.
Multi-Core
and test length
SoCs 13
5 23

Statistical+linear
High-Quality Test data
compression;
Statistical Test compression;
V. Tenentes, low-fill-rate &
Compression (None; on-chip
X. 2013 IEEE TCAD low-power;
with Narrow algorithmic) decompressor;
Kavousianos supports multi-
ATE Interface low pin-count
site with one
24 25 ATE.
ATE channel 12

7
 Code/
Authors / Key
Title / Project Year Venue/Type Verilog Relevance
Source Contribution
Availability

Obfuscated
scan
architecture
Secure Scan
(DOS) with LFSR Illustrates
and Test Using (None;
X. Wang, D. key and XOR scan control
Obfuscation architecture/
Zhang, M. 2018 IEEE TCAD shadow chain; unit design;
Throughout patent
He, et al. includes a secure scan
Supply Chain focus)
Control Unit to logic and FSM.
26
manage
obfuscation
updates 9

Off-load scan
testing to FPGA
Patent Describes
board to bypass
US8127187B2: A. Nicholson practical ATE-
ATE channel/
ATE IC scan test et al. (None; interface limits
2012 US Patent memory limits;
using FPGA- (Mentor patent) and FPGA
handshaking
based system Graphics) control unit
ATE↔FPGA and
1 for scan.
multi-DUT
support 1

Provides
Tutorial on scan
industry
An test; defines
context: JTAG
Introduction to JTAG TAP (None;
M. Seuring Advantest signals, test
Scan Test for 2011 signals; application
(Verigy) App Note mode usage,
Test Engineers describes low- note)
compression
– Part 1 2 pin scan
concept 4
compression.
2 .

Open-source
Integrated reference
M.
Fault (Open- ATPG, scan design;
Abdelatty, IEEE Yes – GitHub
Source DFT insertion, and includes
M. Gaber, M. 2021 Design&Test / (Apache-2.0)
Toolchain) JTAG (TAP) Verilog TAP
Shalan et al. WOSET 2019 19
19 insertion in one and support
(AUC)
flow 19 . for custom
scan.

8
 Code/
Authors / Key
Title / Project Year Venue/Type Verilog Relevance
Source Contribution
Availability

Fully Example
IEEE-1149.1 Verilog TAP for
FreeCores FreeCores compliant TAP on-chip
Yes – GitHub
JTAG TAP (open- 2013 GitHub Verilog core; interface;
(LGPL)
Controller source) implements the reference for
standard 16- state machine
state JTAG FSM. logic.

Verilog
POC scan-chain
example of
wrapper: uses
scan-control
scan_wrapper M. Venn flops & latches Yes – GitHub
FSM and data
(Demo Scan (open- 2022 GitHub to serially load (Apache-2.0)
path; low-
Chain) 18 source) 8-bit inputs and 18
speed scan
capture 8-bit
interface
outputs 18 .
example.

Notes: The table links (【*†L..】) refer to excerpts in this report. Academic papers [29],[26],[44] and vendor
notes [41] give architectural details; GitHub projects [48],[49] provide code.

Each reference illustrates aspects of the ATE–scan interface. For instance, Tenentes et al. target single-
channel ATE test of multi-core SoCs 5 . Seuring’s note covers the standard TAP signals 2 and shows how
compression shrinks pin count 4 . The Fault toolchain automates scan insertion and provides a ready TAP
FSM 19 . The scan_wrapper demo uses simple Verilog FSM ( scan_controller ) to latch and shift data
18 , illustrating how one might implement an ATE-facing scan controller. In all these, Verilog FSMs move
through capture and shift phases under TCK/TMS control; code snippets from FreeCores (shown above)
exemplify how to write these states.

Diagrams: The state machine above is a mermaid diagram of the JTAG TAP (read transitions as “on TMS=x”).
The block diagram (embedded) shows one way to convert parallel I/O to a serial scan chain in hardware.
One could similarly draw a flowchart (e.g. with mermaid) of the ATE test sequence, but due to space we limit
to the state machine.

Assumptions: Target technology is generic digital CMOS; ATE assumed like Advantest/Teradyne with ~8-16
channels and multi-MHz timing. Scan chain lengths up to a few thousand bits are typical. If higher
throughput is needed, multiple channels or sites would be used, but if limited, techniques like compression
or FPGA off-load (patented) become important. No proprietary restrictions (beyond patents) are assumed.
The focus has been on digital control logic; analog aspects (IO buffers, IDDQ modes) follow standard
practice.

Sources: The foregoing is drawn from primary sources: IEEE/ACM papers 13 27 26 , patents 1 ,
application notes 2 4 , and open-source code/docs 19 18 . Where specific data (e.g. ATE memory limits)

9
was not found in publications, we noted it explicitly from the patent 1 . All cited figures refer to these
sources.

1 8 US8127187B2 - Method and apparatus of ATE IC scan test using FPGA-based system - Google Patents
[Link]

2 4 14 17 go/semi paper - scan intro part 1 of 2

[Link]

3 19 Fault Documentation
[Link]

5 13 23 Test-Data Volume and Scan-Power Reduction with Low ATE Interface for Multi-Core SoCs
[Link]

6 7 D:\paginated-pdfs\TCAD\32tcad09-paginated-pdfs\tcad-tenentes-2256394\tcad-tenentes-2256394-
[Link]
[Link]

9 26 Secure Scan and Test Using Obfuscation Throughout Supply Chain

[Link]

10 11 15 16 21 22 jtag/tap/rtl/verilog/tap_top.v at master · freecores/jtag · GitHub

[Link]

12 20 24 25 27 D:\paginated-pdfs\TCAD\32tcad09-paginated-pdfs\tcad-tenentes-2256394\tcad-

[Link]
[Link]

18 GitHub - mattvenn/scan_wrapper · GitHub

[Link]

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