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Exp 4 (Decoder)

The document outlines an experiment aimed at implementing and verifying a decoder using logic gates, specifically focusing on a 2 to 4 decoder. It describes the apparatus required, the theory behind decoders, and provides a procedure for conducting the experiment along with precautions to ensure accurate results. The experiment concludes with the verification of the decoder's functionality through observation of output corresponding to various input combinations.

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3 views2 pages

Exp 4 (Decoder)

The document outlines an experiment aimed at implementing and verifying a decoder using logic gates, specifically focusing on a 2 to 4 decoder. It describes the apparatus required, the theory behind decoders, and provides a procedure for conducting the experiment along with precautions to ensure accurate results. The experiment concludes with the verification of the decoder's functionality through observation of output corresponding to various input combinations.

Uploaded by

anonymoushumanitarian01
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© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT NO:4

AIM: IMPLEMENTATION AND VERIFICATION OF DECODER USING LOGIC


GATES.

APPARATUS REQUIRED: IC 7446, IC 74138 and connecting leads.


BRIEF THEORY:
In digital electronics, a combinational logic circuit that converts an N-bit binary input code into
M output channels in such a way that only one output channel is activated for each one of the
possible combinations of inputs is known as a decoder.
In other words, a combinational logic circuit which converts N input lines into a maximum of
2N output lines is called a decoder.
Therefore, a decoder is a combination logic circuit that is capable of identifying or detecting a
particular code. The operation that a decoder performs is referred to as decoding. A general
block diagram of a decoder is shown in Figure-1.

Here, the decoder has N input lines and M (2N) output lines. In a decoder, each of the N input
lines can be a 0 or a 1, hence the number of possible input combinations or codes be equal to
2N. For each of these input combinations, only one of the M output lines will be active, and all
other output lines will remain inactive.
2 to 4 Decoder
The 2 to 4 decoder is one that has 2 input lines and 4 (22) output lines. The functional block
diagram of the 2 to 4 decoder is shown in Figure-2.
2 to 4 Decoder
When this decoder is enabled with the help of enable input E, then its one of the four outputs
will be active for each combination of inputs. The operation of this 2-line to 4-line decoder can
be analyzed with the help of its truth table which is given below.

INPUT OUTPUT
EN I1 I0 Y3 Y2 Y1 Y0
1 X X 0 0 0 0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0

PROCEDURE:
1. Switch ON the trainer.
2. Give logic I/P to I0 to I1 & EN through slide switches.
3. Observe the output at Y0 and Y3 on the kit through LED.
4. For different combination of inputs observe the outputs and match them with truth
table.

RESULT: Decoder have been studied and verified.

PRECAUTIONS:

1) Make the connections according to the IC pin diagram.


2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

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