Exercise Problems
4.1 Rewrite the SPICE code for the nMOS model in Example 4.1 for a graded junction
using the following parameters:
• N A = 9.60 × 10 1 8 cm -3
• N A (sidewall) = 7.46 × 10 1 5 cm -3
• N D = 4.80 × 10 1 7 cm -3
• x j = 0.02 μm
• t ox = 6 Å
• L D = 4 nm
SOLUTION :
The zero-bias threshold voltage is measured as 0.53 V, and k’ is determined to 98.2 uA/V 2 .
The channel length modulation coefficient is λ=0.08 . The source, drain, gate, and substrate
nodes of the device are labeled by node numbers 4, 6, 12, and 7, respectively. Prepare the
device description line and the .MODEL line for SPICE simulation. Use the LEVEL 1
model, and avoid conflicting parameter definitions.
The gate oxide capacitance per unit area is
ox 3.511013
Cox 5.85 106 F / cm2
tox 6 108
The substrate bias coefficient (GAMMA) and the surface inversion potential (PHI) are
found as follows:
2 q N A Si 2 1.6 10 19 9.60 1018 1.04 10 12 1
6
0.306V 2
Cox 5.85 10
kT ni
2 F ( substrate) 2 ln
q NA
1.45 1010
2 0.026 V ln 18
1.06 V
9.60 10
Now we start to calculate the parameters needed for the parasitic capacitance descriptions.
The built-in junction potential (PB) for the bottom diffusion area is
kT N N 9.60 1018 4.80 1017
0 ln A 2 D 0.026 V ln 0.978 V
q ni 2.11020
Note that this junction potential is used for calculating all junction capacitances, which
results in an overestimation of the sidewall junction capacitance. The zero-bias depletion
capacitances associated with the bottom junction (CJ) and the side-wall junction (CJSW)
are found as
Si q N A N D 1
C j0
2 N A N D 0
1.04 10 12 F/cm 1.6 10 19 C 9.60 1018 4.80 1017 1
18 17
2 9.60 10 4.80 10 0.978
1.97 10 7 F/cm 2
Si q N A ( sw) N D 1
C j 0 sw x j
2 N A ( sw) N D 0
1.04 10 12 F/cm 1.6 10 19 C 7.46 1015 4.80 1017 1
6
2.0 10 15 17
2 7.46 10 4.80 10 0.978
5.00 10 14 F/cm
We will assume abrupt junction profiles for both the bottom junctions and the side-wall
junctions; thus, MJ = 0.5 and MJSW = 0.33. The gate overlap capacitances per unit length
(CGSO and CGDO) are calculated as:
CGSO CGDO Cox LD 5.85 10 6 4 10 7 2.34 pF/cm
Finally, we calculate the area and the perimeter (in m 2 and m, respectively) of the source
and the drain diffusion regions. Now, we can write the device description line and
the .MODEL line that correspond to this device, as follows:
M1 6 12 4 7 NM1 W=200N L=120N LD=10N AS=0.058P PS=0.98U AD=0.1492P
PD=1.7U
.MODEL NM1 NMOS ( VTO=0. 53 KP= 98.2 U LAMBDA=0. 08 GAMMA=0. 306
+ PHI= 1.06 PB=0.978 CJ= 1.97E-3 CJSW=5.00E-1 2
+ CGSO=2.34 E-10 CGDO=2.34 E-10 MJ=0.5 MJSW=0.33 )
Notice that PS and PD are calculated here by taking into account the entire perimeter of
the respective diffusion region, including the boundaries facing the gate (channel).
Similarly, AS and AD are simply taken as the bottom area of the respective diffusion
region. This approach slightly diverges from the exact capacitance calculation formulas
given in Chapter 3, and results in a minor over-estimation of the actual junction
capacitances. Yet due to the relative simplicity of calculating the area and the perimeter of
polygons (i.e., source and drain regions) defined in the mask layout, this method can
easily be applied to automatic layout parasitic extraction.
4.2 A layout of nMOS transistors in the NAND2 gate is shown. Write a SPICE
description corresponding to the layout. The diffusion region between two polysilicon
gates can be split equally between the two transistors.
SOLUTION :
The SPICE input list could be as follows:
M1 2 1 0 0 NMOS W=200N L=60N AS=0.028P AD=0.012P PS=0.68U PD=
0.32U
M2 4 3 2 0 NMOS W=200N L=60N AS=0.012P AD=0.028P PS=0.32U PD=
0.68U
4.3 Using the SPICE Level 1 MOSFET model equations, derive an expression
for the sensitivity of the drain current I D with respect to temperature.
Calculate the sensitivity at room temperature T = 300 K by using the values
in Example 4.1. For simplicity, assume that n i is independent of temperature.
Also verify your solution numerically by calculating I D at 310 K and then ∆
I D /∆T.
SOLUTION :
The sensitivity of drain current with respect to temperature T can be expressed by:
I D I D n I D VT
T n T VT T
where in SPICE level 1 model,
I D I D
n n
The mobility temperature dependence is:
n 300 K
n T 3/2
T
300
n 300 K T 5/2
n
T 200 300
For simplicity, assume V SB =0V,
QB 0 Qox
VT VT 0 GC 2F
Cox Cox
VT GC 1 QB 0
2 F
T T T C ox T
kT n
F ln i
q NA
F F
T T
kT ni 2
GC ln
q N A ND
GC GC
T T
QB 0 2qN A si 2F
QB 0 1 QB 0 F 1 QB 0
T 2 F T 2 T
In linear region,
I D C I W
n ox D 1 VDS 2VDS
VT 2 Leff
Therefore,
I 300 K T
5/2
I D
D n
VT n 200 300
nCox W 1 QB 0
1 VDS 2VDS GC 2 F
2 Leff T T Cox T
In saturation region,
I D W
n Cox 1 VDS VGS VT VT
VT Leff
I 300 K T
5/2
I D
D n
VT n 200 300
W 1 QB 0
n Cox 1 VDS VGS VT VT GC 2 F
Leff T T Cox T
At T=300K, when V DS =5V, V BS =0V, the transistor is saturated.
45 10 6 5
5 0.85 1 0.05 5 1.21mA
2
ID
2 2
I D 5 mA
2 45 10 6 1 0.25 5 0.85 0.85 0.992
VT 2 V
' 6 2
k 45 10 cm
n 8
783
Cox 5.75 10 V s
I D I D 1.21 mA
1.55 10 3 2
n n 783 cm / V s
n 1 cm 2 / V s
783 3.92
T 200 K
VT GC 1 QB 0
2 F
T T T 2C ox T
0.875 0.289 1.38 10 8 V
2 8
5.9 10 4
300 300 2 5.75 10 300 K
I D mA
T
1.55 10 3 3.92 0.992 5.9 10 4 5.49 10 3
K
Calculate ID at T=310K.
F 2.76V
GC 0.861V
QB 0
0.235V
Cox
VTO 0.846V
n 300 K cm 2
n 3/2
745
310 V s
300
745 5.75 10 8 5
5 0.846 1 0.25 1.156mA
2
ID
2 2
I D 1.156 1.21 mA
5.5 10 3
T 310 300 K
The two results are very similar.
4.4 Explain why several versions of nMOS transistor models and pMOS
transistor models coexist despite the fact that some models are more accurate
than others.
SOLUTION :
Some models are more accurate especially for short channel devices, but they
have a lot of model parameters and are thus very complicated. Some models are
less accurate and much simpler. Therefore there is a need for different purposes,
thus different models coexist.