4.

TST Rn, Operand2

TST stands for Test instruction in the ARM Instruction Set Architecture.
It is used to test bits in a register by performing a bitwise AND operation, but the result
is not stored. Instead, it updates the condition flags in the CPSR (Current Program
Status Register).

Where:

 Rn → First register operand

 Operand2 → Second operand (register or immediate value)

Operation

Rn AND Operand2

 The result is not stored in any register.

 Only the condition flags (N, Z, C, V) are updated.

Flag Meaning When it changes

N (Negative) Result is negative Set if MSB = 1
Z (Zero) Result is zero Set if result = 0
C (Carry) Depends on shifter operand Updated if shift used

V (Overflow) Not affected Remains unchanged

TST r0, #1 ; Perform bitwise AND of r0 and 1

BEQ bit_is_zero ; Branch if Z flag is set (result was 0)

1. MUL(Multiply)

MOV R1, #10

MOV R2, #5

MUL R3, R1, R2

EXAMPLE:

R1 = 10

R2 = 5

R3=R1*R2=10*5=50

R3= 50 (0x32)

2. MLA (Multiply and Accumulate)

SYNTAX:

Rd = (Rm × Rs) + Rn

EXAMPLE:

MOV R1, #10

MOV R2, #5

MOV R4, #3

MLA R3, R1, R2, R4

VALUES:

R1 = 10

R2 = 5

R4 = 3

Rd = (Rm × Rs) + Rn=(10x5)+3=50+3=53(0x35)

[RdHi, RdLo]

 RdLo → Lower 32 bits

 RdHi → Higher 32 bits

[RdHi, RdLo] = Rm × Rs

1. UMULL (Unsigned Multiply Long)

Operation:

[RdHi, RdLo] = Rm × Rs

Assembly language;

MOV R1, #2000

MOV R2, #3000

UMULL R4, R5, R1, R2 ; R5=Hi, R4=Lo

Calculation:

2000 × 3000 = 6000000

Convert to hexadecimal

6000000 = 0x005B8D80

Result:

R4 (Lo) = 0x005B8D80

R5 (Hi) = 0x00000000

Because result fits in 32 bits, high part = 0

2. UMLAL (Unsigned Multiply Accumulate Long)

Operation:
[RdHi, RdLo] = [RdHi, RdLo] + (Rm × Rs)
Assembly language:
MOV R1, #10
MOV R2, #20
MOV R4, #5 ; Lo
MOV R5, #0 ; Hi
UMLAL R4, R5, R1, R2

Calculation:
10 × 20 = 200
Previous value = 5
Total = 200 + 5 = 205
Result
R4 = 205 (0xCD)
R5 = 0
 3. SMULL (Signed Multiply Long)
Operation

[RdHi, RdLo] = Rm × Rs (signed numbers)

Assembly language
MOV R1, #-10
MOV R2, #20
SMULL R4, R5, R1, R2
Calculation:
-10 × 20 = -200
Result:
R4 (Lo) = lower 32 bits of -200
R5 (Hi) = sign extension (all 1s for negative)
Negative number stored in 2’s complement
4. SMLAL (Signed Multiply Accumulate Long)
Operation:
[RdHi, RdLo] = [RdHi, RdLo] + (Rm × Rs)
Assembly language
MOV R1, #-5
MOV R2, #10
MOV R4, #20
MOV R5, #0
SMLAL R4, R5, R1, R2
Calculation:
-5 × 10 = -50
20 + (-50) = -30
Result:
R4 = lower 32 bits of -30
R5 = sign extension

Key differences:

Instruction Type Operation

UMULL Unsigned Multiply

UMLAL Unsigned Multiply + Add

SMULL Signed Multiply

 Instruction Type Operation

SMLAL Signed Multiply + Add

3. BX (Branch and Exchange)
 Jump to address in register
 Switch between ARM and Thumb mode

It performs two operations:

1. Branch (Jump)

 Program control jumps to the address stored in register Rm

 PC = Rm & 0xFFFFFFFE

2. Exchange (Mode Switch)

 It may switch between:

o ARM mode (32-bit)
o Thumb mode (16-bit)

Important Concept (T Bit)

 T = Rm & 1 (last bit of register)

LSB of Rm Mode
0 ARM mode
1 Thumb mode

Why & 0xFFFFFFFE?

It clears the last bit (LSB) of the address

 Because instructions must be aligned

 LSB is used only to decide the mode

Syntax:

BX Rm

Working:

PC = Rm & 0xFFFFFFFE

T = Rm & 1 → decides mode (Thumb or ARM)

Example:

LDR R0, =TARGET

BX R0

TARGET

MOV R1, #100

Example 1: simple Branch

LDR R0, =TARGET ; Load address of TARGET into R0

BX R0 ; Jump to TARGET

TARGET
MOV R1, #10

Explanation:

 R0 contains address of TARGET

 BX R0 transfers control to TARGET

Example 2: Mode Switching

Assume:
R0 = 0x1001
Execution:
BX R0

What happens?

 PC = 0x1000(LSB cleared)
 T = 1 → Switch to Thumb mode

Example 3: Returning from Function

BL FUNC ; call function

FUNC

MOV R0, #5

BX LR ; return
[Link] (Branch with Link + Exchange)

Combines:

 Function call (BL)

 Mode switch (BX)

Syntax:

Syntax:
BLX label OR BLX Rm

Working:

 Jumps to target
 Saves return address in LR
 May switch mode

Example 1: Using Label

BLX FUNC

FUNC
MOV R0, #50
BX LR

Example 2: Using Register

LDR R3, =FUNC

BLX R3

FUNC
ADD R0, R0, #1
BX LR
This table shows ARM single-register load/store addressing modes. I’ll explain each type
with simple examples and step-by-step execution so it’s easy to understand.

Basic Idea
Memory address is calculated using:

1. Pre-index with Immediate Offset

LDR R0, [R1, #4]

Example:
R1 = 1000
Memory [1004] = 10
Execution:
 Address = 1000 + 4 = 1004
 R0 = 10
 R1 un change

2. Pre-index with Register Offset

Syntax:
LDR R0, [R1, R2]
 Example:
R1 = 1000, R2 = 8
Memory[1008] = 20

3. Pre-index with Scaled Register Offset

Syntax:
LDR R0, [R1, R2, LSL #2]
Load into register R0 the value from the memory address obtained
by adding R1 to R2 after shifting R2 left by 2 bits (i.e., multiplying
R2 by 4).
R0 = Memory[ R1 + (R2 × 4) ]

Example
R1 = 1000, R2 = 3
Note :
 R2 << 2 = 3 × 4 = 12
 Address = 1000 + 12 = 1012

Offset = 3 × 4 = 12

Address = 1012

Useful for arrays (word = 4 bytes)

4. Pre-index with Write back (!)

Syntax

LDR R0, [R1, #4]!

R0 = Memory[ R1 + 4 ] and then R1 = R1 + 4

Load into register R0 the value from the memory address

obtained by adding 4 to R1, and then update R1 with this
new address.
Example:
R1 = 1000
Memory[1004] = 25

Then:

 Address = 1000 + 4 = 1004

 R0 = 25
 R1 = 1004 (updated)

Core Instructions: Load vs. Store

LDR (Load Register): Moves data from memory into a register. Think
of this as "reading" from RAM.

STR (Store Register): Moves data from a register into memory.

Think of this as "writing" or "saving" to RAM.

Data Types and Suffixes

The instructions use suffixes to determine how many bits are being moved
and how they are treated (signed vs. unsigned):

Suffix Data Size Description

(None) 32-bit Word The default operation for a full register.

B 8-bit Byte Unsigned byte; the rest of the register is zeroed out.

SB 8-bit Signed Byte Loads a byte and sign-extends it to 32 bits.

H 16-bit Halfword Unsigned 16-bit data.

SH 16-bit Signed Halfword Loads a halfword and sign-extends it to 32 bits.

Syntax Breakdown

The image lists the syntax as: <LDR|STR>{<cond>}{B} Rd, addressing

<cond> : Optional condition codes (e.g., LDREQ for "load if equal").

Rd : The destination or source register.

addressing : The memory address, which can be a direct address, a

register, or a register with an offset.

Important Distinction in the Table

The table provided in your image contains a small quirk: it lists STR as
"save byte or word." Generally, in standard ARM assembly:

STR specifically handles 32-bit words.

STRB specifically handles 8-bit bytes.

STRH handles 16-bit halfwords.

Would you like me to show you some code examples of how these
different addressing modes (like [R1, #4] ) work in practice?