Very Large Scale Integration

(VLSI)
Lecture 1

Dr. Ahmed H. Madian

Ah_madian@[Link]

Dr. Ahmed H. Madian-VLSI 1

 Course Objective
You’ll get a bottom-up tour of how integrated circuits are engineered.
We’ll talk about
 MOSFETs: how they work, how they’re built, effects of new
technologies
 Various design and layout techniques, from the ordinary to the
most complex, for creating combinational and sequential circuits,
datapaths, memories, buffers, regular logic structures, …etc.
 how you tackle the problem of designing circuits with 1,000,000
gates -- you’re not in Digital IC Technique anymore!
 Give different testing techniques for VLSI circuits.

Dr. Ahmed H. Madian-VLSI 2

 Administrative Rules
 Course schedule:
 Lectures:
 Saturday (3rd slot), 12:30 - 13:45
 Tuesday (4th slot), 14:15- 15:45
 Office hours: Saturday 14:30 - 16:30 (C3.221)
 Teaching assistant: Eng. Mona Guindy
 Grading
 Quizzes & Assignments: 20%
 Assignment of every lecture is due the following lecture
 Final exam: 80%

Dr. Ahmed H. Madian-VLSI 3

References
 Anantha Chandrakasan, William J. Bowhill, Frank Fox,
“Deign of high performance microprocessor circuits”

 John P. Uyemura, “Introduction to VLSI circuits and

systems”
 Or any VLSI references

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 Course outline
 Overview of VLSI
 Technologies for Micro- and Nanostructures
 Low-Voltage and power design
 Synchronous and Asynchronous Circuit Design
 Architectures for VLSI Applications
 Test and Measurement Techniques for VLSI
Circuits

Dr. Ahmed H. Madian-VLSI 5

 What is VLSI?
 VLSI stands for (Very Large Scale Integrated
circuits)
 Craver Mead of Caltech pioneered the filed of VLSI
in the 1970’s.
 Digital electronic integrated circuits could be
viewed as a set of geometrical patterns on the
surface of a silicon chip.
 Complexity could thus be dealt with using the
concept of repeated patterns that were fitted
together in structured manner.

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 VLSI History

•Jack Kilby, working at Texas Instruments, first dreamed up the idea of a

monolithic “integrated circuit” in July 1959. By the end of the year, he had
constructed several examples, including the flip-flop shown in the patent
drawing above. Components are connected by hand-soldered wires and
isolated by “shaping” and pn diodes used as resistors.

Dr. Ahmed H. Madian-VLSI 7

 VLSI History (cont.)
 1961: TI and Fairchild introduced the first logic IC’s (cost
~$50 in quantity!). This is a dual flip-flop with 4 transistors.

 1963: Densities and yields are improving. This circuit has

four flip flops.

In 1970, making good on its promise to its

investors Intel starts selling a 1K bit RAM,
the 1103.

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 VLSI History (cont.)
 Introduced in 1972, the 8008 had 3,500
transistors supporting a byte-wide data
path. Despite its limitations, the 8008
was the first microprocessor capable of
playing the role of computer CPU as
demonstrated on the cover of the July
‘74 issue of Radio-Electronics.

Dr. Ahmed H. Madian-VLSI 9

 Today
 Many disciplines have
contributed to the current
VLSI designs:
 solid-state physics
 materials science
 lithography and fab
 device modeling
 architecture
 algorithms
 CAD tools
 circuit design & layout

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 Chip Complexity
Chip classification according to number of active elements and minimal feature size:

Dr. Ahmed H. Madian-VLSI 11

 VLSI Chip Types
 Full custom
Every circuit is custom designed
 Application-specific integrated circuits
(ASICS) Design is created using a
standard CAD tools without the need to
interact with the silicon structure
 Semi-custom
In between of full-custom and ASIC-type
circuits. The majority of the chip is designed
using a primitive predefined cells (standard
cells) from library as building blocks.
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 Initial concept
Top design level System specifications

Abstract High-level model System design

VHDL, Verilog, HDL and verification

Design Logic synthesis

Logic design
and verification
hierarchy
overview CMOS design
Circuit design and verification

bottom design level Silicon logic design

physical design and verification

Mass production,
Manufacturing testing and
packaging

Finished VLSI chip Marketing

Dr. Ahmed H. Madian-VLSI 13
 Initial concept
Top design level System specifications

Abstract High-level model System design

VHDL, Verilog, HDL and verification

Logic design
Logic synthesis and verification

VLSI CMOS design

Circuit design
Design and verification

bottom design level Silicon logic design

physical design and verification

Mass production,
Manufacturing testing and
packaging

Finished VLSI chip Marketing

Dr. Ahmed H. Madian-VLSI 14
 VLSI Challenges
The Moore’s Law (Moore is one of the co-founder of Intel corp.)
has been fundamental to the silicon industry, obeyed for the past
30 years; however, technology scaling will become difficult
beyond 0.18 micron, threatening Moore’s Law.

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 Scaled-down Transistors

The principle of constant-filed

scaling lies in scaling the device
voltages and the device dimensions
(both horizontal and vertical) by the
same factor , k (>1) , such that the
electric filed remains unchanged.

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 VLSI Challenges (cont.)
Design Challenges of Technology
Scaling
 Technology models 0.5µm, 0.35µm, 0.25µm,
0.18µm, 0.13µm, 90nm, 65nm, 45nm, 32nm,
20nm, ???.
 Scaling factor of 0.7 in the dimension exist from
generation to the next one.
 Scaling in Area = 0.7 X 0.7 = 0.490.5. This means
the transistor density doubles every generation.

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Challenges of VLSI (cont.)
Every Two years:
1. Capacitance per node reduces by 30% (usual scaling)
2. Electrical nodes in a given area increase by 2X
3. Die size grows by 14% every two years (Moore’s Law)
4. Supply voltage reduces by 15% every two years
5. And frequency increases by 2X.
 This all adds up to 2.7X increase in active power of the
lead microprocessor every two years.

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 Revision on MOSFET
Fabrication procedure

Dr. Ahmed H. Madian-VLSI 19

 Building MOSFET
 bulk CMOS with a p-type substrate:
slice of a silicon ingot that has been
doped with an acceptor (typically
boron) to increase the concentration of
holes

P-type

Back is metallized to provide

a good ground connection.
Dr. Ahmed H. Madian-VLSI 20
 Building MOSFET (cont.)
 Next, a “thick” layer of silicon dioxide, called field oxide,
is formed on the surface by oxidation in wet oxygen.
This is then etched to expose surface where we want to
make a MOSFET:

Dr. Ahmed H. Madian-VLSI 21

 Building MOSFET (cont.)
 Now grow a “thin” layer of silicon dioxide, called
gate oxide, on the surface by exposing the wafer
to dry oxygen.

Dr. Ahmed H. Madian-VLSI 22

 Building MOSFET (cont.)
 On top of the thin oxide a thick layer of polycrystalline silicon,
called polysilicon or poly for short, is deposited by CVD. The
poly layer is patterned and plasma etched exposing the
surface where the source and drain junctions will be formed

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 Building MOSFET (cont.)
 The entire surface is doped, either by diffusion or ion
implantation, with phosphorus (an electron donor) which
creates two n-type regions in the substrate. The phosphorus
also penetrates the poly reducing its resistance and affecting
the nfet’s threshold.

n+ n+

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 Building MOSFET (cont.)
 Finally an intermediate oxide layer is grown and
then reflowed to flatten its surface. Holes are
etched in the oxide (where contacts to poly/diff
are wanted) and aluminum deposited, patterned
and etched.

n+ n+

Dr. Ahmed H. Madian-VLSI 25

 Threshold voltage
 The gate voltage required to form the channel is called the
threshold voltage. Many factors affect the gate-source voltage at
which the channel becomes conductive. Threshold voltage for
source-bulk voltage zero:
Qb Qox
VTo   GC  2 F  
Cox Cox
As Vsb increases, the depth of the depletion region increases, exposing more
of the fixed acceptor (i.e. negative) ions in the substrate.

VT  Vtno    VsB  2F  2F  where  

2 si qN A
Cox
Where F is the Fermi potential, Qb is the depletion region charge,  is the
substrate coefficient and VSB is the substrate bias voltage
Dr. Ahmed H. Madian-VLSI 26
Channel-Length modulation

Dr. Ahmed H. Madian-VLSI 27

 SPICE Models
 There are different models used in circuit
simulators:
 level 1 is our simple model including the most
important second order effects described
 level 2 model is based on device physics
 level 3 is a semi-empirical model allowing to
match equations to the real circuit: example
BSIM model from Berkeley models
subthreshold characteristics.

Dr. Ahmed H. Madian-VLSI 28

 Physical design
 CMOS ICs are electronic switching
networks that are created on small area of
silicon wafer using complex set of physical
and chemical processes.
 A primary task for VLSI designer is to
translate circuit schematics into silicon
form (this process is called physical design)

Dr. Ahmed H. Madian-VLSI 29

Integrated Circuit Layers
 ICs are made by Layer M1
stacking different layers
of materials in a specific
order to form three Insulator
dimensional structures
that act as an electronic
switching network. Substrate

M1 M1
Substrate
Side view Top view
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 Integrated Circuit Layers (cont.)

Layer M2 Layer M1
Layer M1 insulator

Substrate Layer M2
Side view
Top view

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 Designing NFET Arrays layout
B C
 Devices can share A

patterned regions, n+ n+ n+ n+ n+ n+
which may reduce
the layout area or
complexity
n+ n+ n+ n+

A B C

Dr. Ahmed H. Madian-VLSI 32

 Designing PFET Arrays layout
B C
 Devices can share A

patterned regions, p+ p+ p+ p+ p+ p+
which may reduce
the layout area or N-well

complexity
p+ p+ p+ p+

A B C

Dr. Ahmed H. Madian-VLSI 33

Design Examples VLSI
 Draw the CMOS realization and the
layout of NAND and NOR gates
 Colors of layers
polysilicon (gates) : Red
Doped n+/p+ (active) : Green
N-Well : Yellow
Metal 1 : BLUE
Metal 2 : Grey
Contacts : Black X’s
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 CMOS Realization
VDD VDD

a
F  a.b b a
F  ab b

NAND gate CMOS realization NOR gate CMOS realization

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 NAND FET Layout
VDD
N-WELL
PFET Gate P+
P+ Gate P+
a
b

NFET N+ Gate N+ Gate N+

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 NAND FET Layout (cont.)
VDD
VDD

PFET
X X a
b

NFET X

GND
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 NAND FET Layout (cont.)
VDD
VDD

PFET
X X X a
b
OUT
NFET X X
a b
GND
Dr. Ahmed H. Madian-VLSI 38
 NOR FET layout
VDD
VDD

PFET
X X

a
OUT
b
NFET X X X
a b
GND
Dr. Ahmed H. Madian-VLSI 39
Design Examples VLSI
 Draw the pass transistor realization
and the layout of MUX 4:1
 Colors of layers
polysilicon (gates) : Red
Doped n+/p+ (active) : Green
N-Well : Yellow
Metal 1 : BLUE
Metal 2 : Grey
Contacts : Black X’s
Dr. Ahmed H. Madian-VLSI 40
 CMOS realization of MUX 4:1
S1 S1 S0 S0

P0
P0

P1
MUX F
P2 4:1 P1
F
P3

S0 P2
S1

P3

Dr. Ahmed H. Madian-VLSI 41

 MUX layout
S1 S1 S0 S0 S1 S1 S0 S0

P0
X X
P0 X X

P1
P1 X X X
F F

X X
P2
P2 X X

X
P3 X X P3

Dr. Ahmed H. Madian-VLSI 42

Design Examples VLSI
 Draw the CMOS realization and the layout of
logic function
f  a  b. c
 Colors of layers
polysilicon (gates) : Red
Doped n+/p+ (active) : Green
N-Well : Yellow
Metal 1 : BLUE
Metal 2 : Grey
Contacts : Black X’s
Dr. Ahmed H. Madian-VLSI 43
CMOS Realization
VDD

b c

a
f

b
a

Dr. Ahmed H. Madian-VLSI 44

 Logic function Layout
VDD
N-Well

b c
PFET
P+

a
f

b
a
NFET N+
c

Dr. Ahmed H. Madian-VLSI 45

 Logic function Layout
VDD
N-Well VDD
c b a b c
PFET
X X X
a
f

b
a
NFET
c

Dr. Ahmed H. Madian-VLSI 46

 Logic function Layout
VDD
N-Well VDD

PFET c b a b c
X X X X

a
f

f b
a
NFET X X X
c
GND

Dr. Ahmed H. Madian-VLSI 47

 Layout Rules
 Layout rules are the common language between design and
process engineers
 conservative rules absorb process disturbances and variations
 layout rules must be respected by the designer
 layout rules reflect the limits of a process, they describe:
 minimal distance, overlap
 minimal width (e.x. channel length, λ)
 layout readability is improved using colors:
 metal blue
 polysilicium red
 n-diffusion green
 p-diffusion yellow
 n-well brown
 contact, via black

Dr. Ahmed H. Madian-VLSI 48

Layout

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 Stick Diagram
 stick diagrams are
technology independent
 no layout rules need to
be known
 mask layout may be
generated automatically

Dr. Ahmed H. Madian-VLSI 50

Digital Layout: horizontal or vertical
gates?

 Vertical gates  Horizontal gates

 Good for circuits where fets  Good for circuits where long and short
sizes are similar and each fets are needed or where nodes must
gate has limited fanout. Best control many fets. Often used in
choice for multiple input static multiple-output complex gates (e.g,
gates and for datapaths. sum/carry circuits).

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Eliminating Gaps

Dr. Ahmed H. Madian-VLSI 52

Complex CMOS Gates compact
layout.
 Euler Rule:
 Generate an n-graph by replacing the nfet block
with vertices for nodes and edges for fets
 Generate a dual p-graph
 Find a sequence containing all edges in the n-
graph. This sequence is called Euler n-path.
 Generate an Euler p-path with the same labeling
as the Euler n-path. If not possible start again.
 The labeling sequence of the 2 Euler paths are the
gate sequence of the single row nfet/pfet CMOS
gate.

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 Example
 Draw the most compact layout for the
following logic function using Euler’s rule.

F= A.(B+C)

Dr. Ahmed H. Madian-VLSI 54

 Solution
VDD
F
C A
N1
A

N2
B
F VDD F
A
C B
N2
N1
C B

GND GND A  B  C

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 Layout of Example

A  B  C

A B C

Dr. Ahmed H. Madian-VLSI 56

Thanks
 Revision sheet will be soon available on
the web site
 you must solve it
 Download one of the layout tools and
practice on the lecture examples

Dr. Ahmed H. Madian-VLSI 57